Spartan board user manual
Contents
1. r39 139 172 ch a 31 81 59 r40 140 171 ch a 32 82 61 41 141 169 ch a 33 83 62 r42 142 168 ch a 34 84 63 r43 143 167 ch a 35 85 64 r44 144 166 ch a 36 86 65 r45 145 165 ch a 37 87 67 r46 146 164 ch a 38 88 68 r47 147 163 ch a 39 89 69 r48 148 162 ch a 40 90 70 r49 149 161 ch a 41 91 72 r50 150 159 ch a 42 92 73 ch a 1 51 15 ch a 43 93 74 ch a2 52 17 ch a 44 94 75 ch a 3 53 19 ch a 45 95 76 ch a 4 54 20 ch a 46 96 80 5 55 21 ch a 47 97 81 ch a 6 56 22 ch a 48 98 82 cha 7 57 23 ch a 49 99 83 ch a 8 58 24 ch a 50 100 84 ch a 9 59 27 ch b 1 1 85 ch a 10 60 28 ch b 2 2 87 ch a 11 61 29 ch b 3 3 88 ch a 12 62 30 ch b 4 4 89 ch a 13 63 31 ch b 5 5 90 ch a 14 64 32 ch b 6 6 92 15 65 34 b 7 7 93 ch a 16 66 35 ch b 8 8 94 ch a 17 67 36 chb9 9 95 ch a 18 68 37 ch b 10 10 96 ch a 19 69 39 ch b 11 11 97 cha 20 70 40 ch b 12 12 98 ch a 21 71 41 ch b 13 13 99 ch a 22 72 42 ch b 14 14 100 ch a 23 73 43 ch b 15 15 101 ch a 24 74 44 ch b 16 16 107 ch a 25 75 45 ch b 17 17 109 ch a 26 76 46 ch b 18 18 110 ch a 27 77 47 ch b 19 19 111 ch a 28 78 48 ch b 20 20 1122. 19 Table 16 Dedicated signals on connector 19 Table 17 Pin assignment of XCS 20 30 40 FPGA in PQ 208 package 24 ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 98061 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 5 5 1 Introduction This manual describes the specific properties of the board module like power supply FPGA configuration clocks reset LEDs DIP switches and 1 signals Please take information about the FPGA from the Xilinx literature see chapter 4 Literature Online information can be found on the Xilinx websites http www xilinx com and http www support xilinx com Information about new products and new developments can be found on the ErSt Electronic Website http www erst ch If you have questions you may write to the following E mail address info erst ch ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 6 6 2 Overview 2 1 99999999999 Key Features Xilinx FPGA Spartan XCS40 30 20 BV or XCS40XL 30XL 20XL 3 3V in PQ 208 package Header connector for Xchecker cable Header connector for external daisy chain connections SPROM for FPGA Master Serial Mode DIL 8 package with socket Quarz oscillator up to 80 MHz DIL 8 or DIL 14 versions possible Four position DIP switch for user configuratio
3. 64 102 SGCK3 65 103 GND 66 GND 104 DONE 67 105 VCC 68 106 PROGRAM 69 107 I O 70 108 PGCK3 71 VCC 109 72 110 73 111 l O 74 112 75 113 I O Aeschstrasse 171 CH 8123 Ebmatingen Fax Telefon 41 1 980 61 44 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 114 24 24 115 116 117 118 GND 119 120 121 VCC 122 123 124 125 126 127 128 129 130 VCC 131 GND 132 133 134 135 134 137 138 139 140 141 142 143 GND 144 145 146 147 VO 179 l O 148 YO 180 1 0 149 1 0 181 1 0 150 1 0 182 GND 151 VO 183 152 1 0 184 1 0 153 VO DIN 185 1 0 154 YO 186 O SGCK4 DOUT 187 1 0 155 CCLK 188 1 0 156 189 1 0 157 O TDO 190 1 0 158 GND 191 1 0 159 1 0 192 160 193 1 0 161 1 0 194 l O 162 1 0 195 GND 163 1 0 196 1 0 164 1 0 1
4. 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 23 23 5 Appendix A Pin Assignment of XCS 20 30 40 FPGA Active low signals are marked with a at the end of the name Pin Description 1 GND 2 O PGCK1 3 4 5 6 TDI 7 8 9 10 11 12 13 GND 14 15 16 TMS 17 18 VCC 19 20 21 22 23 24 25 GND 26 VCC 27 28 VO 29 30 IVO 31 32 33 VCC 34 IVO 35 36 37 ErSt Electronic GmbH 38 GND 76 39 77 VO INITY 40 78 VCC 41 79 GND 42 80 43 81 44 82 45 83 46 84 47 85 48 86 VCC 49 SGCK2 87 50 Don t connect 88 51 GND 89 52 MODE 90 53 VCC 91 GND 54 Don t connect 92 55 PGCK2 93 56 l O HDC 94 57 95 58 96 59 97 60 l O LDOY 98 61 99 62 100 63 101
5. ch a 29 79 57 ch b 21 21 113 ch a 30 80 58 ch b 22 22 114 ErSt Electronic GmbH Aeschstrasse 171 Telefon CH 8123 Ebmatingen Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALXCS User Manual 19 19 3 8 Dedicated Signals ch b 23 23 115 ch b 39 39 135 ch b 24 24 116 ch b 40 40 136 ch b 25 25 117 ch b 41 41 137 ch b 26 26 119 ch 42 42 138 ch_b_27 27 120 ch b 43 43 139 ch b 28 28 122 ch b 44 44 141 ch b 29 29 123 ch b 45 45 142 ch b 30 30 124 ch b 46 46 144 ch b 31 31 125 ch b 47 47 145 ch b 32 32 126 ch b 48 48 146 ch b 33 33 127 ch b 49 49 147 ch b 34 34 128 ch b 50 50 148 ee j 2 129 Table 15 General I O signals ch b 37 37 133 ch b 38 38 134 The header connector ST1B contains some dedicated signals which are used as clock and configuration signals Signal Name ST1B Pin Connected to FPGA pin pgck_ext 52 2 over J2 pgck2 54 55 pgck3 56 108 pgck4 58 160 sgck1 60 207 sgck2 62 49 sgck3 64 102 tdi 68 6 tck 69 7 tms 70 16 tdo 71 157 hdc 73 56 Idc 74 60 dup 76 N A goes to
6. 14 packages Pin 1 is common for both types of packages Oscillators of the VCXO type need a control signal at pin 1 Uc To get a closed feedback loop this signal must be connected via FPGA to Usu Osz Net Name FPGA Pin FPGAI O Ue 27 Output Uot pgck 2 Clock Input Table 11 Quarz oscillator signals 3 4 Reset Button A functional reset can be issued at any time by pressing the push button T1 The reset signal is active high and needs to be considered in the design appropriately If no reset function is needed the button may be used for arbitrary purposes Button Net Name FPGA Pin T1 reset 56 Table 12 Reset signal ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 16 16 Note 1 Note 2 Note 3 A manual reset initialises the internal circuits of the FPGA registers counters finite state machines etc and must be implemented in the design appropriately Do not press the reset button during the download of a bit stream since this may interfere with the HDC function When used in a stack all HDC pins of all FPGAs are connected in parallel Unconfigured FPGAs tie this pin to high level and act therefore like a pressed reset button Make sure to configure this pin as an input if the reset function is desired 3 5 LEDs The eight LE
7. Name FPGA Pin 1 swi 149 2 sw 150 3 s3 151 4 sw 152 Table 14 DIP switch 3 7 Stimuli and Monitoring Signals The signals ch a 1to ch a 50 ch b 1to ch b 50andr 1tor 50are routed to header connectors All these pins may be used as stimuli and monitoring signals The following table shows the assignment of the FPGA pins to the connector pins IN N Connector FPGA 19 119 197 et ST2B ST2A Pin r20 120 196 a 0 14 r21 121 194 r2 102 12 r22 122 193 r3 103 11 r23 123 191 r4 104 10 r24 124 190 r5 105 9 r25 125 189 r6 106 8 r26 126 188 r7 107 5 r27 127 187 r8 108 4 28 128 186 r9 109 3 r29 129 185 r10 110 206 r30 130 184 r 11 111 205 E33 131 181 r12 112 204 r32 132 180 r13 113 203 r33 133 179 r14 114 202 r34 134 178 15 115 201 r35 7135 177 r16 116 200 r36 136 176 r17 117 199 r37 137 175 r 18 118 198 r38 138 174 ErSt Electronic GmbH Aeschstrasse 171 CH 8123 Ebmatingen Telefon Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALXCS User Manual 18 18
8. inserted Table 9 Clock sources 3 3 1 External Clock The assignment of the clock signals to the connectors pins is shown in the following table Signal Name Connector ST1B FPGA Pin Termination Resistor pgck1 52 2 R18 pgck2 54 55 R19 pgck3 56 108 R20 pgck4 58 160 R21 sgck1 60 207 R22 sgck2 62 49 R23 sgck3 64 102 R24 sgck4 dout not connected 154 Table 10 External clock signals and termination resistors 3 3 1 1 Termination Resistors The clock signals pgck1 to pgck4 and sgck1 to sgck3 may be terminated with resistors R18 to R24 which are connected immediately from the FPGA pin to ground These resistors form a parallel termination The values of the resistors should match the impedance of the circuit board trace which has a nominal value of 100 Ohms Please consider the maximal output current capability of the clock source The resistors SMD size 0805 can be soldered to the board directly beneath the FPGA on the bottom side of the PCB Figure 5 shows the positions ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 15 15 5 Figure 5 Positions of the termination resistors 3 3 2 Internal Clock Quarz Oscillator Since the clock frequency depends strongly on the application the oscillator must be exchangeable The oscillator socket can hold DIL 8 or DIL
9. status messages error messages etc Figure 1 shows the above described function blocks ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 9 9 3 Technical Information 3 1 Power Supply The power supply of a single module or a whole stack comes from the power connector ST5 The negative pole is on the side of the power LED the screw of the positive pole is marked with red color Within a stack any power connector can be used since all boards are connected together over the header connectors Caution Use only board modules within a stack which are specified for the same supply voltage 1 un inim E i AX Figure 2 Polarity of the power connector The power supply voltage is 5V for modules which are equipped with an FPGA of the XCS 20 30 40 family If the XCS 20XL 30XL 40XL family is used the power supply voltage is 3 3V The supply voltages are also available on certain pins of the header connectors verf gbar Table 1 and Table 2 list the supply voltages Only certain voltages are available depending on the used FPGA family Spartan or SpartanXL and the usage of the board module with or without usage of a base board ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 10 10 Signal Name
10. 97 VO 165 1 0 198 1 0 166 1 0 199 1 0 167 VO 200 168 201 169 1 0 202 1 0 170 GND 203 171 YO 204 172 1 0 205 1 0 173 VCC 206 1 0 174 YO 207 SGCK1 175 VO 208 176 177 YO 178 Table 17 Pin assignment of XCS 20 30 40 FPGA in PQ 208 package ErSt Electronic GmbH Aeschstrasse 171 Telefon CH 8123 Ebmatingen Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALXCS User Manual 25 25 6 Appendix B Schematic Diagram and PCB Layout The following pages show some technical details of the board Top overlay silk screen Layout signal layers Schematic diagram ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch
11. Connector Pins on STIA 5V 1 2 3 4 5 36 37 38 39 40 3 3V 6 7 8 9 10 41 42 43 44 45 GND 11 12 13 14 15 21 22 23 24 25 31 32 33 34 35 46 47 48 49 50 12V 16 17 18 19 20 12V 26 27 28 29 30 Table 1 Supply voltages on ST1A Signal Name Connector Pins on ST2C 5V 111 112 113 114 115 146 147 148 149 150 3 3V 106 107 108 109 110 141 142 143 144 145 GND 101 102 103 104 105 116 117 118 119 120 126 127 128 129 130 136 137 138 139 140 12V 131 132 133 134 135 12V 121 122 123 124 125 Table 2 Supply voltages on ST2C Connector Pin Numbers 11 12 13 14 15 STIA 21 22 23 24 25 31 32 33 34 35 46 47 48 49 50 101 102 103 104 105 ST2C 116 117 118 119 120 126 127 128 129 130 136 137 138 139 140 ST1B 51 58 55 57 59 61 63 65 67 72 75 78 Table 3 Ground pins on all connectors ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 11 11 3 2 FPGA Configuration There are two options to configure the FPGA The following table shows the possible modes and the jumper settings of J1 and J2 Mode Data J1 Mode J2 CCLK Daten Comment Master Serial inserted not inserted Output Bit serial SPROM DIL 8 Slave Serial notins
12. Ds D3 to D10 are intended as optical indicators for the display of status information D2 is connected to the DONE pin of the FPGA and D1 serves as power indicator LED The DONE LED turns on at the end of a successful bit stream download The LEDs D3 to D10 turn on whenever the corresponding FPGA output is low The following table shows the assignment to the FPGA pins Note LED Net Name FPGA Pin D3 chai 15 D4 cha2 17 D5 cha3 19 D6 cha4 20 D7 chad 21 D8 cha6 22 D9 23 010 cha8 24 Table 13 LED signals If the board module is used within a stack the LEDs of all levels are connected in parallel If one LED is driven by the FPGA the LEDs of the other levels are driven also The maximal output current of 20mA of an FPGA port is sufficient for up to four levels If more than four levels are used the current limiting resistors of the LEDs of the remaining levels must be removed ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 1717 3 6 DIP Switch The four position DIP switch S1 can be used for application specific purposes In the On position the connected FPGA pin is tied to ground In the Off position the connected FPGA pin is pulled to VCC via a resistor The assignment of the switches to the FPGA pins is as follows Switch Net
13. EVALXCS User Manual Board Module for FPGA Family ErSt Electronic GmbH Aeschstrasse 171 Telefon CH 8123 Ebmatingen Fax Internet 41 1 980 61 44 41 1 980 61 30 http www erst ch EVALXCS User Manual 2 2 Manual EVALXCS Version 1 1 August 1999 EVALXCS Version 1 2 October 1999 This manual describes the technical properties and the usage of the following products versions EVALXCS 20 Version 1 0 April 1999 EVALXCS 30 Version 1 0 April 1999 EVALXCS 40 Version 1 0 April 1999 3 3V versions EVALXCS 20XL Version 1 0 April 1999 EVALXCS 30XL Version 1 0 April 1999 EVALXCS 40XL Version 1 0 April 1999 ErSt Electronic GmbH 1999 The ErSt Electronic GmbH reserves the right to make changes and improvements of the product without notice Important Note The EVALXCS board module has been designed and tested exclusively for the usage as a development tool In particular strong electromagnetic radiation may be produced The ErSt Electronic GmbH does not undertake any liability for damages which may result from an improper use of this product ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Man
14. GAs XAPP091 Configuring Mixed FPGA Daisy Chains XAPP015 Using the Readback Capability XAPP017 Boundary Scan in Xilinx Devices Application Briefs ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 22 22 XBRF001 SelectRAM Flexibility with Speed XBRF002 Low Power Benefits Overview XBRF003 SelectRAM Maximum Configurability XBRF007 Xilinx FPGAs The Best Choice for Delivering Logic Cores XBRF014 A Simple Method of Estimating Power in FPGAs Data Book Spartan and SpartanXL Series Datasheet v1 4 1 99 Spartan Serial Configuration PROMs Datasheet v1 2 9 98 Xcell Articles The 3 3V SpartanXL FPGA Series Invades New Territory with High Speed and Low Cost Q4 98 FPGAs Can Be an Effective Alternative to Mask Gate Arrays Q4 98 New Spartan 4 Devices for High Speed Applications Q3 98 Esaote Biomedica A Spartan Success Story Q3 98 The Low Cost PCI Solution Q3 98 Spartan Series Takes the Lead with Low Power Q2 98 Designing with the Spartan Series FPGAs Q2 98 Introducing the New Spartan FPGA Family for Low Cost Applications Q1 98 Xilinx DSP LogiCORE Advantages Q3 97 SelectRAM Memory Advantages and Uses 96 Synchronous RAM Improves System Speed Q4 95 Synchronous RAM Timing Q4 95 Advanced Carry Logic Techniques Q2 96 ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen
15. ent of XCS 20 30 40 FPGA 23 6 Appendix B Schematic Diagram and PCB Layout 25 ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 44 Figures Figure 1 Block diagram of the board module esee 7 Figure 2 Polarity of the power connector 9 Figure 3 XChecker Cable eii cie ann eee ence terere t 12 Figure 4 External daisy chain nenne 13 Figure 5 Positions of the termination resistors eese eene 15 Tables Table 1 Supply voltages on 10 Table 2 Supply voltages on ST2C sese nennen 10 Table 3 Ground pins on all connectors eese 10 Table 4 Configuration Modes esee eene 11 Table 5 Master Serial Mode 11 Table 6 Slave Serial Mode eese enne nne nennen 11 Table 7 XChecker pin assignment eese 12 Table 8 Pin assignment of the daisy chain connector 514 13 Table 9 Clock sources sans iei qe EE Rege Ende 14 Table 10 External clock signals and termination 14 Table 11 Quarz oscillator signals 15 Table 12 Reset signal iiid ERR E pe ERR tpe 15 Table 13 LED signals asusa wakaka dle i doce uai ER depre eade Ep genet 16 Table 142 DIP switch dea een ae e tud tae aote e dice 17 Table 15 General I O
16. erted inserted Input Bit serial XChecker PC Table 4 Configuration Modes 3 2 1 Master Serial Mode The board module contains an 8 pin DIL socket for Serial Configuration PROMs SCPs The jumper settings for the master serial mode are as follows J1 Data J2 Mode inserted notinserted Table 5 Master Serial Mode Note The XChecker cable must be disconnected to avoid a contention between CCLK and DIN 3 2 2 Slave Serial Mode For this form of FPGA configuration you need an XChecker cable from XILINX which serves as interface between the board module and the PC see Figure 2 The jumper settings for the slave serial mode are as follows J1 Data J2 Mode notinserted inserted Table 6 Slave Serial Mode ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 1242 I ee iret un Due emma d ponent vade Figure 3 XChecker Cable The following table shows the pin assignment of the header connector ST3 ST3 Header Connector XChecker Connector 1 PROG DONE INIT CCLK DIN VCC GND Table 7 XChecker pin assignment NOT Po ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Man
17. ns Push button for reset signal application or arbitrary usage Eight LED display for status messages 2 pole power connector for 5V 3 3V power supply 4 layer PCB Clock signals may be equipped with termination resistors Stand alone usage of the board module possible The module has a standard size of 15cm x 10cm and a digital interface compatible with future products 3x50 pole header connectors 2 54mm grid spacing on each long side of the PCB header connectors stand off from the top side of the PCB the socket connectors from the bottom side Modules may be stacked to form a tower 2 2 Applications 999999999 ASIC emulation Error monitoring and analysis Digital PLLs PWM controller Adaptive digitale filters Signal multiplexer Stimuli generators High speed encoder decoder Memory controller Interface controller ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 77 2 3 Function Description The board module EVALXCS PQ208 is an ideal tool to test complex digital circuits during the early states of their development The various configuration options of the Xilinx FPGAs allow the easy implementation of applications The hardware configuration may be loaded via XChecker or SPROM Almost all pins of the FPGA are routed to header connectors a total of 150 signals These signals may be used as inpu
18. nual 21 21 4 Literature The following list is an excerpt from the Xilinx literature concerning the Spartan FPGA family The correspondent PDF files may be downloaded directly from http www xilinx com apps spartapp htm or be requested from a Xilinx distributor Application Notes XAPP120 How Spartan Series FPGAs Compete for Gate Array Production XAPP125 Conserving Power With Auto Power Down Mode in SpartanXL FPGAs XAPP124 Using Manual Power Down Mode With SpartanXL FPGAs XAPP123 Using Three State Enable Registers in XLA XV and SpartanXL FPGAs 99 How to Design Today for the Upcoming SpartanXL FPGA Family XAPPO088 I O Characteristics of the XL FPGAs SelectRAM Memory XAPP065 Edge Triggered and Dual Port RAM Capability XAPP057 Using SelectRAM Memory in FPGAs XAPP053 Implementing FIFOs in RAM XAPP051 Synchronous and Asynchronous FIFO Designs XAPP052 Efficient Shift Registers LFSR Counters and Long Pseudo Random Sequence Generators Carry Logic XAPP013 Using the Dedicated Carry Logic XAPP023 Accelerating Loadable Counters XAPP018 Estimating the Performance of Adders and Counters XAPP014 Ultra Fast Synchronous Counters XAPP027 Implementing State Machines in FPGA Devices Configuration XAPP126 Data Generation and Configuration for Spartan Series FPGAs XAPP098 The Low Cost Efficient Serial Configuration of Spartan FPGAs XAPP122 The Express Configuration of SpartanXL FP
19. pin 1 of ST4 ddown 77 N A goes to pin 4 of ST4 Table 16 Dedicated signals on connector ST1B ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 20 20 3 9 Stack Extension When several board modules are stacked the signal direction of I O pins of different levels must be choosen very carefully Short circuits between the FPGAs may result in damages or shortens their life Unconfigured pins of the FPGA are in a high impedance state During the assembly of the stack you should pay attention to the fact that the pins of one module are aligned exactly with the holes of the sockets of the other module A good possibility to accomplish this is the usage of two pieces of a prototyping board Each of these pieces should have three rows with 50 holes Before the assembly these pieces are slided up to the ends of the connector pins Thereby the pin ends keep their positions To disassemble a stack we recommend the usage of pliers which are used to remove locking rings The claws of the pliers should be covered with plastic or rubber tubes to prevent damages on the boards The modules are then separated easily by repeated application of gentle pressure with the pliers on all four corners ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Ma
20. ts or outputs Several board modules may be stacked to form a tower which enables one to realise circuits whose demand of gates is beyond the scope of a single FPGA By using an external daisy chain connection the whole stack can be configured at once with a single download operation Quarz oscillator External clock sources with socket Quarz Oscillator 150 I Os N Four position DIP switch Done LED Display with eight LEDs Manual Reset Figure 1 Block diagram of the board module ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 8 8 Seven clock sources can be used whereas one clock source is either the internal quarz oscillator or an external clock source The quarz oscillator is inserted in a socket and can therefore be exchanged easily Both DIL 8 and DIL 14 packages can be used All clock signals may be terminated parallel termination to ground with termination resistors These resistors can be mounted by the user on the bottom side of the PCB A four position DIP switch is available for user defined purposes There is also a push button whose primary intent is to serve as a reset button Since this button is connected to a general I O pin it may be used for arbitrary functions An LED row with eight SIDELEDs is able to display
21. ual 13 13 3 2 2 1 Daisy Chain A whole stack may be configured with a single download To accomplish this the individual layers must be connected in form of a daisy chain External connections of appropriate pins of connector ST4 perform this task see Table 8 STA Connector Pin Name 1 dup 2 di 3 dout 4 ddown Table 8 Pin assignment of the daisy chain connector ST4 Use the following connection scheme dup din dout ddown OG QDI OMS Of tas waz QDS Figure 4 External daisy chain connections The easiest way to make the connections dup din and dout ddown is to insert a jumper However these connections are only needed if the stack is connected to a main board and if the configuration data comes from the main board If the main board is not used you need only the dout din connections The configuration bit streams are then feeded to the lowest level SCP or XChecker ErSt Electronic GmbH Aeschstrasse 171 Telefon 41 1 980 61 44 CH 8123 Ebmatingen Fax 41 1 980 61 30 Internet http www erst ch EVALXCS User Manual 14 14 3 3 Clocks The seven clock signals pgck1 to pgck4 and sgck1 to sgck3 are routed to the header connectors where pgck1 may be connected optionally to the internal quarz oscillator see Table 9 Source J3 CLK int J4 CLK ext Quarz Oscillator inserted notinserted Ext Clock pin 52 of ST1B notinserted
22. ual 3 3 Contents I oss C S 5 PAR I 2 C 6 2 1 Key Features sss sesssessasssssssssssssssnssnsnsssnssssssnnssnnsnnensssssnssennnnnense see 6 2 2 Applications essennsorsonnnsnsennnnnsessnnnnunsnonnnnnssnnnnnnersnnnenssnnnonnessnens 6 2 3 Function Description essenssssssonsensonsonsssonsonssnsnnonnensensonssnennene 7 3 Technical Information 9 3 1 POW Supply AAA 9 3 2 FPGA Configuration eee eee ee eee eere eene eene eaae tensa se aeee 11 3 2 1 Master Serial Mode nitentem eere ey en 11 3 233 Slave Serial Mode a tere ert ORE REEF EU En 11 3 2 2 1 Daisy Clh m cine redes e ed nissen 13 3 3 COCKS HC 14 3 3 1 External Clock ER 14 3 3 1 1 Termination 0 5 14 3 3 2 Internal Clock Quarz 15 3 4 Reset Button cusssosssssossssonssssonsssnsnsnnnsnsnnnnnnnnsnsnnnsnsnnnnnnnnnnenen 15 33 A mc 16 3 6 DIP SOHCD san 17 3 7 Stimuli and Monitoring Signals sssssssseeeeeeee 17 3 8 Dedicated Signals on oen nana nanus nennen 19 3 9 Stack Extension cssesosssssssssonssssonnnnnnsnsnnnnnnsnnnsnsnnnnnsnnnnnnnnenen 20 4 Lilerature X X X X 21 5 Appendix A Pin Assignm
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