Paper - Asee peer logo
Contents
1. U6 2764 SE000 SFFFF PB_BUS 0 7 Address BUS 0 7 address BUSO 10 i PC_BUSO pes Address BUST 9 A0 00 CS PC_BUST 3 8 Address BUSZ 8 A Ol a3 PC_BUS2 E ahsv Address BUSS__7 A2 02 745 PC_BUSS a ml z Address _BUS4 EI O3 76 PC_BUS4 a a 2u g Address _BUS5 5 4 04 747 PC_BUS5 Address_BUS6 4 A5 o5 ig PC_BUS6 gt Address BUS7 3 A6 06 Ce PC_BUS7 E PB BUSO 21271 oF x BUS O w i PC_BUS O 7 elei Je A9 o IFSS A10 A11 z RESET SE oer A12 E 22 les 5V RESET 38 Pc BuSo c19 pa 28 ER ADO PC_BUSI aur a 20 BGM VCC ig ADH PC_BUS2 EH CE GND AD2 5 1 P1 AD3 j VPP Me 5 ADA 1 2 SIE ADS Ben E E PC_BUS7 7 74HC14 USA RE ADIT 20 shee vss PC_BUS O 7 o an ae aw Lo ge eee 74HC14 ca ae USB E Z al 4 coat cio CONNECTOR DB9 7 70 1uF 13 ger AS Rp E 11 2 eae Cp 10 van T20UuT X PB2_BUS 0 7 ge 5 Tofo ee tur E cas Address Hl He puer 10 11 PC_BUSO_ A ZIEL Address_BUS1 gja Won Ce PC_BUST By Cat Address BUS2 ga At voi CG PC_BUS2 2 C2 a Address_BUSS 7 A2 02 45 Pc_BUS3 6 z Address BUS4 SA 1 03 46 PC_BUS4 v u Address _BUS5 pjm vorir 267 ee Address BUSE In W Cu ZN Tue S Address BUS 4J voe is s n 1 07 A8 24 J A9 pp pue VER BUS 21 PB_BUS1 ZS A10 e oR A12 26 1 A13 62256 A14 16K RIW 7E WE J5 JUMPER val 20 WE de ee a2. E RID 2 19 ODB RG RESET SIP WAEA M 2 MODB pco EN dh 1 RST PC1 VRY 3L VRL PC2 SE SS ZS VRH PC3 L xXRQG 4 xRO PC4 uF SE VR I 28 top PC6 Rete TOM AP PC7 RIA c4 c5 45V ee RIB 22pF 22pF SW_PB_SPST PD1 sk ak GT Ba ATK Poe 2 SC 10K Sf 10 HEOK Sip 10 HE S SCH el PD3 ere pba Se PD4 me c1 U4 MC34064 PD5 PDS d Hast wH as H4 As 1uF 5 9 MODA r MODA RW RIE PB_BUS 0 7 S a S 6 A a Al0K SIP 10 HE T DH RIF YE 10K SIP 10 HE RIW y3 4 Z MODB MODA STRA E 2 a STRB 7 8 J2_CONN RECT 10x2 EX A ZS XT Y7 PC2_BUS0 A g PC2_BUS1 PB2_BUS1 PB2_BUSO PC2_BUS2 i 1 PC2_BUS3 PEO PE4 PC2_BUS4 g H PC2_BUSS PEt PES PC2_BUS6 1s 18 PC2_BUS7 PE2 PEG RESET a A XRG PE3 PE7 IRQ 12 20 DO VRI VRH ane RXD PD2 a 23 24 R4 U10 _LM7805C T0220 EDS 25 26 Fo 45V 3 H iga PD5 VDD OUT N 27 28 2 PA7 PAG Hees 29 30 ie 680 2 3 A 31 32 D1 cl SNE cis CONN JACK PWR PA3 a 22 PAO L T PA PA2 PB2_BUS7 3 28 PB2_BUS6 ed DR PB2_BUSS ES 38 PB2_BUS4 PB2_BUS3 PB2_BUS2 S Figure 1 CETHC11EVB2 System Circuit 1
3. RiG 5V 1 Bl ico 10K SIP 10 HE J6 JUMPER j C15 8 1 2 Gef SN me 10K SIP 10 HE Fale 9 J5 off J46J6 on 6000 7FFF 8K J5 on 34636 off 4000 7FFF i pC BUS S Figure 2 CETHC11EVB2 System Circuit 2 Co LL ebed OS CETHC11EVB BUFFALO Ver 3 4 Bi gi aa ot we ele w e Ss a Picture 1 CETHCIIEVB2 System Board HI The 68HC11 Simulator Designs The CET11SIM simulator is a simple and easy to use tool designed for Motorola s MC68HC11 microcontroller CET11SIM allows users to gain a better understanding of the architecture and operations of the HC11 microcontrollers It takes an assembled listing file and allows a user to step through each individual operation and display all hardware registers and memory changes accordingly this gives the user a perspective on how the file they created interacts with the HC11 hardware Debugging a piece of software can leave a person feeling discouraged and sometimes confused With assembly level programming this is more common than not especially for students who are first time learners and novice programmers The majority of the time the bug is a simple syntax error such as inadvertently using an incorrect addressing mode Such errors are difficult to diagnose even for the professional developer Debugging these errors is a time consuming process With every modification to the program the user must assemble and export the pr
4. So 0087 107a 33 PU Pulling B SKHINZVC 0052 107b 33 PU Pulling X CCR joo000001 0043 107 18 38 PL Pulling ht e EE 4 7 7 D ior ark g TPT e TA HESE S Store naw stack pointer in DEI y name 0086 PUSHING ALL REGISTERS IN ANOTHER MEMORY BLOCK SAME ORDER PULLED 0087 peeve ae Ese EREEREER RONIS sp 0078 0048 1081 de 709 LDS STPT eng Stack pointerta STPT 0059 1034 13 3c PSHY Pushing IY PC 1086 0071 1087 37 PSHB Pushing B Step Run Continue 00721086 36 PSHA Pushing A 0073 tren inetininhrinhinnbtnnbtnehintihinhihinbdrinhiranhinnthinttinednhhnierde 0074 PUSHING ALL REGISTERS IN ANOTHER MEMORY BLOCK REVERSE ORDER 0075 saesrenrearoarearernrrenrearoaronrensirsrearenroariarit CETELE LDS STPT3 Mawng Stack pointer to STPT3 0077 108 36 PSHA Pushing A 0078 1080 37 PSHB Pushing E 0079 108e Dr XGDX Exchanging IX with Double O A and B 0080 108r 36 PSHA Pushing A 0084 1090 37 PSHB Pushing amp 0092 1091 19 6f xGDY Exchanging IY with Double D A and B 0033 1093 36 PSHA Pushing A 0034 1094 37 PSHB Pushing B 0085 1095 r 7015 STS STPT3 Store Stack pointer back in STPTI 0036 1098 7c TOR INC COUNT incrementing counter 0097 109b 7210656 JMP MAIN Jumping Sack to MAN 0038 109e Bo of ff ENO LDS S0FFF Relocating the Slack pointer 0089 10a1 2 Swi Ending program 0030 0091 Ow Ending grogram Figure 4 Single Step through CET11SIM 6 8Z L ebed The area below the Step and Run buttons is a display of
5. the student through Motorola s web site and instructors hand outs Additionally requiring students to pay for the parts and the system board 80 00 and using reference books instead of a required text book was preferable to the students From the administrators point of view there is only the initial cost in the development stage of the system board and simulator After the design and development is finalized there are no additional costs such as maintenance or replacement of any of the system boards Since each student owns his her own system board it is guaranteed that the boards will be treated with care Even if there is anything malfunctions in the system board having previous trouble shooting experiences enables them to fix the problem and the cost is just the component expense At the departmental level there are no additional costs except for the basic lab instrumentation From the instructors point of view it is relieved from the task of maintaining and repairing system boards and their associated costs This also gives instructor flexibility in implementing lecture and lab material that is based on the manufacturer s data sheets not a textbook The simulation software is an excellent teaching aid that eliminates many mistakes and associated trouble shooting time before the student actually runs his her software on the CETHC11EVB2 After two years of implementing this hardware and software system feedback and comments fr
6. unacceptable in academic laboratory exercises These 16 I O pins can be made accessible by forcing the CPU into single chip mode but this restricts the CPU s available memory to the on chip memory which in turn restricts the user s programming code size For laboratory instructional purposes this is also undesirable The design of the CETHC11EVB2 uses the 68HC24 marked as U7 to make all 16 I O pins available to the user and keep 68HC11 running in expended mode thus allowing access of 8K or 16K RAM and 8K EPROM at the same time This 68HC24 called a port replacement unit was designed by Motorola for this particular purpose but was later discontinued We are able to get this important part from Tekmos Inc base in Austin TX that continues manufacturing it at a slightly higher cost 2 The Communications and Memory Map T It was not necessary to design the software for communication between the CETHC11EVB2 and a PC since Motorola already has a good user interface software called BUFFALO that is stored in a 2764 an 8K EPROM marked as U6 and decoded at address E000 The communication uses the SCI on the 68HC11 and the RS232 on a PC serial port A simple MAX 232 chip marked as U9 is used for the communication signal conversion between TTL and 12V levels for downloading and debugging The CETHC11EVB2 uses 9600 BAUD rate 8 data bits 1 stop bit and no parity to communicate via a PC s serial port The system is built around
7. 2006 386 A NEW APPROACH IN MICROPROCESSOR MICROCONTROLLER COURSES LABORATORIES MATERIAL DESIGN AND DEVELOPMENT Steve Hsiung Old Dominion University STEVE C HSIUNG Steve Hsiung is an associate professor of electrical engineering technology at Old Dominion University Prior to his current position Dr Hsiung had worked for Maxim Integrated Products Inc Seagate Technology Inc and Lam Research Corp all in Silicon Valley CA Dr Hsiung also taught at Utah State University and California University of Pennsylvania He earned his BS degree from National Kauhsiung Normal University in 1980 MS degrees from University of North Dakota in 1986 and Kansas State University in 1988 and a PhD degree from Iowa State University in 1992 Jeff Willis Utah State University Jeff Willis Jeff Willis is a Software Engineer developing Mission Planning Software at Hill Air Force Base in Utah He earned a BS degree in Computer Electronic Technology and a Masters degree in Computer Science from Utah State University As part of his Master s Thesis he co authored two papers on self configuring deterministically latent intercommunication architectures for satellite payloads American Society for Engineering Education 2006 LOG LL Sped A New Approach in Microprocessor Microcontroller Courses Laboratories Material Design and Development Abstract Courses in microprocessors and microcontrollers are standard parts of the Engineering Technology core cu
8. 9 VII Biography GI SZ LL abed
9. C11EVB2 uses an HC24 port replacement unit to gain access to Port B and Port C T O pins control e There is no need to change the HC11 s mode The CETHC11EVB2 always remains in Expanded Mode e CETHCI11EVB2 has full access to external 8K or 16K RAM Jumpers J4 J5 amp J6 selectable while maintaining control over all I O pins This makes the system flexible enough to accept different RAM chips based on the availability e CETHC11EVB2 can be used as a full target system development tool The only required changes in the developed software are the starting address and RAM access area when moving to a single chip EEPROM or ROM or RAM memory e There are no problems in dealing with insufficient memory and mode changes on the CETHC11EVB2 as compared to other EVBs that only operate the 68HC11 in single chip mode e Most of the available 683HC11 family members can be used on the CETHC11EVB2 There are different kinds of software can be used on this CETHC11EVB2 such as 1 DOS based AS11 EXE for assembler and KERMIT EXE for downloading 2 a window based AXIDE from Axiom and 3 public domain window based MiniIDE These are all compatible with the CETHC11EVB2 The U8 socket accepts an 8K 8 byte or 32K 8 byte RAM the speed of which is irrelevant Figure 1 and 2 are the CETHC11EVB2 system circuits that use a external memories at addresses E000 FFFF for the BUFFALO monitor program and 4000 7FFF for the user RAM and b internal memo
10. cifications The JFrame object controls how each component inside the frame is displayed how messages between components are handled and the actions that result when an event such as a mouse click occurs Sub components such as the text area buttons text fields and the menu all reside within the JFrame object 1 The key component in the JFrame class is the TextArea class This class displays the list file that the HC11 simulator will be executing The TextArea class interacts with the user by allowing break points to be set and displayed and by displaying the next line of the list file to be executed The TextArea object is also responsible for inputting the file to be displayed 313 As the file is input information is extracted and stored to develop a model of the current state of the HC11 The Program class is an abstraction of the HC11 program being debugged It stores information about the HC11 program that has been loaded for simulation The program object is the central link between all other objects It must maintain a data structure that links a line number in the TextArea object with an HC11 memory address This link is utilized when a Jump or Branch instruction is encountered The opcode instruction contains an address of the memory location to jump to at which point the simulator must jump to the corresponding line in the list file and display to the user that it is the next statement to execute This is accomplished with a Hash Table obj
11. e by Motorola Inc in the 1980 s Due to the effort of Motorola University Support program this EVB was very popular in most of the universities and community colleges microprocessor microcontroller related courses and projects designs When Motorola spin off their microprocessor division to Freescale Inc the 68HC11 EVB became very hard to obtain The alternative EVB made by Axiom is more expensive Another draw back is that the alternative board has limited functions as compared to the original Motorola 68HC11 EVB In order to extend the use of the 68HC11 EVB and keep all 68HC11 CPU laboratory exercises and project designs intact the design development of a modified Motorola 68HC11 development system became a reasonable choice The objectives of this new approach are 1 sustain the use of the 68HC11 CPU 2 keep the EVB hardware cost to a minimum 3 make a smooth transition from 8 bit CPU to 16 bit CPU applications 4 give students ownership of flexible hardware that can be used in several courses and 5 relieve the financial burden on the institution After two trials in designing and testing of the hardware circuits and implementation in the laboratory with students for two years this hardware was named the CETHC11EVB2 and has been successfully used in several related courses To minimize the students errors in utilizing the 68HC11 instructions and addressing modes a teaching assistant software simulator was also de
12. e next line to execute CET11SIM uses the ORG opcode to establish an entry point for the HC11 application the first opcode following the ORG instruction will be the first executed The Step button executes the highlighted line updates the HC11 and the display The Run Continue button executes successive lines until a break point or the end of the program is encountered Only one break point is allowed which can be changed at any point When a new break point is recorded the old break point will be discarded To place a break point just point and click on the line of the file where the break point is desired The break point display area shows the line number where a break point has been recorded The line number will also be highlighted in red to indicate the break point The values in the registers are displayed by default in hexadecimal except for the Condition Control Register CCR which is displayed in binary The decimal button changes the HC11 s displayed values to a decimal representation The binary button changes the HC11 s displayed values to a binary representation The values will be returned to a hexadecimal representation after the next line is executed Se ch Open Jst file Display Help File a Decima ve PULUNG THE ALL REGISTERS FROM FIRST MEMORY BLOCK 0058 no oa Gd 00591076 b 70 LDS STPT Mowing Stack pointer to STPT ACCD jo204 0060 1079 32 PU Pulling A
13. e software implementation of CET11SIM is also presented in a flow chart format in Figure 6 Load S19 File ra Is file valid ORG org found Ge Yes y 1 Create Virtual Program 2 Display S19 File y RUNNING Wait for User Input 1 Display current contents of HC s Components 3 BREAK 7 Highlight next line to execute a 2 Allow Break Points to be established POINTS 3 Allow Run 4 Allow Step 5 Allow Interrupt to be triggered 1 Check that line is valid 2 Remove previous break Points STEP 3 High light in red established break point 4 Display Line number of current break point y y RUN 1 Check PC contains a valid Address CONTINUE 2 Pull Opcode Statement from that address 3 Determine Opcode operation to be performed 4 Perform Operation 6 Increment PC to next Memory location to execute i NO 1 Check PC contains a valid Address 2 Pull Opcode Statement from that address 3 Determine Opcode operation to be performed 4 Perform Operation 6 Increment PC to next Memory location to execute Figure 6 Software Structure of CET11SIM ZLG LL abed IV The Microprocessor Microcontroller Related Course Implementations The implementation of the CETHC11EVB2 and CETHC11SIM can be adapter to different levels of the microprocessor microcontroller courses By requiring
14. ect that uses the address as the key and a Statement object as the value The program object also maintains an array of the HC11 s memory contents LESZ LL Beg The Statement class is used to organize each of the list file s statements The statement object breaks a line down to its relevant components such as the HC11 s corresponding memory address the opcode the data and the line number The HC class holds the abstraction for the HC11 object This includes single byte accumulators A B and D and the Condition Code Register CCR and double byte registers X Y the Program Counter PC and the Stack Pointer SP 7 The SP is a virtual stack that represents the contents of the actual stack The HC class also includes all the operations methods needed to simulate an actual HC11 Included in the HC11 class is a memory table which is used to display the current memory contents of the HC11 The table object uses the program s memory array to fill in the table The HC11 classes as well as the majority of the classes contain a utility class which performs basic operations such as converting a hexadecimal string to a decimal or binary value The Opcode class contains all the implementations of the HC11 s operations A fetch call is made from the HC11 class which determines the appropriate opcode function to be executed calls executes the function and updates the pertinent components of the HC11 class The description of th
15. it m eu 0058 0159 Ud sec Sette Camp 0089 015a 49 ROLA Ralate lights Uf sp Os 0070 015b Sa DECS decramentB ee 0071 O15 26 f5 BNE R3LOOP and loop until B 0 Pe oni 0072 0073 015e 7a 01 02 THEENO DEC MAINLOOP Step Run J Continue 0074 0161 26 be BNE BEGINNING 0075 NI 0076 0163 3f ew Halll 0077 Break P 0000 0078 0073 D SERVICE ROUTINE Contents 0030 0032 0167 b6 1005 LDAA PORTCL Clear the STAF flag 0033 0094 016a 06 010 LDAA PARAMETER Check if Pararneter 0035 016d 81 02 CMPA 302 must be reset 0096 0161 27 06 BEQ CYCLEPARAW 0087 0171 7c Ot M ING PARAMETER Parameter 0098 0174 72 01 Fe JMP SERVEND 0089 0177 8600 CYCLEPARAM LDAA RI Reset Param 0090 0179 d7 0107 STAA PARAMETER DC 0092 0093 017 30 SERVYEND RTI 0034 Fy d SS Gi DR Figure 5 Interrupt Operation in CET11SIM At any point a new list file may be opened to debug This will overwrite the previous data objects used to model the HC11 and create a new model from the program loaded OLeZ LL abed 3 The Development The CET11SIM was developed using a broad and simplistic approach It is designed specifically to target university students Colleges around the country utilize many different types of computer systems so a platform is needed that is independently executable CET11SIM is not designed to meet the needs of a commercial user so execution speed was not a primary concern these two factors led to the use of the Java
16. niehinnbenenrnits A i 0012 SET UP LOCATIONS FOR POINTERS TO KEEP TRACK OF STACK POINTER SP rt 0013 Preprerterrercertertereerersertertercrtersercercettertd pc 2040 0014 70h STPT1 EQU 70F1 pa SPTP1 wilh address 70F1 0015 70r STPT2 EQU S70F3 Los SPTP2 wih address 70F3 Step Run Continue 0016 70 STPT3 EQ 70F5 Load SPT 2 wilh address 70F5 0017 700 COUNT EGU 70F Load COUNT with addrass 7 0F7 0m8 IRUPRUAETALIRVIREPAUPRORLEALEREIRTIRTPATIRTANTRGTAGIAWINEDE a 0019 GENERATING THE EVEN NUMBERS BreakPoint 0000 pose 002 Contents 0022 1040 ORG 1040 Starts program at mamory C000 0024 1042 ce 60 40 LDX 45041 x points to 6040 0025 1045 37 00 LOOP STAA a Store A IX polmer 0026 1047 08 INX xis incremented by t 0027 1048 8b 02 ADDA 102 immediate add of 02 to Acc A 0026 1048 8c 60 5e CPX Eis Compares 3E 10 Acc A sets CCR 0029 1040 26 16 BNE LOOP If zero flag 0 relums to LOOP 0030 PAVIE EN R ATAT A E T O 0035 LOADING STACK POINTER LOCATIONS 0032 aaaea iai 0033 104fce 60 3f LOK Gas LGS Ix with 603F 0034 1052 f 70 ft STX STEI Store Kin STPT1 0035 1055 ce d0 74 LDX 40074 Load Ix with 0074 0036 1058 N7013 STX STEI Store in STPT nerve ER vd Figure 3 Display Screen of CET11SIM After setting a break point and stepping through a few instructions the CET11SIM application will look similar to Figure 4 g 8Z 4 ebed The line highlighted in green will be th
17. ns the interrupt service routine will be executed This gives the user the ability to examine a process that is usually hidden 2 Operating Instructions The proper operations of the CET11SIM simulator can be classified in the following three steps 1 Step1 Java s Run Time Environment Installation The only system requirement is that Java s virtual machine is properly installed on the machine where the application is to be executed The Java virtual machine or Run Time Environment can be downloaded at http java sun com getjava CET11SIM was developed using the Java run time environment version 1 3 1 02 and tested up through version 1 4 2 06 The CET11SIM executable file is a Java jar Die 27 Once the Java runtime environment is installed the jar file can be placed in any directory to be executed To execute the jar file double click on the file The application will then start 2 Step2 Creation of a List File A list file contains a line number a hexadecimal address and the hexadecimal values of L8Z LL e6ed the opcodes All are used as input for the CET11SIM to model the current state of the HC11 microcontroller The list file is a text file that can be created when an HC11 program is compiled or assembled The s19 file is a hexadecimal file that is created with the specific purpose of being executed on the HC11 hardware Most assemblers generate a list file by default The user can generate a list file from the c
18. od Cliffs NJ Prentice Hall 2001 EVBU Available http www programmersheaven com zoneS5 cat26 31763 htm September 2005 5 Freescale Inc Available http www freescale com webapp sps site homepage jsp nodeld 06 January FLUG LL abed 2006 Gendrachi Thomas Teaching Effective Troubleshooting in the Microprocessor Lab Proceedings of the 2004 ASEE Annual Conference and Exposition Salt Lake City Utah June 20 23 2004 M68HC11 Programming Reference Guide MC68HC11EGR AD Motorola Inc 1991 M68HC11 Reference Manual MC68HC11RM AD Rev 3 Motorola Inc 1991 M68HC11 Evaluation Borad User s Manual M68HC11EVB D1 Motorola Inc 1986 Mastronardi Andrew Montanez Eduardo Microcontrollers in Education Embedded Control Everywhere and Everyday Proceedings of the 2005 ASEE Annual Conference and Exposition Portland Oregon June 12 15 2005 Miller Gene H Microcomputer Engineering Englewood Cliffs NJ Prentice Hall 1993 MiniIDE Available http www mgtek com miniide January 2006 Sun Java website Available http www java sun com Tekmos Available http www tekmos com standard_products TK68HC24 htm January 2006 THRSim11 Available http www hel1 demon nl thrsim11 info htm September 2005 Wray W Greenfield R and Bannatyne R Using Microprocessors and Microcomputers the Motorola Family Fourth Edition Englewood Cliffs NJ Prentice Hall 199
19. ogram to the microcontroller and then execute and examine the results for clues which hopefully will lead to a solution The CET11SIM application is designed specifically for Motorola s MC68HC11 eight bit microcontroller series The CET11SIM simulates the HC11 by performing all of the HC11 operations and then displaying the results of each operation This allows each HC11 instruction to be verified and corrected immediately before it is downloaded to the HC11 s internal external memory for verification The repeated time consuming process of exporting the HC11 program to the microcontroller executing and then verifying the results can be nearly eliminated Oo 1 LL e6ed 1 Overview of Operations CET11SIM operation consists of opening and loading a list file to the CET11SIM The list file a text file is a product of the assembling process The programmer creates this text file which contains the operations to be performed by the microcontroller The text file is an input file for the assembler The assembler generates a hexadecimal file that will be loaded to the memory of the microcontroller for execution and the list file The list file displays the relationship between the user created text file and the hexadecimal file executed by the microcontroller The list file also displays any assembly errors to the user The assembler adds to each line a line number the hexadecimal value of each opcode and its arguments as shown in Fig
20. om the students who use it in their microprocessor microcontroller courses is totally positive It is a great access to the students who use it in their senior project designs With this system board they can basically do their design work anytime and anyplace Additionally it has been observed that students do not sell the system board after they have completed their classes or degree It seems like a proud trophy that students want to keep for years to come Having students go through the process of building the system board and using the simulator has triggered students interest in how the board operates and the function of the codes in the simulator In those microprocessor microcontroller classes there are interesting topics students asked about the system that they built and software they used which provide the instructor with additional ideas for project experiments and teaching methods This integration provides interesting concepts that offer students a better understanding of the links between hardware and software and the potential microcontroller applications at future workplaces VI Bibliography 1 Axiom Manufacturing CME 11E9 EVBU MC68HC11 Low Cost Development System Available http www axman com January 2006 2 Cady Frederick M and Sibigtroth James M Software and Hardware Engineering Motorola M68HC11 Oxford NY Oxford University Press 1997 Cay Horstmann S Core Java 2 Volume 2 Advanced Features Englewo
21. ommand line using as11 filename 1 gt filename lst This redirects the list file output of the as11 command to a destination file The generated list file can then be used with CET11SIM There are many freely available HC11 assemblers that will automate this process These Microsoft Windows based assemblers are available from web sites such as AxIDE at http www axman com files Other AxIDE AxIDE363 exe or MiniIDE at http www mgtek com miniide Download Either of these assemblers will assemble HC11 source code and generate the s19 and Ist Dies LI 3 Step3 Execute the CET11SIM Applications To execute the CET11SIM simply double click on the executable jar file To open a list file click the Open list file at the top of the application this will bring up a dialog box Select the list file you would like to debug and open that file The application will appear as shown in Figure 3 loj xj Open Jst fle Display Help File ACCA IFA Decima oca saceeeneenneneeneehasnenaeneneenehnbieneneneenehitienienenenenrnennrseneeneie 0002 File Name Labz acco FB Binary 0003 Function Generate a set of consecutve even numbers and move tham using pen 0004 he stack point to anjotter black s of memory forward and backyards a 000 7 Author Owen Buttars SMHINZVC 0006 Date 1 27 2003 ccr 90000000 0007 0008 ix 001A 0009 LABE OPCODE OPERAND COMMENTS ML EE 000 EE m Jonn 0011 steseeneeneenenesesioneenenenone
22. programming language Java is similar to C in that they are both object oriented programming languages and they follow the same syntax guidelines They both allow the development of unique data structures making them very versatile However there are a few things that differentiate the two Java is platform independent meaning once the code is compiled it can be run on any computer with the Java virtual machine Java is much more reliable than C with its built in exception handling Exceptions allow a program to continue running even after an error has occurred For example if a program is expecting a specific file format for input and an incorrect format is encountered the program will create an exception This means the program will stop executing the code to input the file and return to the state previous of the file being input Java does not allow multiple inheritances which removes a great deal of complexity Java does not use pointer syntax Everything is either an object or a primitive such as float integer or character This makes Java code easy to read and write Java is free to any non commercial user and its documentation is easy to understand 4 Software Structure The main component of the CET11SIM is the window or frame Its job is to take information input by the user and route that information to functions that will handle the request Java s JFrame class is used as a base class that was extended to fit the project s spe
23. rricula The traditional course material developments include both lectures and associated laboratory exercises No matter how creative is the curriculum it is usually budgetary constraints that confine the creativity when developing new curricula This limits the freedom of the major approach in new course development This article demonstrates new course lecture and laboratories material development that starts from ground up with both a hardware platform and simulation software design for microprocessor microcontroller related courses It is not only very cost effective but also does not limit the instructor s creativity when developing new curricula The only obstacle is the instructor s imagination on courses and laboratories activities This system can be implemented at no cost to the department for sponsoring the courses As a matter of fact the initial trials of this system have generated revenue thereby supporting future improvements and development needs This new approach in course improvement starts with the design of a hardware platform in a custom made evaluation board It involves the system circuit and power supply design printed circuit board layout prototype testing and circuit board fabrication The second step is to design the simulation software for laboratory uses The total design and development of both software and hardware was a two year evolutionary process I Introduction The 68HC11 EVB evaluation board was mad
24. ry at 0000 00FF or 0100 0FFF depending on the type of 68HC11 family members for interrupt vectors and user memory Picture 1 presents a photo of a fully assembled CETHC11EVB2 system board VSZ 4 afp U1_MC68HC11E9 34 31 U2_74HC373 PAO 33 PAO PA3 F n PA3 Address_BUSO PAI 32 PAI PA4 59 PA4 D1 Qi PA2 PA2 pas L PAS D2 o i pas L PAS D3 o PEO 45 PEO PA7 PA7 D4 Q4 RET 47 PEI PB_BUSO D5 Q5 PE2 4 PE2 PBO De Q6 PE3 424 PES PB1 D o PE4 4a PES PB2 D8 op e PES 48 PES PB3 zu Address_BUS O 7 PEG 8 PEs PBA TE vec ei IRQ PE7 PE7 PB5 OE GND e mig xT Bog PB KR wok sip woHE eech e
25. students to own the EVB system board they are required to build it from components to a complete assembled functional board It is not only an interesting and challenging task at the beginning of the entry level class but it also enhances student understanding of the system in future classes Since each student processes his her own board there is no borrowing lending of the system board and the maintenance expenses are nonexistent Additionally the simulator software can be simply downloaded from the department s server computer Table 1 summarizes various exercises of hardware and software implementation in different level classes uP uC Related Topics Course Contents CETHCI1IEVB2 Class CETHCI1SIM Level Entry Assembly Programming Addressing Mode Hardware CETHC11EVB2 Architecture Subroutines Stacks Basic Math Routines amp CETHC11SIM Simple I O Controls Interrupts Medium Advanced I O Controls Different Number Systems Codes CETHC11EVB2 Conversations Timer Functions ADC Controls Stepper amp CETHC11SIM Motors Controls DC Motors Controls Parallel Interface Serial Interface SPI SCI Bit Banning Display Units LCD Keypad Card Reader Communications High Parallel and Serial Communication Protocols Multiple CETHC11EVB2 Processor Communications HC11 to PC Interfacing 16 32 bit Precision Multiple and Divide Routines External Serial Memories Interfacing Storage Wireless Communications System Integra
26. the current contents of the HC1 1 s memory When these values are changed the changed address and value are highlighted with yellow to make it easier to verify the program s operation The INT Interrupt button triggers the Program Counter PC to load 00EE which is the IRQ Interrupt vector The opcode at this address is executed If the user has properly linked their Interrupt Service Routine with the interrupt vector table the first line of the Interrupt Service Routine will be the next line to execute The following is an example of the contents of the interrupt vector table Address Contents Description 00EE 7E Jump Instruction 00EF ISR address High byte location of Interrupt Service routine high byte 00FO ISR address Low byte location of Interrupt Service routine low byte Figure 5 is an example of what might be seen immediately following pressing the IRQ button Notice the contents of all registers have been pushed onto the stack Bn wll sl Open bt file Display Help Fite ae www wi ie e nen e weve WI te ACCA 00 Decimal 0059 0146 n7 1004 STAA PORTE setLights S 0050 0149 5a DECS Subtract 1 fre E sn Binary 0067 014a 2615 BNE R2LOOP and loop until B 0 acen loose 0082 014c 76 Ot Se IMP THEEND EE 0053 SRHINZVC 0084 C141 88 fe ROUTINE LDAA att 4 11111110 CCR 00010100 0085 0151 ch 09 LDAS 509 B 9 n 0066 0153 07 1004 R3LOOP STAA PORTE Set Lights H poa 0087 0156 bd OF Zo ISR SLEEP Na
27. the structure specified by BUFFALO which keeps all the interrupt vectors the same as 68HC11 families This makes the system board flexible enough to accept almost all available 68HC11 chips There are jumper selections J4 J5 amp J6 to choose 8K RAM 6264 static RAM or 16K RAM 62256 static RAM chip marked as U8 This design gives the CETHC11EVB2 the flexibility to accept different RAM chips depending on the availability and cost EBL LL afp 3 The Power Supply and Connections There is also an on board power unit that uses 5V regulator 7805 marked as U10 to regulate any wall mount power plug that ranges between 6V and 12V DC down to 5V for the operation of the system board and possible low power to the users external experimental circuits This allows the CETHC11EVB2 to be operated in any convenient place There are two 0 1 dual row receptacles marked as J1 amp J2 that are used for interfacing between the CETHC11EVB2 and a user s breadboard circuit or any prototype board These connectors can adapt any jumper wires to standard breadboard or any header pin size connectors to any user interface application 4 The Features This system is the second version of the HC11 evaluation board It is an improved design for enhancing lab experimentation and project use Based on the suggestions from the students the CETHC11EVB2 has several modifications over its predecessor CETHC11EVB and providing several advantages e CETH
28. tions Designs Project Combine of All the Topics to a Useful Application Project CETHC11EVB2 Table 1 The Related Courses with CETHCI1IEVB2 and CETHC11SIM Certainly there are no practical limitations on the use of this hardware and software If there are limited numbers of classes available topics can be combined into two courses or some subjects can be eliminated V Conclusion Although the development of a new microprocessor microcontroller educational system was a challenging task to the instructor it is a worthwhile effort and pays off in the future for years to come It has several attributes that make it attractive to students administrators and instructors From the students point of view the requirement to purchase all the components and assemble solder and test of the final system board is a valuable learning experience The soldering experience is a fringe benefit that students do not normally receive as part of an engineering technology program It is impractical to offer one particular course to teach student soldering and de soldering skills but it is a common practice in real world in either EL SLZ LL afp design or application This assembling trouble shooting experience provides them a valuable lesson and they are determined to be successful This is a perfect example of competence based learning experience and students are absolutely motivated Instructional materials are widely available to
29. ure 1 CET11SIM displays this file to the user with the next line to be executed highlighted in green A break point is registered by clicking on the line where the break point is to be established at which point the first four characters of that line are highlighted in red A user can press either the Step button to execute each HC11 operation individually or the Run Continue button which will execute successive operations until a break point is encountered At this point the user may step through each individual HC11 operation After each operation is executed the results can be viewed in hexadecimal default decimal or binary There is a dedicated text box for each HC11component These include accumulators A B and D index registers X and Y the Stack Pointer SP the Program Counter PC and the Condition Code Register CCR 2 The contents of the HC11 s memory are displayed in a table that indicates an address and the address contents Each time a value in memory is modified it is highlighted in yellow which makes finding and viewing pertinent memory locations easier The IRQ interrupt is the only interrupt supported by the CET11SIM The user triggers an IRQ interrupt by clicking the INT button This causes the program counter to load the dedicated interrupt vector address and perform the operation indicated by the values at that address If the memory contents at the interrupt vector address contain appropriate instructio
30. veloped to be used with this hardware This software is not a comprehensive simulator and is not intended to compete with Z8Z 4 bed commercially available packages but it assists student learning reduces mistakes and enhances trouble shooting skills gt This simulator software is named as CETHC11SIM and has been used in the beginning level microprocessor microcontroller course II The CETHC11EVB2 Hardware Designs The design of the hardware is based on the original Motorola HC11EVB structure that uses the 68HC24 port replacement unit to bring all the available I O ports to the user s control while still running 68HC11 marked as U1 in its expended mode 1 Keeping All the Physical Available Pins of the 68HC11 The 68HC11 has four different modes controllable through the MODA and MODB pins Single Chip Mode Uses the 68HC11 in its independent state only and does not allow for any external memory to be attached Expanded Mode Uses the 68HC11 along with external memory EEPROM EPROM RAM This mode sacrifices general I O ports Bootstrap Mode Uses the 68HC11 for internal memory programming Special Test Mode Used for 68HC11 factory test operations Under normal conditions if the 68HC11 is running in expanded mode all the standard 16 I O pins must be used for address and data buses for accessing external memory Therefore there is no general I O available for the user to use in intended applications This is
Download Pdf Manuals
Related Search