Descriptions changed in M16C/5LD Group, M16C/56D Group User`s
Contents
1. Yes Write WD 1 to WA address Program suspend accepted Access flash memory Interrupt I flag amp 1 enabled FMR31 lt 0 Command No restart FMROO 1 P Yes D Full status check C Program completed D Notes 1 In EWO mode set the interrupt vector table for interrupts to be used and the interrupt routine in areas other than flash memory 2 When interrupts are not used an instruction to enable interrupts is not necessary 3 Program is not suspended until td SR SUS elapses after the FMR31 bit is set to 1 Program Flowchart in EWO Mode Suspend Function Enabled Premodification Start Maskable interrupt Write 0 and then 1 Suspend to the FMR30 bit enabled FMROO 0 Write command code xx41h to WA address Suspend request Interrupt I flag lt 4 enabled FMR33 1 No Write WDO to WA address Fes Access flash memory rs Program suspend accepted Access flash memory Write WD1 to WA address Command FMR31 lt 0 restart FMROO 1 p Yes Full status check C Program completed D Notes 1 In EWO mode set the interrupt vector table for interrupts to be used and the interrupt routine in areas other than flash memory 2 When interrupts are not used an instruction to enable interrupts are not necessary 3 Program is2. 3 0 V to 5 5V 150 300 us 4 4 Oscillator 27 1 6 Oscillator Electrical Characteristics The characteristic of the dedicated 125 kHz on chip oscillator for the watchdog timer has been added Standard Typ Characteristic Dedicated 125 kHz on chip oscillator for the watchdog timer oscillation 125 RENESAS Page 5 of 6 RENESAS TECHNICAL UPDATE TN 16C A210A E Date Dec 14 2011 4 5 Hysteresis V V for TAOIN and others 27 2 1 Electrical Characteristics VCC 5 V The maximum value of the following V7 V7 hysteresis has been changed Standard Parameter Measuring Condition Typ Before TAOIN to TA4IN TBOIN to TB2IN INTO to INT5 NMI ADTRG CTSO to CTS3 SCL2 SDA2 Hysteresis CLKO to CLK4 TAOOUT to TA4OUT KIO to KI3 RXDO to RXD4 ZP IDU IDW IDV SD INPC1_0 to INPC1_7 CRXO 27 3 1 Electrical Characteristics VCC 3 V The maximum value of the following V7 V7 hysteresis has been changed Standard Parameter Measuring Condition r Max yp Before TAOIN to TA4IN TBOIN to TB2IN INTO to INT5 NMI ADTRG CTSO to CTS3 SCL2 SDA2 CLKO to CLK4 TAOOUT to TA4OUT KIO to KI3 RXDO to RXD4 ZP IDU IDW IDV SD INPC1_0 to INPC1_7 CRX0 Hysteresis 4 6 Two Phase Pulse in Timer S gt 27 2 2 5 Timer S Input 27 3 2 5 Timer S Input The characteristics of two phase pulse input in two p
3. not suspended until td SR SUS elapses after the FMR31 bit is set to 1 Program Flowchart in EWO Mode Suspend Function Enabled RENESAS rage ore RENESAS TECHNICAL UPDATE TN 16C A210A E Date Dec 14 2011 4 Additions and Changes on Electrical Characteristics 4 1 Recommended Operating Condition for VCC gt 27 1 2 Recommended Operating Conditions The characteristic of the minimum value for the Vcc power supply has been modified Standard Characteristic in Typ Before Supply voltage 3 0 4 2 Voltage Detector 2 27 1 5 Voltage Detector and Power Supply Circuit Electrical Characteristics The characteristics of Vdet2_0 to Vdet2_3 and Vdet2_5 to Vdet2_7 for voltage detector 2 have been added Standard Min Typ Max Parameter Condition Voltage detection level Vdet2_0 Voltage detection level Vdet2_1 Voltage detection level Vdet2_2 Voltage detection level Vdet2_3 When Vec is falling Voltage detection level Vdet2_5 Voltage detection level Vdet2_6 Voltage detection level Vdet2_7 4 3 Power Supply Circuit Timing Characteristics 27 1 5 Voltage Detector and Power Supply Circuit Electrical Characteristics The maximum value of tdiw g has been modified Standard Unit Symbol Parameter Measuring Condition T Max Min Typ Before After tdiw s Low power mode wait mode release time VCC
4. 26 11 4 1 User Boot Mode Program in Notes on Flash Memory Following notes have been added to the user boot mode description e When using user boot mode make sure to allocate the program to be executed to program ROM 2 e The LVDAS bit in the OFS1 address and bits WDTRCS1 and WDTRCS0 in the OFS2 address are disabled in boot mode e When restarting the MCU in user boot mode after starting it in user boot mode RAM becomes undefined e If addresses 13FF8h to 13FFBh are all 00h the MCU does not enter standard serial I O mode Therefore the programmer or on chip debugger cannot be connected As the reset sequence differs the time necessary for starting the program is longer than in single chip mode e Functions in user boot mode cannot be debugged by the on chip debugging emulator or full spec emulator e While using user boot mode do not change the input level of the pin used for user boot entry However if there is a possibility that the input level may change perform the necessary processes in user boot mode then restart the MCU in single chip mode before the input level changes e To use user boot mode after standard serial I O mode turn off the power when exiting standard serial I O mode and then turn on the power again cold start The MCU enters user boot mode under the right conditions RENESAS Page 2 of 6 RENESAS TECHNICAL UPDATE TN 16C A210A E Date Dec 14 2011 3 1 2 Procedures When Suspend Function is Enabl
5. Date Dec 14 2011 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU amp MCU Document Category No TN 16C A21 0A E Rev 1 00 Title Descriptions changed in M16C 5LD Group Information Technical Notification M16C 56D Group User s Manual Category Lot No Applicable M16C 5LD and M16C 56D Groups B Reference M16C 5LD Group M16C 56D Group Product Document User s Manual Hardware Rev 1 20 Some specifications of the M16C 5LD and M16C 56D Groups have been changed MCU usage and setting procedures have also been added or changed Indicates the titles in the M16C 5LD Group M16C 56D Group User s Manual Hardware Rev 1 20 1 Specification Changes 1 1 Clock 8 9 5 PLL Frequency Synthesizer To use the PLL frequency synthesizer stabilize the supply voltage within the acceptable range of power supply ripple The following table shows the acceptable range of power supply ripple and the figure shows the voltage fluctuation timing Tse Power supply rooe alowabie Wequency WOO 10 me VP P ripple Power supply ripple allowable vcC 5V 05 v ampitude voltage wez Jo v Vcc jav aT Power supply ripple rising faling vcC 5V 03 Vms gradient vecs 03 i vms ripple f ripple Power supply ripple allowable frequency VCC Vp p ripple Power supply ripple allowable ampli
6. ed 26 8 1 1 Suspend Function EWO Mode 26 8 2 1 Suspend Function EW1 Mode The procedure for enabling the suspend function has been modified The modified figures and modifications are shown below Post modification and premodification examples of the program flowcharts in EWO mode are shown on the next page Modified Figures e Program Flowchart in EWO Mode Suspend Function Enabled e Block Erase Flowchart in EWO Mode Suspend Function Enabled e Lock Bit Program Flowchart in EWO Mode Suspend Function Enabled Modifications e The timing to set the flag to 1 interrupt enabled has been changed e The determination flag used in maskable interrupt routine has been changed from bits FMR32 or FMR33 to the FMROO bit Modified figures e Program Flowchart in EW1 Mode Suspend Function Enabled e Block Erase Flowchart in EW1 Mode Suspend Function Enabled e Lock Bit Program Flowchart in EW1 Mode Suspend Function Enabled Modification e The timing to set the flag to 1 interrupt enabled has been changed RENESAS Page 3 of 6 RENESAS TECHNICAL UPDATE TN 16C A210A E Date Dec 14 2011 Post modification Start Maskable interrupt Interrupt weas 0 disabled FMR00 0 nd then 1 Suspend Write 0 a to the FMR30 bit enabled Yes Suspend FMR31 lt 1 request Write command code xx41h to WA address No Write WDO to WA address FMROO 1 Access flash memory
7. hase pulse signal processing mode have been added Also the pin name TSUDA has been added to P8_0 and TSUDB to P8_1 Standard Min Max Parameter tw TSH TSUDA TSUDB input high pulse width twTsL TSUDA TSUDB input low pulse width su TSUDA TSUDB TSUDB input setup time tsu TSUDB TSUDA TSUDA input setup time Two phase pulse input in two phase pulse signal processing mode TSUDA input tsu TSUDA TSUDB tsu TSUDA TSUDB tw TSH tsu TSUDB TSUDA tw TSL TSUDB input tsu TSUDB TSUDA Note 1 When the TSUDA and TSUDB phases are interchanged tsu TSUDA TSUDB aNd tsuctsuDB TSUDA are also interchanged RENESAS Page 6 of 6
8. tude voltage c 2011 Renesas Electronics Corporation All rights reserved RENESAS Page 1 of 6 RENESAS TECHNICAL UPDATE TN 16C A210A E Date Dec 14 2011 1 2 3 3 1 G1BT Register in Timer S 18 2 5 Base Timer Register G1BT Do not write to this register The G1BT register becomes 0000h when the BTS bit in the G1BCR1 register is set to 0 base timer reset This function works same as before without any change Changes on Usage Note Interrupt Request When Selecting Time Measurement Function 18 5 6 Interrupt Request When Selecting Time Measurement Function When the FSCj bit j 0 to 7 in the G1FS register is set to 1 time measurement function selected and the IFEj bit in the G1FE register is also set to 1 the G1IRj bit in the G1IR register or the IR bit in the ICOCiIC register i 0 1 or ICOCHiIC register j 0 to 3 may become 1 interrupt requested after a maximum of two fBT1 cycles When using the IC OC interrupt i or IC OC channel j interrupt set bits FSCj and IFEj to 1 then perform the following 1 Wait for two or more fBT1 cycles 2 Set the IR bit in the ICOCiIC register and or ICOCHjIC register to 0 3 Wait for three or more fBT1 cycles after the time measurement function is selected Set the G1IR register to 00h after the IR bit in the ICOCIiIC register is set to 0 Additions and Changes on Usage and Setting Procedures Flash Memory 3 1 1 User Boot Mode Program
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