FIPSOC User Manual
Contents
1. cIkh lt T gt BEER 825625 82882 181 8 Switching Matrix i g ge S9Ng BERERE SEE 5 8088 Wie S3 x f y 232929 Banaag q Fig 3 1 The FIPSOC Routing Architecture Chapter 2 FIPSOC Programmable Logic 19 PAD 1 PADO IOB BE ES PAD 1 PADO OB 0 89 3333 9 Beas S8 NG s288 am E S eee B qe 882555 IOB Hg PAD ERKI oomi kal DMC DMC 2 g ps S282 ESRERA EXEEEE 2088 ad 2 ga 828g BESEER SEREEB 8088 EERER sagasa SS a 3 232222 gauss crooc a FE 188 e Ha PADO 8820 ES IOB PAD 1 DMC DMC E g pu S282 BSREER S2BEER 2082 E g ga B282 BERBERE SEREER BORD EENER 3 EERER 2 3 Fig 3 2 The FIPSOC Routing Architecture upper left corner Chapter 2 FIPSOC Programmable Logic 20 Semiconductor Design Solutions 3 88 332. Fig 1 18 Mux Type FF CS1 1 CS2 CS3 0 1 3 2 2 D Type FF with Local Synchronous Reset The equivalent circuit for this type of FF can be observed in figure 1 19 Input D2 acts here as a synchronous active low reset The E signal does not affect the FF operation It must be remembered that a synchronous reset should be used in FF modes not in latch ones although its operation in latch modes is permitted To configure the FF in this mode CS1 and CS3 must be set to one and CS2 must be reset to Zero Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions Fig 1 19 D Type FF with Local Synchronous Reset CS1 1 CS2 0 CS3 1 1 3 2 3 D Type FF with Enable The equivalent circuit for this type of FF can be observed in figure 1 20 The E control signal acts as an active high enable pin It must be remembered that this signal is shared by the four FFs even though its function can be different depending on the operating mode selected for each FF The D2 input does not affect the FF operation To configure the FF in this mode CS1 and CS2 must be set to one and CS3 must be reset to zero Fig 1 20 D Type FF with Enable CS1 1 CS2 1 CS3 0 1 3 2 4 D Type FF with local Enable The equivalent circuit for this type of FF can be observed in figure 1 20 Input D2 acts here as an active high enable pin The E signal does not affect the FF operation To configure the FF in this mode CS1 CS2 and CS3 mus
3. COUTC This is the carry out signal from the combinational part when it is configured as a 4 bit adder There is a fast dedicated connection to drive this signal to the carry in input of the upper DMC COUTS This is the carry out signal from the sequential part when it is configured as an up down counter It also drives the output bit stream in the shift register SHR mode There is a fast dedicated connection to drive this signal to the carry in or bit stream in input of the upper DMC 1 1 3 Configuration Data The configuration data is stored in RAM bits that in fact are duplicated to store two different contexts Configuration bits starting with CC correspond to the combinational block those with the prefix CR are used for the routing resources and the CS prefix corresponds to the configuration bits of the sequential block For the combinational block configuration bits ending with 1 refer to the upper tile 0 for the lower one CCMA1 CCMBI upper tile CCMA0 CCMB0 lower tile These bits select the operating mode for the each tile as described in table 1 1 CCMAI CCMBI Operating Mode M EM ms Simple Combinational Combinational Multiplexer zm RENE NM i t Complex Combinational Table 1 1 Operating modes of LUT pairs CCMA1 and CCMB1 configure the upper tile while CCMAO and CCMBO configure the lower tile SIDSA CCR This bit activates the dynamic mode for the combinational part of a DMC If
4. COUTS R6_ Ra RS R ROS IAUXI IAUX2 CLK LSR GSRN 7 03 Seq Block gt OE0 GOE Fig 1 2 Block Diagram of the Digital Macro Cell DMC 1 1 1 PO signals The signals marked with arrows are global I O pins for each DMC All of them are described hereby TAS IAO IB5 IB0 These are the input pins for the LUTs In the static modes IA3 and IA2 are shared by the first couple of 4 input LUTs See Section 1 2 Combinational Block and also are IB3 and IB2 by the two LUTs of the lower tile In the dynamic modes no inputs are shared as far as there are four 3 input LUTs These pins are also used as data inputs in the 4 bit adder mode and as address and control pins in the memory modes IAUXI The first auxiliary signal IAUXI is used for extra input in the sequential macro modes In the counter mode sequential part IAUXI is the up down control pin up on high level In the shift register SHR mode IAUXI is the enable control pin active high Chapter 2 FIPSOC Programmable Logic IAUX2 The second auxiliary signal IAUX2 is used for extra input in the sequential macro modes In the counter mode it is the carry in signal In the shift register SHR mode it is the input pin for the incoming bit stream D3 D0 The data inputs D3 DO are mainly used as direct inputs for the sequential part They provide a neat way to independently use the combinational and sequential parts of the DMC
5. x in the following table should be a 1 For the lower tile a 0 Configuration STATIC DYNAMIC pto 1 1 Complex 4 BIT ADDER Table 1 2 Combinational tile operating modes 1 3 Sequential Block The sequential block has been designed to have a convenient and flexible interface to the combinational part It is 4 bit wide as well and supplies the user with several FF types to be used more or less independently A general block diagram can be seen in figure 1 16 As it can be observed each FF has two data inputs an enable pin two resets the clock input and the Q output 11 CCR Fig 1 16 Sequential Block Overview The FF blocks can be configured more or less independently as described in paragraph 1 17 All the configuration bits used for the sequential part of the DMC are in fact duplicated to store two contexts and therefore they can be dynamically reconfigured while in operation The data stored into the FFs themselves is also duplicated so it is possible to swap an entire context without even affecting the data in the FFs within that context in that moment and then get it back when the context becomes active again If desired this feature can be disabled therefore sharing data in the FFs between both contexts To establish an analogy to software procedures two virtual hardware blocks implemented on the same DMCs in different contexts could be likened to concurrent procedures Data share
6. CIPOOA 3 2 CIPO1B 0 1 1101 MB BOTU EL 1A CIPO1A 3 2 CIPOOA 3 2 CIPO1B 0 1 CIPOOB 0 1 18 CIPOOA 3 2 CIPO1B 0 1 17 NOT USED Sd I MU CIPOIA 32 CIPOOA 3 2 CIPOIB 0 1 CIPOOB 0 1 cr M5 as CIPOOA 3 2 CIPO1B 0 1 a CIPO1A 3 2 CIPOOA 3 2 CIPO1B 0 1 CIPOOB 0 1 eee ee 11 NOT USED eeu al 0E swmx_h9 0 swmx_h8 2 0 swmx_h2 2 0 swmx_h3 2 0C swmx h8 2 0 swmx h2 2 0 SOB swmx h3 1 0 swmx h10 2 0 swmx_h11 2 0 0101 0A swmx h5 2 0 swmx h4 2 0 swmx h6 2 1 0 09 swmx_h6 0 swmx_h7 2 0 swmx_h13 2 0 swmx_h12 2 0100 possum a 08 swmx_h12 1 0 swmx_h14 2 0 swmx_h15 2 0 negout1 negctrll dr_up1N 2 0 dr_down1N 2 0 oo S07 negoutl negonll 06 negout0 negctrlO dr upON 2 0 dr down0N 2 0 05 copi1 4 0 ctrlin1 4 2 s04 ctrlin1 1 0 NOT USED CIPO1B 2 3 CIPO0B 2 3 S03 NOT USED copi0 4 2 0001 802 copi 1 0 ctrlin0 4 0 NOT USED P so um m 0000 Table 4 4 Top IOB memory map Chapter 2 FIPSOC Programmable Logic 31 9 S ID S A Semiconductor Design Solutions M 1E swmx_h9 0 swmx_h8 2 0 swmx_h2 2 0 swmx_h3 2 Nw sin wenn a 1A swmx_h5 2 0 swmx_h4 2 0 swmx_h6 2 1 18 swmx_h14 2 0 swmx_h15 2 0 17 swmx h0 2 0 swmx h9 2 1 16 swmx h9 0 swmx_h8 2 0 swmx_h2 2 0 swmx_h3 2 dd 12 swmx_h5 2 0 swmx_h4 2 0 swmx_h6 2 1 10 swmx_h14 2 0 swmx_h15 2 0 E SOE swmx_h0 2 0 swmx_h9 2 1 0E swmx_h9 0 swmx_h8 2 0 swmx_h2 2 0 swmx_h3
7. 1 TICs are labeled from right to left as A through FF Each IIC has nine inputs driven from the programmable logic through the routing channels and four outputs that can force values on routing channels of the FPGA as depicted in fig 3 5 Table 3 1 shows the connections to the CAB and UP of IICs from HA to F Chapter 2 FIPSOC Programmable Logic IC Port A Semiconductor Design Solutions Name Right Out PORTDO lt 5 gt PORTDO lt 4 gt PORTDO lt 3 gt PORTDO lt 2 gt CustomCLK1 PLconv lt 3 gt PLeonv lt 2 gt PLconv lt 1 gt PORTDI lt 5 gt hwSTA hwINT4 PORTCI lt 3 gt PORTCI lt 2 gt RDY4 RDY3 RDY2 RDY1 CustomCLKO PORTDI lt 4 gt PLconv lt 0 gt PLselout lt 0 gt PLselout lt 1 gt PLselout lt 2 gt hwINT3 PORTCI lt 1 gt PORTCI lt 0 gt Out PLOUTEXT lt 1 gt PLOUTEXT lt 0 gt PORTDO lt 1 gt PORTDO lt 0 gt hwSTC PLINA lt 7 gt PLINA lt 6 gt PLINA lt 5 gt PLINA lt 4 gt PLINA lt 3 gt PLINA lt 2 gt PLINA lt 1 gt PLINA lt 0 gt Out PL_OUT lt 7 gt PL_OUT lt 6 gt PL_OUT lt 5 gt PL_OUT lt 4 gt hwINT2 PLINB lt 7 gt PLINB lt 6 gt PLINB lt 5 gt PLINB lt 4 gt PLINB lt 3 gt PLINB lt 2 gt PLINB lt 1 gt PLINB lt 0 gt PL_OUT lt 3 gt PL_OUT lt 2 gt PL_OUT lt 1 gt PL_OUT lt 0 gt hwSTE PLINC lt 7 gt PLINC lt 6 gt PLINC lt 5 gt PLINC lt 4 gt PLINC lt 3 gt PLINC lt 2 gt PLINC lt 1 gt PLINC lt 0 gt F Left O
8. FFs However there is still an alternative mode which provides local synchronous reset capability but not set GSRN This is the asynchronous Global Set Reset input for the FFs It can be configured for reset or set operation this is configured individually for each FF This pin is active low and is shared by the four FFs OAUXI The first auxiliary output is mainly used to drive the carry out from the combinational block in the adder mode out of the DMC It also can route other combinational and sequential outputs See section 1 4 Internal Routing Resources OAUX2 The second auxiliary output is mainly used to drive out of the DMC the carry out from the sequential block in the counter mode and the output bit stream in the shift register SHR mode It also can route other combinational and sequential outputs See section 1 4 Internal Routing Resources 1 1 2 Internal signals The names given to the internal signals generated at the interfaces between the different blocks described in the block diagram figure 1 2 are the following GOE This input is connected to the Global Output Enable net this terminal is shortcut to the GOE terminal of every DMC and every IOB of the chip It can be used during startup to disable every output pin on every DMC and every IOB to avoid random output collisions C3 C0 These are the outputs of the combinational block They are generated by the LUTs and their internal connectivity depen
9. RAM memory all of the inputs to the DMC are not used and therefore the sequential part may only be used in a macro mode shift register counter or to latch or clock the data out of the RAM SIDSA To configure the upper tile in the Static Memory Mode CCMAI must be set to 1 CCMB1 must be set to zero and CCR must be set to zero CCMA0 1 CCMB0 0 for the lower tile 1 2 2 Dynamic Operating Modes The dynamically reconfigurable modes are used to implement the hardware swap In these modes two contexts are stored for the combinational part of the DMC so in fact there are two virtual DMCs while only one of them is active The non active context can be rewritten while the other one is active and the active and non active contexts can be swapped without affecting the device operation To select the combinational part of the DMC as dynamically reconfigurable CCR should be set to one As explained in section 4 Configuration Memory of this manual the context load operation can be triggered either by a microprocessor write or by the combinational part of a DMC Configuration bit CHWR sets the DMC into a special mode for triggering context loads when this bit is set input pins IA2 and IB2 are used in the place of IA3 and IB3 IA3 is used then to actually trigger the context load process for the DMC when a high level is applied while IB3 is used to select which context is to be transferred low level for context 0 high lev
10. direction These independent switches are controlled by independent configuration bits named after the routing channel they connect ind v0 to ind v11 and ind v16 for vertical channels and ind h0 to ind h0 to ind h3 Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions and ind h8 to ind h11 for horizontal channels Switching matrices are used to interconnect horizontal to vertical channels and are implemented with bidirectional multiplexers for each horizontal track only one of the seven switches can be active at a given time Therefore switching matrices may not be used to shortcut two vertical channels However two horizontal channels may be shorcutted by connecting them to the same vertical track Each bidirectional multiplexer can also be disabled so no interconnection takes place These multiplexers are controlled with 3 bit configuration words named after the horizontal channels they connect i e swmx h0 2 0 to swmx_h15 2 0 Configuration words for each switching matrix is mapped on the nearest block on top and right of it and therefore the upper right corner is a separate block which only includes the switching matrix configuration in its logical map 18 S2REZA 2228 EE 2 ge BIR BSREER SEReER 82088 D 2 38 9 Y 232429 2258 clkh lt 0 gt
11. one per FF CS2 CS3 They store the operating mode of each FF in the sequential part of the DMC See Section 1 3 Sequential Block for details CS4 One per FF it sets as reset CS4 0 or set CS4 1 the GSRN signal CS5 One per FF it sets as reset CS5 0 or set CS5 1 the LSR signal CS6 One per DMC it sets as synchronous CS6 0 or asynchronous CS6 1 the LSR reset set signal CS7 One per DMC it sets them as latch CS7 0 or FF CS7 1 CS8 One per DMC it sets the clock polarity CS8 0 for rising edge FF and low level sensitive latch CS8 1 for falling edge FF and high level sensitive latch CS9 One per FF it sets the polarity of the output signals of the FFs CS9 0 for Q CS9 1 for negated Q Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions CSR The CSR bit marks when set the sequential part of the DMC as dynamically reconfigurable This means that the data in the FFs will be saved upon context swap and restored when the saved context becomes active again When this bit is reset to zero the configuration context is swapped but the actual data in the FFs is not changed I This bit stores the context ID currently set as active for each DMC It selects which part of the LUT is active and which context of the FFs is being used It only has meaning when the CSR or CCR bits are set 1 2 Combinational Block The combinational block is composed of two 6 input 2 output tiles
12. whole tile is like in the complex combinational mode but performing the multiplexing function instead of the custom complex one This mode works exactly as in the static mode but with a slightly different wiring Note In fact each combinational tile can be configured to perform a multiplexing function of the two simple custom functions of the simple mode This usage is tricky and will be explained in the next release of this user manual In Fig 1 13 it is shown the combinational part of a DMC in which both tiles are configured as static 4 to multiplexers All combinations of multiplexer modes and simple complex and memory configurations apply and can be derived from the wiring described in the complex combinational modes section Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions A combinational tile is configured as a dynamic multiplexer when CCMA 0 CCMB 1 and CCR 1 Special configuration data has also to be loaded into the LUTs Fig 1 13 Dynamic Multiplexer Combinational Mode both tiles CCMA1 CCMA0 0 CCMB1 CCMBO0 1 CCR 1 1 2 2 4 Dynamic Memory mode Each 2 bit tile can be configured as a 8x2 RAM memory Here the words static and dynamic do not mean static and dynamic RAM types as it is normally understood but they apply to the configuration type The address pins are IA4 IA2 and IA1 for the upper tile IB4 IB2 and IB1 for the lower tile The chip select line is IAO for the upper
13. 1A 2 3 CIPOOA 2 3 ee KLE AE AET pi0l4 2 02 copi0 1 0 ctrlin0 4 0 p so pa paa 0000 00 NOT USED Table 4 2 Right IOB memory map Chapter 2 FIPSOC Programmable Logic 29 S ID S A Semiconductor Design Solutions dr_up1N 2 0 dr downIN 2 0 1E negoutO negctrl0 dr up0N 2 0 dr down0N 2 0 BENE copi1 4 0 ctrlin1 4 2 uo nmn AAA 1C ctrlin1 1 0 NOT USED NOT USED copi0 4 2 uo Uo O O O O iy _a SIA cop10 1 0 ctrlin0 4 0 NOT USED BU inl EnIn1 llup1 lldown1 i EnIn0 IlupO IldownO 18 NOT USED 17 negoutl negctrll dr upIN 2 0 dr_down1N 2 0 1011 EEE 16 negoutO negctrl0 dr up0N 2 0 dr downON 2 0 15 1010 14 13 1001 12 copi0 1 0 ctrlin0 4 0 NOT USED MD neginl Enlni pullupl pulldown i Enin0 pullupo pulldown0 10 NOT USED SOF negoutl negctrll dr upIN 2 0 dr down1N 2 0 0111 or ESE 0E negoutO negctrl0 dr up0N 2 0 dr down0N 2 0 0A copi0 1 0 ctrlin0 4 0 NOT USED pr so ne pa 0100 S08 NOT USED 07 negout1 negctrll dr_up1N 2 0 dr_down1N 2 0 0011 07 negouti negeudl 06 negout0 negctrlO dr upON 2 0 dr down0N 2 0 0010 S02 10 1 ctrlin0 4 0 NOT USED m s a pe 0000 00 NOT USED Table 4 3 Left IOB memory map Chapter 2 FIPSOC Programmable Logic 30 9 S ID S A Semiconductor Design Solutions SIF CIPOOA 0 1 Ka SIE CIPO1A 3 2 CIPO0A 3 2 CIPO1B 0 1 CIPOOB 0 1 MANON 1D NOT USED CIPOOA 0 1 CIPOIAIOI 1 SN 1C CIPO1A 3 2
14. 2 n 0A swmx h5 2 0 swmx h4 2 0 swmx h6 2 1 EE 06 swmx h9 0 swmx h8 2 0 swmx h2 2 0 swmx h3 2 ps sos aa 00 swmx_h12 1 0 swmx_h14 2 0 Table 4 5 Top right corner memory map Chapter 2 FIPSOC Programmable Logic 32 9 S ID S A Semiconductor Design Solutions 1111 i 1E O1 3 2 O2 0 1 1110 SD sic 1101 1B SIA m 19 RENE RN 0 18 1011 PE 16 1010 e 14 I7 l I6 4 NOT USED 812 1314 0 BU 2 4 0 ip l ee 10 E NOT USED NOT USED ou SF er 0E NOT USED clksel 5 0 SDN NOT USED oo D PA AYY Y YO O O LO N L 0C NOT USED clksel 5 0 NOT USED oo 5 NO r vvv rv vr c crr SOA NOT USED clksel 5 0 09 NOT USED 08 NOT USED clksel 5 0 NOT USED o 7 MEME MW NOT USED o 995 NHU HEH 04 NOT USED clksel 5 0 NOT USED o 0 BEEN 02 NOT USED clksel 5 0 NOT USED we OL Ce Table 4 6 Right IIC memory map Chapter 2 FIPSOC Programmable Logic 33 S ID S A Semiconductor Design Solutions 1E NOT USED clksel 5 0 T 1B NOT USED T 18 NOT USED clksel 5 0 T NOT 14 NOT USED clksel 5 0 NOT NOT NOT USED 0D NOT USED NOT USED NOT USED NOT 06 NOT USED clksel 5 0 NOT T 02 NOT USED clksel 5 0 NOT Table 4 7 Bottom left peripheral cell memory map Chapter 2 FIPSOC Programmable Logic 34
15. 4 100 clk96 4 100 clk96 3 011 clk8051DMC 3 011 clk8051DMC 2 010 clkANADMC 2 010 clkANADMC 1 001 clk DMCO 1 001 clk DMCO O 000 clk DMC1 O 000 clk DMC1 Table 3 2 Signal selection for the clock buffers Independent switches are used to connect horizontal clock lines clkh lt 0 gt and clkh lt 1 gt to vertical clock lines clkv lt 0 gt and clkv lt 1 gt A normal clock distribution would drive the vertical clock lines with the column buffers and then connect horizontal lines to the selected vertical lines Each DMC has one clock input that can be connected to one of the two vertical clock lines on the left or one of the two horizontal clock lines on the bottom of it The shaded region in figure 3 6 shows the clock routing resources configured by configuration nibble cfgcIk 3 0 located in the logical memory map of the corresponding DMC the one where the clock lines would be connected The horizontal vertical interconnection information is coded within the same cfgclk 3 0 nibble The different possibilities are listed in table 3 3 cfgclk 3 0 Select Interconnection SF 1111 clkv0 None E 1110 clkv1 clkh0 clkv0 D 1101 clkv0 clkhl clkv1 C 1100 clkv1 None B 1011 O clkh1 clkv1 clkh0 clkv0 A 1010 O clkh0 clkv0 9 1001 O clkhl clkv1 8 1000 0 None 7 0111 cIkhO clkh1 clkv1 cIkh0 cIkv0 6 0110 clkhO clkh0 clkv0 5 0101 c
16. 83 o B255 UJ e CIRUN 1 CUN O COPI COPI cro cro SPO PO DMC E IOB E 3338 Seas 0 AW g ga 8288 BERBER SZE 9998 AU SS s f N 239959 gamas ka gt DMC mi A2 a a OB s 3833 2855 o O Ego Fig 3 3 The FIPSOC Routing Architecture upper right corner Chapter 2 FIPSOC Programmable Logic 21 J 97 gt Semiconductor Design Solutions gaa Ed 1 IOB E PAD 1 am o Icom Gorio DMC DMC EE g ga S282 BERBER SERBER 2082 ES g ys 8282 BERBER BEREEE 2982 EERER T Sd n f y 232922 sa s PADO oe 888 i IOB T Cono PAD 1 am pa DMC DMC 2 pe SERE B2REER B gt ncEs BORZ ES g Js BERR BERBER ESFERA 9908 CEEITEE 1 EERER RO Fig 3 4 The FIPSOC Routing Architecture lower left corner Chapter 2 FIPSOC Programmable Logic 22 SIDSA aag caya 8 ON BE E gw Sexe SSRERR BERZES GOSB Sly rua sa B ge Soke BREFS SERERE SISE CERE T ai 8282 gt EE g gas ESRE BIRERS EEEEEE 8282 EE B Q s SUN BSBEFR BEKEEE SONG Semiconductor Design Solutions as E ELE TI DMC ES IOB TE E 3338 3 Beki ana pr Fig 3 5 The FIPSOC Routing Architecture lower right corner 3 3 I
17. DL SIDSA Chapter 2 FIPSOC Programmable Logic FIPSOC User s Manual SIDSA Semiconductor Design Solutions FIPSOC Programmable Logic Overview The Field Programmable System On Chip FIPSOC constitutes a new concept in system integration It provides the user with the possibility of integrating a microprocessor core along with programmable digital and analog cells within the same integrated circuit This chip can be considered as a large granularity FPGA with a FPAA Field Programmable Analog Array and a built in microprocessor core that does not only act as a general purpose processing element but also configures the programmable cells and their interconnections Therefore there is a strong interaction between hardware and software as long as signal values and configuration data within the programmable cells are accessible from microprocessor programs This manual describes the FPGA included in the chip It is composed of an array of DMCs Digital Macro Cells surrounded by IOBs In Out Blocks and IICs Internal Interface Cells The DMC is the basic tile repeated to form the FPGA core The IOBs are the programmable IO cells that include bonding pads to communicate with the external world The HCs are special ports to interconnect the microprocessor and the routing channels of the FPGA Figure 1 1 shows an overview of a generic MxN FPGA In later sections each of these elements DMCs IOBs and IICs are described s
18. Horizontal channels h lt 4 gt through h lt 11 gt span two DMC width e Horizontal channels hx125 through h lt 15 gt extend to the whole array width Long channels v lt 20 gt to v lt 23 gt and h lt l2 gt to h lt 15 gt are primarily intended for global signals like resets enable signals or wide multiplexers control although they can be used for general purpose routing in case of long connections between distant blocks Local interconnect is mainly done using short channels v 0 to v 7 and h 0 to h lt 3 gt The routing architecture is programmed by configuration bits which belong to the logical memory map of a given FPGA block like a DMC IOB etc Some routing resources relative to a given DMC are controlled by configuration bits logically located on the memory map of another DMC or IOB To clarify this point figures 3 2 through 3 5 use dashed lines to draw the limits of the logical memory maps For example DMC outputs on the left are mapped on the memory space of the DMC or IOB located on the right 3 1 DMC Routing Resources Figure 3 1 shows the complete routing architecture of a DMC and its surroundings The routing resources for DMC input signals are implemented using input multiplexers so each DMC input can only be connected to one routing channel only one of the interconnection switches that connect a given input signal can be activate at the same time Each input signal can always be connected to VDD a
19. Mode CS1 0 CS2 1 CS3 0 each DMC 1 3 3 2 Counter Macro Mode In the Counter Macro Mode the sequential part of the Cells CSI CS2 cs3 Mode D FF local sync reset D FF Enable DMC is configured as a 4 bit up down counter with load and enable Figure 1 23 shows the pin out for this mode D FF local enable Shift register Table 1 3 FF operating modes 1 4 Internal Routing Resources In this section we describe the routing resources included in the DMC to interconnect the different functional blocks within the DMC and also to provide the necessary connectivity between different DMCs It is described as well which internal signals can be Chapter 2 FIPSOC Programmable Logic 14 GS SIDSA driven out the DMC via the output pins 03 00 OAUXI and OAUX2 All the routing resources must be considered as dynamically reconfigurable as all the configuration bits are in fact duplicated A hardware swap command issued by the MP for a particular DMC unconditionally swaps its routing configuration from one context to another 1 4 1 Internal Router In this paragraph we describe the nternal Router block placed between the combinational and the sequential blocks as depicted in figure 1 2 This block can only provide connectivity between the combinational and the sequential parts of the DMC and should not be mixed up with the general purpose interconnection resources that connect the DMC inputs and outputs to the routing ch
20. OB Routing Resources Figures 3 2 through 3 5 show the complete routing architecture of IOBs on the different sides of the chip up left and right and their surroundings In general the routing resources at the surroundings of the IOBs closely follow the architecture established for the DMC At least the number and distribution of channels the independent switches and the switching matrices have been strictly kept to provide a consistent periphery to the DMC array Therefore every DMC is surrounded by exactly the Chapter 2 FIPSOC Programmable Logic same routing environment regardless of how near it is to a peripheral side of the chip The routing resources for IOB input signals are implemented using input multiplexers so each IOB input can only be connected to one routing channel only one of the interconnection switches that connect a given input signal can be activate at the same time Each input signal can always be connected to VDD and GND These input routing resources are controlled by configuration words with the same name of the corresponding IOB input For example the 5 bit configuration word COPI1 4 0 selects one out of 32 possible signals 30 routing 23 channels plus VDD and GND to which input COPI1 1s to be connected The routing resources for the CIPO IOB output signals have also been implemented using output multiplexers bigger in size to avoid excessive routing delay Two of these multiplexers labe
21. SR reset 12 SIDSA 1 3 2 FF Types The four FFs of a DMC can be not individually configured either as latches or FFs Configuration bit CS7 controls this CS7 1 for FF mode CS7 0 for latch mode For the same clock polarity the latch is sensitive to low levels and the FF to rising edges or the latch to high levels and the FF to falling edges This arises from the fact that the latch is actually the first half of the FF This means that if the configuration changes while valid data is stored in the latch FF care must be taken if this data is to be used again specially if the latch becomes a FF or the FF becomes a latch To clarify this figure 1 17 shows the internal organization of the basic DFF core EI ME CLK Fig 1 17 Internal DFF structure Each FF latch can be individually configured in one of four possible operating modes For these modes configuration bit CS1 must be set to one to disable the 4 bit macro modes 1 3 2 1 Mux Type FF The equivalent circuit for this type of FF can be observed in figure 1 18 The E control signal acts as the selection pin for the multiplexer when E is high the D input is selected D2 otherwise It must be remembered that this signal is shared by the four FFs even though its function can be different depending on the operating mode selected for each FF To configure the FF in this mode CS1 must be set to one and CS2 and CS3 must be reset to zero
22. T SOE ind v10 ind v11 ind v16 0110 SOC swmx_h8 2 0 swmx_h2 2 0 0A swmx_h5 2 0 swmx_h4 2 0 swmx_h6 2 1 I swmx h6 0 swmx_h7 2 0 swmx_h13 2 0 swmx_h12 2 stag Mia 08 swmx h12 1 0 swmx_h14 2 0 swmx_h15 2 0 n 5 on Hp o ced EA 06 CS9 1 0 CR 9 6 CRO 3 2 gn i 05 CRO 1 0 ind_v8 ind_v7 ind_v4 ind_v3 SR CS6 CS8 o 2 2 2 3 CS3 2 CS4 CS2 CSS CS4 CS2 3 CS5 3 00 ind hl ind h9 ind h3 ind hil ind hlO ind h2 ind hO Table 4 1 DMC memory map Chapter 2 FIPSOC Programmable Logic 28 2 S ID S A Semiconductor Design Solutions SIE OAUXI L 0 1 OAUX2 L 0 1 SN 1C CIPO1B 3 2 CIPO1A 0 1 T muna e s14 OLLI O0 L 2 0 OAUXI_L 0 1 OAUX2_L 0 1 P ss Goss ds 18 CIPO1A 3 2 CIPO1B 0 1 I mina m 16 OLLIO O0 L 2 0 OAUXI_L 0 1 OAUX2 L 0 1 E sis Goss a 14 CIPO1A 3 2 CIPO1B 0 1 I muna s12 POLLI O0 L 2 0 OAUXI_L 0 1 OAUX2 L 0 1 ps T conr NOT USED 0111 SOF 0E ind v10 ind v11 ind v16 MW 0D swmx h0 2 0 swmx_h9 2 1 0110 0C swmx_h8 2 0 swmx_h2 2 0 SOB swmx_h3 1 0 swmx_h10 2 0 swmx_h11 2 0 0101 0A swmx h5 2 0 swmx h4 2 0 swmx h6 2 1 0 09 swmx_h6 0 swmx_h7 2 0 swmx_h13 2 0 swmx_h12 2 0100 baa py 08 swmx_h12 1 0 swmx_h14 2 0 swmx_h15 2 0 negout1 negctrll dr_up1N 2 0 dr_down1N 2 0 oo S07 negoutl negonll 06 negout0 negctrlO dr upON 2 0 dr down0N 2 0 05 copi1 4 0 ctrlin1 4 2 804 ctrlin1 1 0 NOT USED CIPO
23. They are also used as the input data bus in the memory modes It should be noted that both the combinational outputs C3 C0 in the diagram and the direct inputs D3 DO are used in the mux type FF modes and their detailed routing is determined by the configuration of the internal outer block see section 5 Routing Resources CLK This is the clock input Its polarity can be configured as rising or falling edge FF modes or high or low level Latch modes This terminal is the same for each of the four FFs E The Enable pin is used as the enable input active high for the D type with enable FF mode In the SIDSA mux type FF mode the E pin is used as the selection pin a high level on the E pin selects the D input a low level selects the D2 input in each FF See Section 1 3 Sequential Block In the counter mode the E input is the load control pin a low level loads data into the counter In the shift register SHR mode the E input is the load control pin a high level loads a parallel word into the register This terminal is the same for the four FFs although there is an special mode which provides a local enable capability see Section 1 3 Sequential Block LSR This is the Local Set Reset input for the FFs It can be configured for synchronous or asynchronous operation same for the four FFs and to reset or set each FF this is configured individually for each FF This pin is active high and is shared by the four
24. annels and therefore to the rest of the DMCs In figure 1 24 it can be observed the internal structure of this block ca Fig 1 24 Internal Router This block is made out of interchangers or blocks that simply selectively swap their two inputs For each of them O1 is shortcut to I1 and 00 to 10 if the selection bit is 1 and O1 is connected to 10 and OO to Il otherwise Configuration bits CRO CR5 control these interchangers as depicted in figure 1 24 1 4 2 Output Connectivity In this paragraph we describe how the internal signals depicted in figure 1 2 and explained throughout this chapter can be routed out of the DMC Configuration bits CR6 CR9 and CRO3 CROO control the Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions multiplexers for the output signals as depicted in figure 1 25 A OU S iv paa CR9 CRS P CROB oms g s gege 2 O gt di OEI T IB AGE SL N ol Gras a be Cao QUICA AS WN ken o uo om ax Fig 1 25 Output Terminals and their connectivity The polarity of the configuration data is listed in table o o cours Table 1 4 Output selection 2 Input Output Blocks IOBs IOBs Input Output Blocks are the peripheral cells used to interface the FPGA to the external world They are placed on the left top and right side of the FPGA one per column or row and they include two I
25. ch can implement any 3 input function As before two LUTs can carry out a 4 input function and the whole combinational block can implement any 5 input boolean function In these modes two independent contexts are stored in RAM bits so there are two backup copies of each configuration bit but for the LUTs The contexts can be independently read and written while only one of them can be active This means that one of the contexts can be changed while the device is operating within the other context and once it is configured then it can be activated to suddenly change the functionality of the device without even affecting its operation The main allure of this approach is that it is not necessary to stop the device to reconfigure it 22 SIDSA N Columns Semiconductor Design Solutions Matrix Rows DMC N O eee DMC EO DMC DMC Swot Matrix wo i H Sw Sw Ww i Matrix Matrix Matri
26. d between the two contexts is like global variables or pointer referenced parameters passed to the procedures while data in the FFs saved with the context information is like local variables or reference parameters passed to procedures To share data between contexts that is to use global variables in the hardware procedures configuration bit CSR must be reset to zero To save the data stored in the FFs when swapping contexts that is to use local parameters in hardware procedures CSR must be set to one Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions 1 3 1 VO and control signals The sequential part of the DMC is composed of four FFs which share their control signals but not their data pins Control signals and data pins have different functions depending on the operating mode in which an individual FF is configured this will be explained in detail in next paragraph We describe hereby the common features for all the operating modes and the common control signals The shared signals for all FFs are CLK E LSR and GSRN CLK This is the clock signal Its polarity can be changed so the FFs can be sensitive to rising or falling edge if configured as FFs low or high level if configured as latches Configuration bit CS8 controls the clock polarity CS8 0 for rising edge FFs or low level latches CS8 1 for falling edge FFs or high level latches E The E input has a different function depending
27. ds on the operating mode See Section 1 2 Combinational Block In the memory mode they are the output data bus In the adder mode they drive the result of the addition R7 R0 These are the outputs of the router block The router block simply interchanges its inputs so R7 RO are the same than C3 C0 and D3 DO but not in the Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions same order In fact R7 R4 can only map to some permutations of C3 D3 C2 and D2 that is signals related to the upper tile and the same applies to R3 RO with C1 D1 CO and DO lower tile Refer to section 1 4 Internal Routing Resources for details S3 S0 These are the outputs of the sequential blocks OE1 OE0 These signals are the control pins for the tri state output buffers As it can be seen in figures 1 8 and 1 14 the output control signals OE1 and OEO are the or function of the CCO configuration bit and IAO and IBO respectively for each tile This configuration bit should only be used to control the output buffers when building larger memories although it can be used at any moment When the tile is configured in memory mode OEI is the output enable signal for the upper 16x2 memory tile and OEO is the same for the lower tile The memory output is then enabled only when the chip select line is high IAO for the upper tile IBO for the lower tile and the output control option is enabled configuration bit CCO reset to zero
28. e in static modes CCR 0 in both figures Fig 1 5 Upper Complex Lower Simple Static Combinational Mode CCMA1 CCMB1 1 CCMBA0 CCMB0 0 CCR 0 SIDSA Fig 1 6 Upper Simple Lower Complex Static Combinational Mode CCMA1 CCMB1 0 CCMBA0 CCMB0 1 CCR 0 1 2 1 3 Static Multiplexer Mode Each combinational tile can be configured as a 4 to 1 multiplexer The behavior of the whole tile is like in the complex combinational mode but performing the multiplexing function instead of the custom complex one Note In fact each combinational tile can be configured to perform a multiplexing function of the two simple custom functions of the simple mode This usage is tricky and will be explained in the next release of this user manual In Fig 1 7 it is shown the combinational part of a DMC in which both tiles are configured as static 4 to multiplexers All combinations of multiplexer modes and simple complex and memory configurations apply and can be derived from the wiring described in the complex combinational modes section A combinational tile is configured as an static multiplexer when CCMA 0 CCMB 1 and CCR 0 Special configuration data has also to be loaded into the LUTs TIAS Fig 1 7 Static Multiplexer Combinational Mode both tiles CCMA1 CCMA0 0 CCMB1 CCMBO0 1 CCR 0 Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions 1 2 1 4 Static Memory mode Each 2 bit tile can be conf
29. e selected strength of the pull down transistor is not disabled dr down1N 2 0 dr down0N 2 0 These bits regulate the falling driving strength of the output buffers in linear steps from zero disabled to seven maximum strength When the selected value is zero the pull down transistor of the corresponding buffer is disabled therefore allowing an open source pull up operating mode if the selected strength of the pull up transistor is not disabled 3 Routing Resources The FPGA is composed of a regular array of DMCs surrounded by IOBs distributed in rows and columns with horizontal and vertical routing channels of different lengths as depicted in figure 1 1 This section deals with the detailed architecture of these routing channels depicted in figures 3 1 through 3 5 Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions There are 24 vertical channels per column and 16 horizontal channels per row not including the special clock lines The routing channels are not identical and have different lengths and routing patterns e Vertical channels v lt 0 gt through v lt 7 gt span just one DMC heigth e Vertical channels v lt 8 gt through v lt 15 gt span two DMC heigth e Vertical channels v lt 16 gt through v lt 19 gt span four DMC heigth e Vertical channels v lt 20 gt through v lt 23 gt extend to the whole array height e Horizontal channels h lt 0 gt through h lt 3 gt span just one DMC width e
30. el for context 1 Therefore in the dynamic simple combinational mode each two LUTs would share an input pin IA2 instead of IA3 for the upper tile IB2 instead of IB3 for the lower if CHWR is set and the dynamic multiplexer mode would only have three different inputs IA2 and IB2 instead of IA3 and IB3 1 2 2 1 Dynamic Simple Combinational Mode In this mode the tile performs two independent 3 input combinational functions sharing none of them as depicted in figure 1 9 In this figure both tiles are configured in this Simple Dynamic Combinational Mode IAS IA4 C3 M 3LUT 142 A C2 ua 3LUT IB5 4 C1 us 3LUT IB2 1 C0 TE 3 LUT Fig 1 9 Simple Dynamic Combinational Mode CCMA1 CCMB1 0 CCMA0 CCMB0 0 CCR 1 Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions For the Simple Dynamic Combinational Mode the configuration data is CCMAI CCMBI 0 and CCR 1 for the upper tile and CCMA0 CCMB0 0 and CCR 1 for the lower tile As long as it is a dynamic mode two contexts are stored 1 2 2 2 Complex Dynamic Combinational Modes The Complex Dynamic Combinational Mode is different for each tile In fact we will explain the three possible combinations of Complex dynamic modes as long as the functionality of a tile in the Complex Combinational Mode depends on whether the other tile is configured in the Simple or Complex Combinational Mode The common feature of this mode for both tiles is that a 4 inp
31. eparately DMCs and other FPGA elements are designated vertically from bottom to top with numbers zero is the first one and horizontally form right to left with capital letters A is the first one Therefore the DMC located at the bottom right corner is designated as 0 A Chapter 2 FIPSOC Programmable Logic 1 Digital Macro Cell DMC This section describes the functionality of the Digital Macro Cell DMC the programmable digital element of the FPGA It is a large granularity 4 bit wide LUT based programmable cell with combinational and seguential resources It easily interfaces the microprocessor through the memory space and can be dynamically reconfigured while in operation as far as two operating contexts are stored at every moment In the static modes that is not in the dynamically reconfigurable modes the combinational part of the DMC includes four 16 bit Look Up Tables LUTs that can be programmed to carry out any function of 4 inputs Each two LUTs constitute a tile and share two inputs These two LUTs in each tile can be grouped to carry out any 5 input boolean function and the four LUTs can be connected to implement a single 6 input function Each combinational tile can also be configured to perform a multiplexing function of two custom functions in particular as a 4 to 1 multiplexer In the dynamically reconfigurable modes the DMC has four 8 bit independent LUTs that share no inputs each of whi
32. he IIC output signals have also been implemented using output multiplexers bigger in size to avoid excessive routing delay Only one of these multiplexers is available for each signal A Global Output Enable GOE signal is routed to the whole FPGA to disable every single DMC IOB and IIC output before chip configuration is done 3 5 Clock Routing Special nets are provided for clock distribution These nets can not be used for general purpose routing They span the whole height and width of the FPGA and are vertically driven by special buffers located at every column Figure 3 6 shows the clock network distribution Two clock buffers are provided at the bottom of every column to drive the two vertical clock lines clkv lt 1 gt and clkv lt 0 gt Seven possible clock signals are only available for the whole chip as described in the Clock Generation Block manual A clock selector is provided at every column to specify which of these seven clock signals is routed to each one of the clock drivers a constant low level can also be selected The 6 bit configuration word clksel 5 0 is used to select the signals routed to the clock buffers as shown in table 3 2 Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions clksel 5 3 clk 1 clksel 2 0 clk 0 7 111 O 7 111 O 6 110 customCLK1 6 110 customCLK1 5 101 customCLK0 5 101 customCLK0
33. igured as a 16x2 RAM memory Here the words static and dynamic do not mean static and dynamic RAM types as it is normally understood but they apply to the configuration type The address pins are IA1 IA4 for the upper tile IB 1 IB4 for the lower tile The chip select line is IAO for the upper tile IBO for the lower tile and it is active high select on high level The read write line is IAS for the upper tile IB5 for the lower tile and it is active high read on high level write on low level The input data bus is D3 D2 for the upper tile and D1 DO for the lower tile The output buffers can be controlled by the chip select lines if the output control option is enabled CCO set to low If this bit is set to high the output buffers are always enabled If set to low the output buffers are enabled when the chip select lines inputs TAO and IBO are active With this technique one can build larger memory blocks In figure 1 8 it can be observed the combinational part of the DMC when both tiles are configured as memory blocks CCO oti D3 D2 TAO cco Gili IBO Dout2 Din1 Din0 D1 DO Fig 1 8 Static Memory Mode both tiles CCMA1 CCMA0 1 CCMB1 CCMB0 0 CCR 0 All combinations of the memory mode and simple complex and multiplexer configurations apply and can be derived from the wiring described in the complex combinational modes section As it can be seen when both tiles are used to implement a 16x4
34. in the On Chip Subsystems Interface manual or by the actual hardware as explained in section 1 2 2 of this manual The LUTs do not share this model because they are dual port RAMs which are directly accessed by the microprocessor Only a DMC uses up the complete 256 configuration bits The rest of the cells IOBs IICs etc have a similar memory map on which the unused locations 26 SIDSA are reserved for future use The position of the used locations is always maintained in every block for example the switching matrices configuration words are mapped at 08 to 0D within all blocks that include a switching matrix i e DMCs right and top IOBs and the top right corner Tables 4 1 to 4 7 show the memory maps for all FPGA blocks that have one underlined bits in tables Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions are inverted Note that the addresses mentioned in these tables are relative to a base address which depends on the selected memory access mode the particular DMC being accessed and the selected context The access modes to these memory locations are explained in the On Chip Subsystems Interface manual 27 2 S ID S A Semiconductor Design Solutions 1E OAUXI L 0 1 OAUX2 L 0 1 EC mem up i gt FU o o O mw mem Wm L 04 16 IB4 1 0 1B3 4 0 CCMBO m a 15 IB2 4 0 IB1 4 2 D3 3 0 D2 3 0 ma BL o 0 E 4 2 jap BH 3 0 IAUX2 3 0 om BO
35. irtual hardware block keeping the data previously written when the context was active To configure the upper tile in the Dynamic Memory Mode CCMAI must be set to 1 CCMBI must be set to zero and CCR must be set to one CCMA0 1 CCMB0 0 for the lower tile 1 2 3 4 bit Arithmetic Mode This mode is set globally for the whole combinational part of the DMC The input words are from MSB to LSB IA5 IA1 IB5 IB1 and IA4 IAO IB4 IB0 The carry in signal is the IB2 pin In figure 1 15 it can be found a sketch of the 4 bit arithmetic mode Fig 1 15 4 bit Arithmetic Mode CCMA1 CCMA0 CCMB1 CCMB0 0 CCA 1 Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions The carry out signal can be routed through the OAUXI output pin The block has exactly the same pin out regardless of the status of the CCR bits although in the dynamic mode IA3 and IA2 IB3 and IB2 for the lower tile would have to be explicitly tied together and the number or arithmetic functions supported in dynamic mode is smaller To configure the combinational part of the DMC in the 4 bit arithmetic mode the CCA bit has to be set to one and the CCMAx and CCMBX bits have to be set to zero Appropriate data has to be loaded into the LUTS for the required arithmetic operation adder substractor etc 1 2 4 Configuration table We include hereby a reference table table 1 2 to help the user configure a combinational tile For an upper tile the
36. led in figures 3 2 through 3 5 as CIPOxA and CIPOxB for IOC x of the IOB are provided for IOCs in IOBs placed on top and right of the chip while three of these multiplexers labeled in figures 3 3 and 3 4 as CIPOxA CIPOxB and CIPOxC for IOC x of the IOB are available for CIPO signals in IOBs placed on top of the array Note that each of these interconnection points CIPOxA CIPOxB or even CIPOxC are actually connected to the same CIPOx signal and therefore they are the same logical net These multiplexers are controlled with configuration words with the same name CIPO1A 3 0 etc As derived from the dashed lines separations in figs 3 2 to 3 5 which establish the limits of the configuration logical memory maps of the different FPGA blocks CIPO signals of the left IOBs are controlled by configuration words in the logical map of the DMCs on the right of them A Global Output Enable GOE signal is routed to the whole FPGA to disable every single DMC IOB and TIC output before chip configuration is done 3 4 Internal Interface Cell IIC and its Routing Resources 3 4 1 Internal Interface Cell IIC architecture The Internal Interface Cells TICs are special routing blocks that provide connectivity between the routing channels and selected control signals of the CAB and HP Each FIPSOC chip has six DMCs located on the bottom side of the FPGA pushed to the right just on top of the microprocessor area as depicted in fig 1
37. lkhO clkhl clkv1 4 0100 clkhO None 3 0011 clkh1 clkh1 clkv1 cIkh0 cIkv0 2 0010 clkhl cIkh0 cIkv0 S1 0001 clkh1 clkhl clkv1 0 0000 clkh1 None Table 3 3 Clock line selection and interconnection at DMCs The clock generation and distribution circuits are described later in the Clock Generation Block manual Each vertical clock line in each column can be selected from the five clock signals provided by the clock generator and two extra buffered clock signals randomly generated from the programmable logic Clocks automatically generated including the MP clock are synchronized and synchronous data transfers to the uP can be safely done 25 SIDSA Semiconductor Design Solutions DMC 7T DMC t 1 DMC 1 ig E E i o O ckh o lo Tlwn n DMC TT TDMC TT TDMC DMC AA AA Clock A N Clock AA Buffer 0 Buffer 1 ee Clock selector customCLK1 customCLKO clk96 clk8051DMC CIKANADMC clk DMC2 clk DMC1 Fig 3 6 Clock routing architecture 4 Configuration memory Configuration data is stored as memory to the eyes of the microprocessor Each complete configuration of a DMC IOB IIC Bottom left peripheral cell which includes the clock buffers for the leftmost columns and even some FPGA corners need a 32 byte memory map upon which up to 256 configuration bits are organized Figure 4 1
38. lowing GOE This input is connected to the Global Output Enable net this terminal is shortcut to the GOE terminal of every DMC and every IOB of the chip It can be used during startup to disable every output pin on every DMC and every IOB to avoid random output collisions 2 1 3 Configuration Data The configuration data is stored in RAM bits that in fact are duplicated to store two different contexts negout1 negout0 These bits select the polarity of the signal to be driven to the external pad when the IO cell is configured as output or bi directional If set to one the output signal is negated neginl negin0 These bits select the polarity of the signal to be driven to the routing channels from the external pad when the IO cell is configured as input or bi directional If set to one the input signal is negated negctrll negctrl0 These bits select the polarity of the control signal that enables the output buffer of the IO cell If set to one the control signal is negated which means that a low level on the corresponding ctrl will enable the output buffer If reset to zero a 16 SIDSA high level on the corresponding ctrl signal will enable the output buffer Note Care must be taken when pure input or pure output configurations are selected because this polarity control still applies to the constant levels that may be selected to permanently enable or disable the output buffer For example if it is intended
39. nd GND Signal IAUX2 can also be directly connected to the carry out signal from the sequential block of the adjacent DMCs on the left and bottom which is a convenient way to implement sequential wide macro functions counters and shift registers wider than 4 bits Input routing resources are controlled by configuration words with the same name of the corresponding DMC input For example the 5 bit configuration word IA4 4 0 selects one out of 32 17 SIDSA possible signals 30 routing channels plus VDD and GND to which input IA4 is to be connected and configuration nibble GSRN 3 0 selects the channel or the constant VDD or GND value to which the GSRN line will be connected The routing resources for DMC output signals are also implemented using output multiplexers bigger in size to avoid excessive routing delay For normal output signals O3 to 00 two such output multiplexers are available One of them can connect the output to only one of 7 vertical channels on the right of the DMC the other one can connect the output to only one of 15 channels on the left and top of the DMC The first multiplexers are controlled by configuration words 03 L 2 0 to 00_L 2 0 mapped on the logical address space of the DMC on the right i e configuration words O3 L 2 0 to 00_L 2 0 within the memory map of a given DMC or IOB configure the routing information for the right output signals of the DMC or IOB placed on the left within the ar
40. nput Output Cells IOCs which can be independently configured IO Cells can be programmed either as input output or fully bi directional The Global Output Enable GOE signal disables all buffers which is especially important during reset GOE is guaranteed to be low upon reset Inputs and outputs can be programmed to be direct or negated as well as the polarity of the control signal which enables the output buffers during the bi directional operation 15 The driving capability of each output buffer can also be programmed An output buffer is composed of a PMOS pull up transistor and a NMOS pull down transistor whose strength can be independently programmed so asymmetric rising and falling times at the output can be achieved Three bits are available to program the strength of each output transistor from zero disabled to seven in linear steps Zero strength configurations are used for open drain or open source configurations pure pull up or pure pull down The input buffers that drive external signals to the internal routing channels can be isolated from the external signals and tied to a constant level Changing the polarity of the input signal which in this case would be a constant level allows selectively setting constant stimuli as if they were coming from the external world which is useful in system debugging applications to emulate real stimuli coming from the external world A resistive pull up and pull do
41. of the FF type For the D FF type it is used as an enable signal while for the mux FF type it is the select signal LSR This is the Local Set Reset signal This set reset can be configured as synchronous configuration bit CS6 0 or asynchronous CS6z1 although this choice must be made for all the FFs in the DMC This signal can produce a set or a reset depending on the value of configuration bit CS5 CS5 0 for reset CS5 1 for set This choice can be made independently for each FF in the same DMC The LSR pin is active high GSRN This is the Global Set Reset signal This signal can produce an asynchronous set or reset depending on the value of configuration bit CS4 CS4 0 for reset CS4 1 for set This choice can be made independently for each FF in the same DMC The GSRN pin is active low The only differences between this reset and LSR are LSR is active high and GSRN is active low LSR can be synchronous or asynchronous while GSRN is always asynchronous LSR has considerably more routing flexibility than GSRN which in turn should be used as a global reset for big hardware blocks instead of single DMCs Collision between resets and uP write operations are permitted although wholeheartedly discouraged They do not lead to device malfunction while they should not be produced as they imply a bad design methodology If they take place the highest priority is taken by the UP write then the GSRN operation and finally the L
42. ptimized way to implement 4 bit up down counters with load and enable and 4 bit shift registers with load and enable These functions may be expanded to any number of bits by connecting more DMCs to the carry pins Chapter 2 FIPSOC Programmable Logic The microprocessor can also read from and write data into the FFs As in the combinational block two contexts are also available for the configuration of the sequential block The user can write one of them while the other one is active so the dynamic reconfiguration can take place without interruption of operation Furthermore the data into the FFs can also be stored with the rest of the context and then restored back upon context swap Finally there are some routing resources to flexibly interconnect the combinational and sequential parts of the DMC Both parts can be used more or less independently although a limited number of output pins are available See next section for details The dynamically reconfigurable mode can be selected for any combination of DMCs Also the hardware swap can be triggered for a group of DMCs rather than for the whole chip 1 1 Block Diagram and VO Pins A simplified block diagram of the DMC can be seen in fig 1 2 SIDSA Semiconductor Design Solutions OAUX1 OAUX2 GOE GOE COUTC C1 C2 COUTC IAS IA4 C3 IA3 D3 IA2 C2 IA1 Comb D2 Block a IBS 1B4 m 183 ds 1B2 UI OE1 B0 OE0 D3 D2 D1 DO COUTS C3 S1 S2
43. ray The second multiplexers are controlled by configuration nibbles O3 3 0 to O0 3 0 of the corresponding DMC The dashed lines of figures 3 2 to 3 5 represent the separations between configuration logical memory maps Auxiliary outputs also routed through multiplexers can only be connected to one of 15 different channels on the right and top of the DMC These multiplexers are controlled by configuration nibbles OAUX1_L 3 0 and OAUX2_L 3 0 mapped on the logical address space of the DMC on the right i e configuration nibbles OAUXI L 3 0 and OAUX2 L 3 0 within the memory map of a given DMC or IOB configure the routing information for the right and top output signals of the DMC or IOB placed on the left within the array Each output signal can always be left open not connected to a routing channel Tri state operation is provided for the output signals so deep memory blocks can be generated General purpose tri state operation is possible but unsupported and strongly discouraged A Global Output Enable GOE signal is routed to the whole FPGA to disable every single DMC IOB and IIC output before chip configuration is done 3 2 Switching Matrices As it can be seen in figs 3 1 through 3 5 routing channels can be connected to other routing channels using independent switches and switching matrices Independent switches only connect channels with the same name in adjacent DMCs or IOBs so a track can be continued in the same
44. shows the configuration bit structure used for every programmable feature of the FIPSOC chips except for the LUTs Configuration Bit CkiM CH2 Load Load 1 Mapped memory Fig 4 1 Configuration Memory Model The real configuration bit is not mapped in the uP memory addressing space However two mapped backup configuration bits are available behind every Chapter 2 FIPSOC Programmable Logic real configuration bit This backup configuration memory can be treated as normal memory It either can be effectively used to store configurations or it can be treated as general purpose RAM memory to run programs or hold user data The set of 256 bits of user data necessary to configure a DMC or an array of them or IOBs IICs etc is called a configuration context DMCs may be configured individually but not partially The whole FIPSOC chip can be partially configured by selecting a set of DMCs specifying a mask of rows and columns To configure a DMC the uP writes the configuration data into a buffer context Then a context load operation transfers the configuration from the buffer context into the real configuration bits As long as they are physically separated the microprocessor may keep using the buffer context for example to load a new context while the DMC is working using the data stored in the real configuration bits The context load operation can be triggered by a microprocessor write operation as explained
45. st also be 0 1 2 1 2 Complex Static Combinational Modes The Complex Static Combinational Mode is different for each tile In fact we will explain the three possible combinations of static modes as long as the functionality of a tile in the Complex Static Combinational Mode depends on whether the other tile is configured in the Simple or Complex Static Combinational Mode The common feature of this mode for both tiles is that a 5 input function is carried out by one of the outputs In figure 1 4 it can be seen both tiles configured in the Complex Static Combinational Mode C3 and Cl carry out two independent 5 input combinational functions while C2 multiplexes these outputs TAO controls the multiplexer transmitting the upper function when IA0 1 and the lower when IA0 0 and CO performs an AND function of these outputs and the IBO input This mode correspond to CCMA1 CCMAO 1 CCMBI CCMBO 1 and CCR 0 Chapter 2 FIPSOC Programmable Logic Fig 1 4 Static Complex Combinational Mode CCMA1 CCMA0 1 CCMB1 CCMBO0 1 CCR 0 The mixed modes one tile in the Complex mode and the other one in the Simple mode are depicted in figures 1 5 and 1 6 The configuration data is CCMAI CCMBI 1 and CCMAO CCMBO 0 to have the upper tile in the Complex mode and the lower tile in the Simple mode Fig 1 5 and CCMAI CCMB1 0 and CCMAO CCMBO 1 for the upper tile to be in the Simple mode and the lower tile in the Complex mode Fig 1 6 Both tiles ar
46. t be set to one Fig 1 21 D Type FF with Local Enable CS1 1 CS2 CS3 1 1 3 3 4 bit Macro Modes When the CSI bit is reset to zero the sequential part of the DMC is said to be in a 4 bit Macro Mode There are two 4 bit Macro Modes The SHR with load and enable and the up down counter with load and enable For these modes bit CS7 must be set to configure the registers as FFs not as latches There are special direct paths for routing the IAUX2 signal directly from the sequential carry out signals of the DMCs on the left and bottom of every DMC This way SHRs and counters can be cascaded without incurring delays because of the parasitic 13 Semiconductor Design Solutions capacitance of routing channels see section 3 1 DMC Routing Resources 1 3 3 1 Shift Register Macro Mode In figure 1 22 it can be seen the pin out for this mode When configured in this mode the sequential part of the DMC becomes a shift register SHR with load and enable The shift direction is always towards the most significant bit MSB The load control signal is the E pin and it is active high a high level loads data from the R7 R5 R3 and RI inputs into the SHR The IAUXI pin is the enable control signal and it is also active high The IAUX2 pin is the serial path where the incoming bit stream comes from The COUTS output pin drives out the output serial stream Several DMCs can be joined together to form larger SHRs connecting
47. that can be independently configured except for the 4 bit adder mode Each tile can be configured in one of the four operating modes simple combinational complex combinational multiplexer and memory mode The two tiles are equivalent except in the complex combinational mode Therefore there are 17 static operating modes for the combinational part of the DMC two tiles four modes per tile plus the 4 bit adder mode In the same manner there are 17 dynamic operating modes 1 2 1 Static Operating Modes To configure the upper tile in a static mode the CCR bit must be reset to zero This is the only difference between the configuration of any static mode and its dynamically reconfigurable counterpart Each combinational tile can be independently configured in a static or dynamically reconfigurable mode configuration bit CCR 1 2 1 1 Simple Static Combinational Mode In this mode the tile performs two independent 4 input combinational functions sharing 2 of them as depicted in figure 1 3 In this figure both tiles are configured in this Simple Static Combinational Mode although they do not have necessarily to be configured in the same mode GS SIDSA Semiconductor Design Solutions Fig 1 3 Simple Static Combinational Mode CCMA1 CCMB1 0 CCMA0 CCMB0 0 CCR 0 For the Simple Static Combinational Mode the configuration data is CCMA1 0 and CCMB1 0 for the upper tile and CCMA0 0 and CCMBO 0 for the lower tile CCR mu
48. the COUTS signal of the less significant slice to the IAUX2 port of the next DMC Fig 1 23 Counter Macro Mode CS1 0 CS2 CS3 0 The E pin is the load control signal and it is active low a low level applied to this signal causes the data To configure the sequential part of the DMC as a 4 from R6 R4 R2 and RO to be loaded info the bit Shift Register configuration bit CS1 must be reset to zero CS2 must be set to 1 and CS3 must be reset to zero These values must be fulfilled in the whole four FFs Of course the FFs must be configured as counter The IAUXI signal controls the direction of the counter IAUXI 1 upwards IAUX1 0 downwards IAUX2 is the carry in input for the counter and COUTS is the carry out signal Several actual FFs not as latches DMCs can be connected to form a larger counter just by driving the COUTS signal to the IAUX2 input in the next DMC The carry in input of the least significant tile in the counter can be used as the enable signal To configure the sequential part of the DMC as a 4 bit Counter configuration bits CS1 CS2 and CS3 must be reset to zero These values must be fulfilled in the whole four FFs Of course the FFs must be configured as actual FFs not as latches 1 3 4 Configuration table We include hereby a reference table table 1 3 to help the user to configure a given FF It must be remembered that CS1 is shared by the four FFs of Fig 1 22 Shift Register Macro
49. this bits is set the hardware swap command can be issued CCA This bit configures the combinational block as a 4 bit adder CCMAx and CCMBx must be set to zero to use the combinational block as a 4 bit adder CCO When reset to zero this bit provides user control over the output buffers As it can be seen in figures 1 8 and 1 14 the output control signals OE1 and OEO are the or function of this bits and IAO and IBO respectively for each tile This configuration bit should only be used to control the output buffers when building larger memories although they can be used at any moment For normal operation output buffers always enabled this bit must be set to one CR5 CRO These bits configure the internal router that connects the combinational block to the sequential part of the DMC See section 1 4 Internal Routing Resources for details CR6 CR9 These bits configure the multiplexers for the auxiliary output signals OAUX1 and OAUX2 See section 1 4 Internal Routing Resources for details CRO3 CRO0 These four bits configure the output multiplexers to selectively drive through the output pins 03 00 the output signals from the combinational or sequential part of the DMC See section 1 4 Internal Routing Resources for details CS1 The CS1 bit enables the 4 bit macro modes for the sequential part of the DMC when set to zero If set to one the four FFs are configured independently through the CS2 and CS3 configuration bits
50. tile IBO for the lower tile and it is active high select on high level The read write line is IA5 for the upper tile IB5 for the lower tile and it is active high read on high level write on low level The input data bus is D3 D2 for the upper tile and D1 DO for the lower tile The output buffers can be controlled by the chip select lines if the output control option is enabled CCO set to low If this bit is set to high the output buffers are always enabled If set to low the output buffers are enabled when the chip select lines inputs TAO and IBO are active With this technique one can build larger memory blocks In figure 1 14 it can be observed the combinational part of the DMC when both tiles are configured as dynamic memory blocks 10 Fig 1 14 Dynamic Memory Mode both tiles CCMA1 CCMA1 1 CCMB1 CCMB0 0 CCR 1 All combinations of the memory mode and simple complex and multiplexer configurations apply and can be derived from the wiring described in the complex combinational modes section As it can be seen when both tiles are used to implement a 8x4 RAM memory all of the inputs to the DMC are not used except the auxiliary inputs IAUXI and IAUX2 and therefore the sequential part could only be used in a macro mode shift register counter or to latch or clock the data out of the RAM In this dynamic mode two contexts are stored for each tile This means that a 8x2 RAM memory block can exist as a v
51. to configure the IO cell as an output and the corresponding negctrl bit is zero the corresponding Ctrl input has to be routed to a logical 1 EnIn1 EnIn0 These bits enable the input buffer connected to the external pin When the corresponding EnlIn pin is set to one the input buffer is enabled and therefore the corresponding CIPO signal will reflect the values read from the external pin direct or negated depending on the corresponding negin bit If this bit is reset to zero the input signal coming from the bonding pad will be ignored and replaced with a constant low level The actual value of the corresponding CIPO signal would depend therefore on the value of the corresponding negin bit which therefore can be used to set constant stimuli on input pads for system emulation pullup1 pullup0 These bits enable the 10KQ pull up resistors connected between Vpp and the bonding pad When set to one the corresponding resistor is connected pulldown1 pulldown0 These bits enable the 10KQ pull down resistors connected between Vss and the bonding pad When set to one the corresponding resistor is connected dr up1N 2 0 dr up0N 2 0 These bits regulate the rising driving strength of the output buffers in linear steps from zero disabled to seven maximum strength When the selected value is zero the pull up transistor of the corresponding buffer is disabled therefore allowing an open drain pull down operating mode if th
52. ut function is carried out by one of the outputs In figure 1 10 it can be seen both tiles configured in the Complex Dynamic Combinational Mode C3 and CI carry out two independent 4 input combinational functions while C2 multiplexes these outputs TAO controls the multiplexer transmitting the upper function when IA0 1 and the lower when IA0 0 and CO performs an AND function of these outputs and the IBO input This mode correspond to CCR 1 with CCMA 1 CCMA0 1 CCMB1 CCMBO 1 Fig 1 10 Dynamic Complex Combinational Mode CCMA1 CCMA0 1 CCMB1 CCMBO0 1 CCR 1 The dynamic mixed modes one tile in Complex mode and the other one in Simple mode are depicted in figures 1 11 and 1 12 The configuration data is CCMAI CCMBI 1 and CCMAO CCMBO 0 to have the upper tile in Complex mode and the lower tile in Simple mode Fig 1 11 and CCMA1 CCMB1 0 and CCMA0 CCMB0 1 the other way round Fig 1 12 In these figures DMCs are configured as dynamically reconfigurable CCR 1 SIDSA IB2 mi 3LUT m Fig 1 11 Upper Complex Lower Simple Dynamic Combinational Mode CCMA1 CCMBI 1 CCMA0 CCMB0 0 CCR 1 Fig 1 12 Upper Simple Lower Complex Static Combinational Mode CCMA1 CCMB1 0 CCMA0 CCMBO0 1 CCR 1 Finally it should be remembered that two contexts are stored for each dynamically reconfigurable tile 1 2 2 3 Dynamic Multiplexer Mode Each combinational tile can be configured as a 4 to 1 multiplexer The behavior of the
53. utComp lt 3 gt OutComp lt 2 gt OutComp lt l gt OutComp lt 0 gt hwINTI PLIND lt 7 gt PLIND lt 6 gt PLIND lt 5 gt PLIND lt 4 gt PLIND lt 3 gt PLIND lt 2 gt PLIND lt 1 gt PLIND lt 0 gt OC d U Ro oU O0 oyo t9 0 ada x cO t o nu amp t o o r HO NURUAN go ovulo vu eU O0 Jo y WISDEN d r o o o o d Table 3 1 Connections between the FPGA and the CAB and uP through IIC ports 24 3 4 2 IIC routing resources Figures 3 4 and 3 5 show the complete routing architecture of IICs The six IICs are located on the bottom side of the chip pushed to the right just on top of the microprocessor area In general the routing resources at the surroundings of the IICs closely follow the architecture established for the DMC At least the number and distribution of channels the independent switches and the switching matrices have been strictly kept to provide a consistent periphery to the DMC array Therefore every DMC is surrounded by exactly the same routing environment regardless of how near it is to a peripheral side of the chip The routing resources for IIC input signals are implemented using input multiplexers so each IIC input can only be connected to one routing channel only one of the interconnection switches that connect a given input signal can be activate at the same time Each input signal can always be connected to VDD and GND The routing resources for t
54. wn is also provided for input configurations 2 1 Block Diagram and VO Pins A simplified block diagram of the DMC can be seen in Figure 2 1 schematically shows a digital programmable IO Block IOB Fig 2 1 Simplified diagram of a programmable IO block Chapter 2 FIPSOC Programmable Logic Semiconductor Design Solutions 2 1 1 VO signals The signals marked with arrows are global I O pins for each IOB All of them are described hereby COPI1 COPI0 The COPI Core Out Pad In signals are outputs from the core and inputs to the IO Cell A COPI signal is driven to the PAD when the IO Cell is configured as an output CIPO1 CIPO0 The CIPO Core In Pad Out signals are inputs to the core and outputs from the IO Cell A CIPO signal is read from the PAD and driven towards the DMCs when the input buffer of the IO Cell is enabled that is when the corresponding configuration bit EnIn is 1 Ctrl1 Ctrl0 These signals are outputs from the core and inputs to the IO Cell They are used as an output enable control terminal for the output buffers in the bi directional mode Routing a logical 1 to this signal configures the pad as pure output while using a O leaves it as pure input PAD1 PADO These are the bonding pads connected to the external leads of the chip package 2 1 2 Internal signals The names given to the internal signals used in the IOBs as described in the block diagram figure 2 1 are the fol
55. x Matix PE IC E IC D lC c IC B Clock A Clock Clock Clock Clock Clock Clock Clock Buffers J Buffers T 9 9 pues Buffers T Buffers T Buffers T Buffers T Butters T FE e E 5 t lee ee ee Micrprocessor 08 Analog Block P Fig 1 1 The FIPSOC FPGA Structure overview The combinational part of the DMC can also be configured as a 4 input adder with carry in and carry out This adder can be expanded connecting more DMCs to the carry pins and fits in one context that is the DMC can be used as an adder in one context and as general purpose LUTs in the other one Finally each tile that is every two LUTs can be used as a stackable RAM memory block 16x2 RAM in the normal modes 8x2 RAM in each context in the dynamic modes The sequential part of the DMC is also 4 bit wide It includes four flip flops than can be individually configured as D type with enable mux type and 4 bit macro functions Each FF can be individually configured with normal or negated output and each of the two reset mechanisms global and local can be individually selected as reset or set The global reset is always asynchronous while the local reset can be selected to be synchronous or asynchronous for the four of them not individually The clock polarity and a latch FF mode can also be set for the four FFs The 4 bit macro functions provide an o
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