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TC1024 Userts Manual - RTD Embedded Technologies, Inc.

1. Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 2 Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 2 and then write the resulting value to the port In BASIC this is programmed as V INP PortAddress V V AND 223 OUT PortAddress V 4 6 set a single bit in a port OR the current value of the port with the value b where b 291 Example Set bit 3 in a port Read in the current value of the port OR it with 8 8 2 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress VOR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255
2. aa tu Reload Source ome o o a 1 memo Jo Y o vj Gate Control 15 0 13 ooo LEVEL EDGE LEVEL EDGE 000 LEVEL EDGE 000 LEVEL EDGE Countto once ndm j Count to TC twice then disarm ctr Count to TC repeatedly without disarming Jd xu qc A A X sl e E 3 A Gate input does counter input Count only during active gate level Start count on active gate edge and stop count on next TC Start count on active gate edge and stop count on second EBD No hardware retriggering BE TC that gate is LOW transfer Hold Register x x into counter on each TC that gate is HIGH On active gate edge transfer counter into Hold Register and then reload counter from Load Register On active gate edge transfer counter into Hold Register but counting continues Notes 1 Counter modes M P T U and W are reserved and should not be used 2 Mode X is available for Am9513A oniy Reload counter from Load Register on TC Reload counter on each TC alternating reload source between Load and Hold Registers Transfer Load Register into counter on each Figure 1 16 Counter Mode Operating Summary 1 11 COUNTER DESCRIPTIONS Counter Mode register bits CM15 CM13 and 7 5 select the
3. Non Retriggerable One Shot mea fx tx x xix EE NENE MESE NENES Mode F shown in Figure 1 17f provides a non retriggerable one shet timing function The counter must be armed before it will function Application of a Gate edge to the armed counter will enable counting When the counter reaches TC it will reload itself from the Load register The counter will then stop counting awaiting a new Gate edge Note that unlike Mode C a new ARM command is not needed after TC only a new Gate edge After application of a triggering Gate edge the Gate input is disre garded until TC ae AN TC TOGGLED OUTPUT A COUNT VALUE RI MODE G Software Triggered Delayed Pulse One Shot lacio lea ajos in Mode G the Gate does not affect the counter s operation Once armed the counter will count to TC twice and then automatically disarm itself For most applications the counter will initially be loaded from the Load register either by a LOAD command or by the last TC of an earlier timing cycle Upon counting to the first TC the counter will reload itself from the Hold register Counting will proceed until the second TC when the counter will reload itself from the Load register and automatically disarm itself inhibiting further counting Counting can be resumed by issuing a new ARM command A software triggered delayed pulse one shot may be generated by specifying the
4. TC1024 User s Manual 1509001 and 9100 Certified Real Time Devices Inc Accessing the Analog World TC1024 User s Manual IED REAL TIME DEVICES INC Post Office Box 906 State College Pennsylvania 16804 Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc P O Box 906 State College PA 16804 Copyright 1992 by Real Time Devices Inc All rights reserved Printed in U S A Rev 9411 Table of Contents INTRODUCTION 0s0s0000r00000000000002000000000002020000000220000000 v Am9513A Timer Ca 1 3 Digital VO nee M i 3 What Comes With Your Board siessen e iss Vaiee E i 3 Board Accessorles 2 i 3 Using This Manual 1 4 When You Need Help en 1 4 CHAPTER 1 BOARD SETTINGS M 1 1 Factory Configured Switch and Jumper Settings 1 3 P5 Counter OUT 2 5 Interrupt Channel Select Factory Setting Interrupt Channels Disabled 1 4 P6 Counter OUT 7 10 Interrupt Channel Select Factory Setting Interrupt Channels Disabled 1 4 P7 Interrupt Source Channel Select Factory Setting No Connection sse 1 4 S1 Base Address Factory Setting
5. 231256 2 Figure 2 82C55A Pinout Diagrams are tor pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel 82 55 Table 1 Pin Description Pin Number symbol Dip PLCC Name and Function PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch RB 5 e READ CONTROL This input is low during CPU read operations control the selection of one of the three ports or the contro ual ha CHIP SELECT low on this input enables the 82 55 to word registers respond to RD and WR signals RD and WR are ignored so 0 Ao RD WR CS input Operation Read _ 1 Pora DataBus _ 1 4 __ _ Porc DataBus o t o conto word DataBus 1 DataBus Pota _ 1 DataBus PonB ADDRESS These input signals in conjunction RD and WR otherwise 1 DaaBus Pono DataBus Gontrol Disable Function EX x x X 3 DataBus a Siate LX x 1 DaaBus 3 stats PORT C PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch a
6. C D Control Data Input The Control Data signal selects source and destination locations for read and write operations on the data bus Control Write operations load the Command register and the Data Pointer Control Read operations output the Status register Data Read Data Bus Width MM14 16 Bits 8 Bits Package Figure 1 6 Data Bus Assignments and Data Write transfers communicate with all other internal registers Indirect addressing at the data port is controlled inter nally by the Data Pointer register Interface Considerations of the input and output signals for the Am9513 are specified with logic levels compatible with those of standard TTL circuits See the Am9513 data sheet for specifications In addition to providing TTL compatible voltage levels other output conditions are specified to help configure non standard interface circuitry The logic level specifications take into account all worst case combinations of the three variables that affect the logic level thresholds ambient temperature supply voltage and processing parameters A change in any of these toward nominal values will improve the actual operating margins and will increase noise immunity Unprotected open gate inputs of high quality MOS transistors exhibit very high resistances on the order of perhaps 1014 ohms It 15 easy therefore in some circumstances for charge to enter the gate node of such an input faster than it can be d
7. With a Set Reset Port C Bit command any Port C line programmed as an output including INTR IBF and can be written an interrupt enable flag can be either set or reset Port C lines programmed as inputs including and STB lines associated with Port C are not affected by Set Reset Port Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current intel 82C55A Reading Port C Status INPUT CONFIGURATION D Dg Ds Dz D3 Dz Di Do In Mode 0 Port transfers data to or from the pe ripheral device When the 82 55 is programmed to function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de GROUP B vice Reading the contents of Port C allows the pro OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe D7 Ds Ds D4 D3 D2 D4 Do device and change the program flow ac ARE dr cer ires vo vo rna res 68 s NTR GROUP A GROUP B There is no special instruction to read the status in formation from Por
8. 0 01050500005 00000000 00000000 4000000000000 938 784 32 1 20000000 500000000 000000000000 013 game 08088 D o ise 00000000 0000000000 0000000000 0000000000 9000000000 99999999995 PP 10000000000 0000000000 0000000000 u c16 15 14 12 11 18 976545 om E0 P2 P1 Fig 1 1 Board Layout Showing Factory Configured Settings 1 3 P5 Counter OUT 2 5 Interrupt Channel Select Factory Setting Interrupt Channels Disabled This header connector shown in Figure 1 2 lets you connect the output of counter 2 or 5 whichever is selected on S4 1 to any of 11 interrupt channels IRQ9 highest priority channel through IRQ12 IRQ14 IRQ15 and then back to IRQ3 through IRQ7 lowest priority Chapter 4 explains interrupt channel prioritization in detail To activate a channel you must install a jumper across the desired IRQ channel Figure 1 2a shows the factory setting Figure 1 2b shows the interrupt source connected to IRQ3 If you use multiple interrupts make sure each source is assigned to a different IRQ channel 5 Q Fig 1 2a c Factory Setting 5 IRQ 15 14 121110 9 7 6 5 4 3 P5 Fig 1 2b Interrupt Source Connected to IRQ3 S IRQ 15 14 121110 9 7 6 5 4 3 Fig 1 2 Counter OUT 2 5 Interrupt Channel Select Jumper P5 P6 Counter OUT 7 10 Interrupt Channel Select Factory Setting Interrupt Channels Disabled This header conn
9. All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel 82C55A BIDIRECTIONAL DATA BUS 231256 3 EXTERNAL INTERNAL PORT A DATA IN PIN INTERNAL DATA OUT EXTERNAL PORT PIN INTERNAL DATA NOTE 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration 3 127 A ee nn AL un ce AR 82 55 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that
10. FOUT Source 0000 Fi 0001 SRC 1 0010 SRC 2 0011 SRC 3 0100 SRC 4 0101 SRC 5 0110 1 0111 GATE 2 1000 3 1001 GATE 4 1010 GATE 5 1011 F1 1100 F2 1101 F3 1110 1111 25 L Four Gate 0 FOUT On 1 FOUT Off Low Z to GND Data Bus Width 0 8 Bit Bus 1 16 Bit Bus Data Pointer Control O Enable increment 1 Disable increment Scaler Control 0 Binary Division 1 BCD Division Compare 2 Enable 0 Disabled 1 Enabled Compare 1 Enable 0 Disabled 1 Enabled Time of Day Mode 00 TOD Disabled 01 TOD Enabled 5 Input 10 TOD Enabled 6 Input 11 TOD Enabled 10 Input Figure 1 13 Master Mode Register Bit Assignments Time of Day Bits MMO and 1 of the Master Mode register specify the Time of Day TOD options When 0 and 1 O the special logic used to implement TOD is disabled and Counters 1 and 2 will operate in exactly the same way as Counters 3 4 and 5 When 1 or MM1 1 additional counter decoding and control logic is enabled on Counters 1 and 2 which causes their decades to tum over at the counts that generate appropriate 24 hour TOD accumulations For additional information see the Time of Day chapter in this applications note Comparator Enable Bits MM2 and MM3 control the Comparators associated with Counter 1 and 2 When a Comparator is enabled its output is substituted for the normal counter ou
11. Lo o o ourur ourur o output BERE Bo Eg _ o o 1 output output Lo o o ourrur output Lo 1 ourur ourrur o oureur input 4 output 0 3 ourur 5 ourrur weur jo 1 1 o ourur e o 3 1 1 ourur 7 PUT _ outeur s oureur ourur 1 wer outeur e ourur PUT __ 1 1 o ourur 10 eur ourur L3 1 meur ourur 1 weur wer MEERE oM 15 1 t wer o eur weur oo weu wer L1 fos 1 ner MODE 0 Configurations CONTROL WORD 0 CONTROL WORD 2 D D D D O D D D 04 D D 0 D 0 CONTROL WORD 1 CONTROL WORD 3 D 06 f 04 0 D D Dy D D D D D 0 3 131 intel 82C55A MODE 0 Configurations Continued CONTROL WORD 4 CONTROL WORD 8 D De D D D D D 0 D D D D D 0 D CONTROL WORD 95 CONTROL WORD 9 D D D D 0 0 D Dy 0 De 05 D Do 0 D CONTROL WORD 06 CONTROL WORD 10 D D D D 0 D D D Dg 05 0 D D D D CONTROL WORD 7 CONTROL WORD 11 PISIS Ds 04 0 D D O De Os Dj D3 0 Oo 5 PCy PCy 231256 11 3 132
12. 5 9 5 arm counting tor an sited counters 9 s 9 ss S Load comens o source mo al selected counters Tops 8 9 S _ a s s and Save al electo counters 3 As s 51 Save al electos counters in Hal register 3 3 9 9 _ a M Set Togo out igh for counter 0 N T fo M lar Toga ot Low for counter lt 1100 ___ ECETIA 5 9 Poter Sequencing _ Gp fe ft ft ft ewweeesroun tt mods Tae fs fo 9 0 cer ms enable Data Panter Sequencing ______ t 0 Ca p 9eMwsEnesbbemd E Bp AN Enable Prefetch for Write operations Am9513 A only 3 E 0 1 Bical Petts tor operaons AMOS _________________ Not to be used for asynchronous operations Figure 1 21 Am9513 Command Summary In modes which alternate reload sources Modes G L the ARMing operation is used as a reset for the logic which deter mines which reload source to use on the upcoming TC Following each ARM or LOAD and ARM a counter in one of thes
13. Interrupt Occurs 4 10 Using Interrupts in Your Programs 4 10 Writing an Interrupt Service Routine ISR essen 4 10 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector eene 4 11 Restoring the Startup IMR and Interrupt Vector 4 12 Common Interrupt Mistakes eese eene ntnnnetennnntnenntntn thee tn tn 4 12 Example Programs 4 12 and Pascal Programs 4 12 BASIC Programs sscocssssssonssesssssesnescoessorsoonosesssessassossnscsscncscetsesscauseeesesssnencanesscsaeneeceasanacererensscosessserssneneetos 4 12 CHAPTER 5 EXAMPLES Am9513A APPLICATIONS ussesoesnesosseonesneonenessnsnsennsnnnaresesonsnee 5 1 EXAMPLE Counting Program Using Timer Counters 1 2 and 3 sse 5 3 APPENDIX A TC1024 SPECIFICATIONS eere eee eene enean atas e rasta tantas sense ette tenete eee A 1 APPENDIX B AND P4 CONNECTOR PIN ASSIGNMENTS e esee eee eee nete eene entnaon B 1 APPENDIX COMPONENT DATA SHEETS 0 0s00ur00200000000r0ne00se0ne0nsoneeunennnennenosennensensssuncen C 1 APPENDIX D WARRANTY ssssosssosssnssnnesonssnesnussunssonssnsssnssnsssnsnnnensnsssennsnsnsssnunsusenunsnnnnnsnnnenenes sos D 1 List of Illustratio
14. 0012 0012 0012 0012 0016 09184 90918 09184 0014 00184 0014 0922 9922 9022 0022 9024 0026 0026 0026 INTERRUPT SERVICE ROUTINE NVI VI SET DATA POINTER TO COUNTER 1 HOLD REG R2 0FF 19H CMDPRT R2 co ENABLE AUTO SEQUENCING 2 2 CODE TO ACCESS REGISTERS DISABLE AUTO SEQUENCING R2 OFFESH CMDPRT R2 OTnNNNNNOTNNN 4 ENABLE INTERRUPTS AND RETURN NVI UI NN NN Ar b 28000 Code Figure 2 7 Am9513 Interrupt Service Routine 2 5 In many systems the Am9513 counters will be by inter rupt routines In such systems it is important that the Am9513 service routines not be interrupted by another Am9513 service routine while register accesses are occurring Consider for example an interrupt service routine which reads the Hold regis ter value in the Counter 1 logic group This routine will set the Data Pointer register and read the Hold register value Consider the sequence of events which would occur if after this routine set the Data Pointer registers but before it read the Hold register it was interrupted by a second Am9513 interrupt routine This second routine might for example read the Counter 3 logic group Hold register value When this second interrupt routine finishes it returns control to the last half ofthe first int
15. 2 2 26 and then write the resulting value to the port In this is programmed as v inportb port_address v amp 171 outportb port address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 23 25 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a range of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as inportb port_address amp 199 40 outportb port_address A final note Don t be intimidated by the binary operators AND and OR and try
16. C and nominal processing parameters Supply current always de creases with increasing ambienttemperature thermal run away is not a problem Supply current will vary somewhat from part to part but a given unitat a given operating temperature will exhibit a nearly constant power drain There is no functional operating region that will cause more than a few percent change in the supply current Decoupling of VCC then is straightforward and will generally be usedto isolate the Am9513 from VCC noise originating externally 1 5 CONTROL PORT REGISTERS The STC is addressed by the external system as only two loca tions a Control port and a Data port Transfers atthe Control port C D High allow direct access to the command register when writing and the status register when reading All other available internal locations are accessed for both reading and writing via the Data port C D Low Data port transfers are executed to and from the location currently addressed by the Data Pointer register Options available in the Master Mode register and the Data Pointer control structure allow several types of transfer sequencing to be used See Figure 1 8 Transfers to and from the Control port are always 8 bits wide Each access to the Control port will transfer data between the Command register writes or Status register reads and Data Bus pins DBO DB7 regardless of whether the Am9513 is in 8 or 16 bit bus mode When the Am951
17. Lower Binary Decimal 10000000 tes 10000001 129 B Output 10000010 130 10000011 131 10001000 136 10010001 145 10010010 146 10010011 147 10011000 152 10011001 Output 10011010 10011011 4 4 When bit 7 of this word is set to 0 a write can be used to individually program the Port lines Set Reset Bit Set Reset Function Bit Bit Select 0 set bit to O 0 active 000 1 set bit to 1 001 PC1 010 2 011 100 PC4 101 5 110 6 111 7 For example if you want to set Port C 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects and bit 0 is 1 this sets to 1 The control word is set up like this Sets to 1 written to BA 6 X don t care Set Reset Set PCO Function Bit Bit Select 000 IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip BA 8 Am9513A 1 Data Register Read Write 16 bit operation after initialization Accesses the Am9513A data register for counters 1 5 This chapter explains initialization procedures See the example programs in Chapter 5 and the data sheet included in Appendix C for more information on the operation of the Am9513A BA 10 Am9513A 1 Command Register Read Write
18. TC and represents the period in time that the counter reaches an equiva lent value of zero TC will occur on the next count when the counter is at 0001 for down counting at 9999 BCD for BCD up counting or at FFFF hex for binary up counting Figure 1 20 shows a Terminal Count pulse and an example context that generated it The TC width is determined by the period of the counting source Regardless of any gating input or whether the counter is Armed or Disarmed the terminal count will go active for only one clock cycle Figure 1 20 assumes active high source polarity counter armed counter decrementing and an external reload value of K The counter will always be loaded from an external location when TC occurs the user can choose the source location and the value If a non zero value is picked the counter will never really attain a zero state and TC will indicate the counter stat that would have been zero had no parallel transfer occurred Count Source Selection Count Control 0000 TCN 1 0 Disable Special Gate 0001 SRC 1 Enable Special Gate 0010 SRC2 Reload from Load 0011 SRC3 Reload from Load or 0100 SRC4 Except in Mode X Which 0101 SRC5 Reloads Only from Load 0110 GATE 1 Count Once 0111 GATE 2 1000 GATE 3 Count Repetitively Binary Count 1001 BCD Count 1010 1011 Count Down 1100 Count Up 1101 1110 1111 ens ome ore ore om ow ow ou ow To TT cola ee n n
19. The sequence then is to Reset the device Load all counters Command 16 bit mode set Data Pointer to the Master Mode Register set Master Mode Register to desired value set Data Pointer to counter 1 Mode Register and initialize counters to desired mode of operation Note CS must be high during power up or the internal reset circuitry will not function correctly This will result in part ignoring all commands issued to it except software reset Command Initiation Commands are issued to the Am9513 by writing the appro priate command code to the Am9513 Control Port Figure 2 6 shows an example of command initiation in this case opcode MACKO80 00 Version 2 0 9S13INIT 5 gt 0 INIT 0000 0000 0000 0000 0000 0000 0000 0000 0000 0004 0008 0006 0010 0014 0018 FFI7 opic 0012 020 2 0024 0010 0028 FF01 002C 0012 0030 0030 MODULE INIT 5 CONST 0012 0012 0012 INIT LD OUT LD OUT LD OUT LD OUT LD END 9 19 80 Signal Contiguration Data Bus Es cio Ro W8 Operation Transfer contents of register addressed by Data Pointer to the data bus Transfer contents of data bus to data register addressed by Data Pointer Transfer contents of Status register to data bus Transfer contents of data bus into Command register IX X 1 1 Notranster No transfer Ux x e o wercmawn Figur
20. and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC4 INTE B Controlled by bit set reset of PC INPUT FROM PERIPHERAL MODE 1 PORT A CONTROL WORD D D 0 0 D O D D D 13 PCa Y 0 OUTPUT CONTROL WORD D 0 Dy D 0 D O XII D 231256 13 Figure 8 MODE 1 Input 231256 14 Figure 9 MODE 1 Strobed Input 3 134 intel 82C55A Output Control Signal Definition OBF Output Buffer Full F F The OBF output will MOOE 1 PORT go low to indicate that the CPU has written data CONTROL WORD out to the specified port The F F will be set b D D Dy 0 D 0 D the rising edge of the WR input and reset by ACK Input being low 1 INP Acknowiedge Input A low on this input o ouTPuT informs the 82C55A that the data from Port A or Port B has been accepted essence a response from the peripheral device indicating that it has received the data output by the CPU MODE 1 PORT 8 INTR Interrupt Request A high this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU WORD INTR is set when ACK is a one OBF is a one an and INTE is a one It is reset b
21. it is important that the high and low order counters be initialized to L 1 and H 1 respectively prior to the first timing cycle Note that if the Counter 1 source period is less than the propagation delay from Counter 1 s source through Counter 2 s output through the two flip flops to the OR gate then the low order counter s contents at the end of a count cycle may be offset by a few counts In such cases the value used to initialize the counters should be similarly offset 3 5 The previous count down concatenation examples have as sumed the counters are to count repetitively To add count once capability to a count down configuration the high order counter should be programmed to generate a TC Toggled output waveform This output should be used to gate source pulses through an AND gate into the low order counter as shown in Figure 3 10 The count cycle will now appear as shown in Figure 3 11 Note that when the counters stop the high order counter s output will be low and the low order counter s contents will be 9999 To reset the counters for another timing cycle a LOAD command should be issued to the low order counter which will Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint COUNTER 1 INTERNAL TC SOURCE Counter 1 Mode Register COUNTER 2 Counter 2 Mode Register MOS 617 Figure 3 10 Count Down Concatenation with Count Once Feature CLEAR HIGH ORDER OUTPUT COMM
22. l COUNTER PIN 7 d snc 2 2 CEDEIRA 11 Jour 2 COUNTER 1 PIN 13 3 EA PIN 15 1 gare 3 l i COUNTER PIN 19 ASRC 4 1 ein 29 dour 5 CCAA S4 1 1 O a TO 1 IRQ HEADER oe AM9513 2 03 54 3 I COUNTER 9 PiN2 a snce 6 1 PIN 4_AGATE 6 1 i 1 1 COUNTER PINS ISRC7 7 Y 587 PIN 10 SGAE 7 1 1 PIN 12 Lour 7 1 1 I 1 1 COUNTER PIN 14 sac 1 es ren PIN 16 GATE 8 Lour a 1 1 1 COUNTER I PIN 20 1 src 9 1 EN cv m i i 1 PIN 24 Lour 9 1 1 1 1 counter PIN 26 SRC 10 1 10 Y EA PIN 28 Gare 10 Zoe Pin 30 Our 10 I 84 2 Lo ete Q TO P6 5 O IRQ HEADER Fig 1 9 Counter Circuitry Showing S4 Switch Connections Pull up Pull down Resistors on Digital O Lines The 8255 programmable peripheral interface provides 24 TTL CMOS compatible digital T O lines which can be interfaced with external devices The lines are divided into four groups eight Port A lines four Port C Lower lines eight Port B lines and four Port C Upper lines You can install and connect pull up or pull down resistors for any or all of these four groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull down lines connected to relays which contr
23. 12 and the Control Register port is at BA 14 In our example programs follow these steps to initialize the Am9513A Note that until you point to and set up the master mode register in step 2 you must send your commands in 8 bit format After the master mode register has been configured for 16 bit operation by setting bit 13 to a logic 1 you can then send 16 bit words to the Am9513A 1 Send a master reset to the Am9513A 8 bit 2 Point to and set up the master mode register 8 bit When setting up the master mode register set MM13 to logic 1 so that you can do 16 bit transfers 3 Point to and set up counter 1 mode register 16 bit 4 Point to counter 1 load register and load desired value 16 bit 5 Point to and set up counter 2 mode register 16 bit 6 Point to counter 2 load register and load desired value 16 bit 11 Point to and set up counter 5 mode register 16 bit 12 Point to counter 5 load register and load desired value 16 bit 13 Load and arm counters 16 bit The examples on the disk and in Chapter 5 will aid you in programming the Am9513A for your application These tools and the data sheet in Appendix C provide a comprehensive description of timer counter operation IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip Initializing the 8255 Before you can use the 24 digital I O lines on your TC1024 the 8255 PPI must be initialize
24. 2 AND MODE 1 OUTPUT CONTROL WORD D De 05 D Dz D D D bg 82 MODE 2 AND MODE 0 OUTPUT CONTROL WORD D D 0 O O 0 D D lo 25 INPUT MODE 2 AND MODE 1 INPUT CONTROL WORD D D 05 D D3 D D Do IUDA VU 231256 21 Figure 16 MODE Y Combinations 3 138 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 and PC6 bit positions as illustrated by Figure 18 Through a Write Port command only the Port pins programmed as outputs in a Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to 3 139 82C55A GROUP A ONLY MODE O OR MODE 1 ONLY lt gt lt gt lt gt gt lt gt lt gt gt gt change an interrupt enable flag the Set Reset Port C Bit command must be used
25. 300 hex 768 decimal 1 5 S2 and S3 Buffer Bypass Switches Factory Setting OPEN Not 4 esee 1 6 S4 Interrupt Source Clock Source Select Factory Setting OUTS OUT10 EXT6 1 8 Pull up Pull down Resistors on Digital VO Lines eee nennen nnne 1 10 RC Filters on Source Clock Input Lines eese eerie tntntntntntntntn 1 12 CHAPTER 2 BOARD INSTALLATION eeeee eee esenena ento ses tn ese sn tns enen sensns es ensesenseseesenese enses e 271 Board Installation I mm 2 3 External VO Connections tese 2 3 Connecting the Timer Counters and Digital 2 4 Running the 1024DIAG Diagnostics Program 2 4 CHAPTER 3 HARDWARE DESCRIPTION eere eee s esta sene en santos ensensensosenseoseosessensessensess S L Am9513A Timer 3 3 Digital Programmable Peripheral Interface 3 3 3 4 CHAPTER 4 BOARD OPERATION AND PROGRAMMING Defining the VO Map H 4 3 0 PPI Port Digital VO Read Write 4 3 BA 2 PPI Port B Digital YO Read Write 4 3 4 PPI Port C Digital VO Read Wr
26. Figure 3 9 uses an external gate signal to set an enabling flip flop The enabling flip flop is cleared when both counters reach TC The delay flip flop ensures that one additional count occurs after both counters reach TC in order to drive the low order counter out of TC thereby deactivating the enabling flip flop s clear input Note that the counters stop at an unusual point in the count sequence L 1 H 1 in Figure 3 7 or 3926 4177 for the earlier example but this is not important LOW ORDER OOO OOOO VALUES LOW ORDER AE e 1 X L X t 1 K X K 1 HIGH ORDER Count Down with Edge Gating Stops Here TC Dn rs Figure 3 7 Timing Waveforms for Am9513 Count Down Concatenation MOS 614 SYNCHRONIZING FLIP FLOP Counter 1 Mode Register COUNTER OUT INTERNAL TC 15 0 som oor Counter 2 Mode Register MOS 615 Figure 3 8 Count Down Concatenation with Level Gating ENABLING FLIP FLOP DELAY FLIP FLOP Am9513A Am9513 GATE TC SOURCE NTER OUT cou 15 0 15 0 ox emm ooo Counter 1 Mode Register Counter 2 Mode Register MOS 616 Figure 3 9 Count Down Concatenation with Edge Gating since the timeout duration remains constant at L 1 H for Figure 3 7 and 3926 4178 for the earlier example To ensure that the counters first timing cycle has the same timeout duration as subsequent timing cycles
27. GATE 2A VSS GND Top View Pin 1 is marked tor orientation MOS 172 Figure 1 4 Connection Diagram Signal Abbreviation Pins 5 Volts Power Ground Power Crystal 1 Read input Write Input Input Input Input Input VO Output Output Chip Select Control Data Source N Gate N Data Bus Frequency Out Out N a Figure 1 5 Interface Signal Summary select between two counter output frequencies All gating func tions may also be disabled The active Gate input is conditioned by an auxiliary input when the unit is operating with an external 8 bit data bus See Data Bus description Schmitt trigger circuitry on the GATE inputs allows slow transition times to be used SRC1 SRC5 Source Inputs The Source inputs provide external signals that may be counted by any ofthe counters Any Source line may be routed to any or all of the counters and the FOUT divider The active polarity for a selected SRC input is programmed at each counter Any duty cycle waveform will be accepted as long as the minimum pulse width is at least half the period of the maximum specified counting frequency for the part Schmitt trigger circuitry on the SRC inputs allows slow transition times to be used OUT1 OUT5 Counter Outputs Each 3 state OUT signal is directly associated with a corre sponding individual counter Depending on the counter config uration the OUT signal may be a
28. Interrupt Mask Register and Interrupt Vector The next step after writing the ISR 15 to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR for IRQO IRQ7 is located at I O port 21H the IMR for IRQ8 IRQ15 is located at I O port A1H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 four byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for IRQO IRQ7 are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on The vectors for IRQ8 IRQ15 are vectors 70H through 77H where IRQ8 uses vector 70H IRQO9 uses vector 71H and so on Thus if the TC1024 will be using IRQ15 you should save the value of interrupt vector 77H Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H for IRQO IRQ7 or at I O port A1H for IRQ8 IRQ1S5 and set the bit that corresponds to your IRQ 4 11 remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The on 8
29. S1 the base address switch to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Factory Settings Function Controlled Jumpers Installed Connects the output of counter 2 or 5 to an interrupt channel 4 selects which counter is available Interrupt channels disabled Connects the output of counter 7 or 10 to an interrupt channel S4 selects which counter is available Interrupt channels disabled Connects any of 11 interrupt sources to any of 11 interrupt channels connection made by wire wrapping between selected header pins No connection Sets the base address 300 hex 768 decimal Bypasses 8255 Port C buffers for Mode 1 or Mode 2 operation Open buffers not bypassed Bypasses 8255 Port A buffers for Mode 2 operation Open buffers not bypassed Selects the interrupt sources to be available at P5 and P6 selects the source for counter 1 and counter 6 OUT5 OUT10 EXT6 EXT1 1 54 o oooon 00000000 1999959 XTAL SWITCH GE Switch 200000000000000000000 Wuoo0000000 7 3908 G0000000000000000000 0009 5 74 245 89909000 1999590 0000000000 00000000000000000000 10000000005 PCI PCH RNS 90000000000000000000 0000000000 7900995 5655555 po 191024 1999998 005660 0000000000 ie USA 3968806869 ooooooo 2000000000 00000000 i 74HCT139 1000000 00000000000000000000 n 000000000000000
30. a wide variety of categories Fre quency generation waveform duty cycle control event counting interval measurement precise periodic interrupts time of day accumulation delays gap detection etc are just a few of the types of operations typically undertaken When the system must accomplish several of these activities especially when some measure of concurrency is necessary a significant portion of the available processing and or hardware logic resources can be consumed Throughput limitations easily arise A specialized circuit with enough versatility to handle many types of counting and timing functions would therefore be able to simplify software improve system performance and decrease system chip count The Am9513 System Timing Controller has been designed to accomplish just such a task It provides signifi cant capability for waveform generation counting timing and SOURCE 1 5 GATE 1 5 4 BIT COUNTER FOUT DIVIDER 8 BIT 6 BIT COMMAND DATA REGISTER POINTER 8 087 BUS BUFFER AND MUX 8 088 0815 vcc 5 M 16 BIT COUNTER 5 OSCILLATOR FREQUENCY SCALER REGISTER 8 16 16 BIT MASTER MODE REGISTER 16 POWER ON RESET intervalometer functions for many types of processor oriented systems It offers an unusually versatile control structure that allows the use of many operating configurations so that a wide variety of applications can be efficiently serviced The operating
31. as follows 1 Priorto performing the actual write operation the Data Pointer should be set to point to the register to be written to as outlined above in the Setting the Data Pointer section of this docu ment In cases where auto sequencing of the Data Pointer is used the Pointer has to be set only once to the first register in the sequence When auto sequencing is disabled repetitive accesses can be made to the same register without reloading the Data pointer each time Establish the appropriate data on the DBO DB7 lines 8 bit bus mode or DBO DB15 16 bit bus mode When using the 8 bit bus mode data bus lines DB13 DB15 should be set High during the write operation and DBO DB7 should be set to the lower data byte for the first write and to the upper data byte for the second write Establish a Low on the C D input Establish a Low on the CS input Establish a Low on the WR input n Y 011B 7 011C 0310 011 7 O11F 0310 Drive High sometime after the minimum WR low pulse duration has been achieved taking carethe CS C D and data setup times are met see Timing Diagram After meeting the required CS C D and data hold times these signals can be changed see Timing Diagram 8 After meeting the write recovery time see Timing Diagram a new read or write operation can be performed For the 8 bit bus mode steps 2 through 7 should be repeated this time placing the high data byte on pins DB
32. by 16 FOUT Gate Master Mode bit MM12 provides a software gating capability for the FOUT signal When MM12 1 FOUT is off and in a low impedance state to ground MM12 may be set or cleared in conjunction with the loading of the other bits in the Master Mode register alternatively there are commands that allow 12 to be individually set or cleared directly without changing any other Master Mode bits After power up or reset FOUT is gated on When changing the FOUT divider ratio or FOUT source transient pulses as short as half the period of the FOUT source may appear on the FOUT pin Turning the FOUT gate on or off can also generate a transient This should be considered when using FOUT as a system clock source Bus Width Bit MM13 controls the multiplexer at data bus interface in order to configure the part for an 8 bit or 16 bit external bus The internal bus is always 16 bits wide When MM13 1 16 bit data is transferred directly between the internal bus and all 16 of the external bus lines In this configuration the Byte Pointer bit in the Data Pointer register remains set at all times When MM13 0 16 bit internal data is transferred a byte at a time to and from the eight low order external data bus lines The Byte Pointer bit tog gles with each byte transfer in this mode When the Am9513 is set to operate with an 8 bit data bus width pins DB8 through DB15 are not used for the data bus and are available for o
33. can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any 1 O structure instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis CONTROL BUS PAYPA B A vo P5 8 CONTROL CONTROL PA PA OR ORO A Uo BI DI
34. commands are described in the following text Figure 1 21 summarizes the command codes and includes a brief de scription of each function Figure 1 22 shows all the unused code combinations unused codes should not be entered into the Command register since undefined activities may occur Six of the command types are used for direct software control of the counting process and they each contain a 5 bit S field In a linear select fashion each bit in the S field corresponds to one of the five general counters 51 Counter 1 S2 Counter 2 etc When an S bit is a one the specified operation is performed on the counter so designated when an S bit is a zero no operation occurs for the corresponding counter This type of command format has three basic advantages It saves host software by allowing any combination of counters to be acted on by a single command It allows simultaneous action on multiple counters where synchronization of commands is important It allows counter specific service routines to control individual counters without needing to be aware of the operating context of other counters Three of the commands use a 3 bit binary code N4 N2 N1 to identify the affected counter a 001 programs counter 1 etc Unlike the previously mentioned commands these commands allow you to program only one counter at a time Command Code ceo AAA mcm G 000 G 110
35. corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 5 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 5 shows the DIP switch set for a base address of 300 hex 768 decimal Fig 1 5 Base Address Switch S1 Base Address Switch Setting Decimal Hex 54321 Decimal Hex 54321 512 200 10000 528 210 784 310 10001 544 020 10010 576 240 10100 592 250 10101 608 260 10110 624 270 10111 11000 656 290 11001 672 2A0 11010 688 11011 704 200 11100 736 11110 7521 11111 S2 and S3 Buffer Bypass Switches Factory OPEN Not Bypassed Mode 1 Operation 52 When operating the 8255 in Mode 1 the lines of Port function as control lines some as outputs and some as inputs When using Mode 1 the Port C buffers must be removed and bypassed to allow the Port C lines to be individually set as inputs or outputs Figure 1 6 shows the Port C buffers and the following steps tell you how to configure the board for Mode 1 operation To remove buffering from Port C 1 Close DIP switches 1 through 8 on S2 2 Remove U10 from the board 3 Remove U11 from the board
36. is not required to drive CS or C D High between successive reads or writes although this is permissible As described in the Setting the Data Pointer register section the Am9513 service routines should disable interrupts during Data port register accesses if the service routine could be in terrupted by another service routine requiring access to Data port registers Figure 2 9 shows sample programs for reading a Data port register The Am8080A 8085A code reads the data in two byte reads low byte first and assembles it into the HL register pair The AmZ8002 program assumes that a 16 bit data interface is being used and reads the data into register RO in a single word read This code can be substituted into the sample interrupt service routines in Figure 2 7 in the place marked Code to Access Registers CODE TO REAL FROM DATA PORT REG DATAPRT Ly H A a 8080 Code AM9513_EXAMPLES 002A 0024 002A 002A 002 002E 002 3B24 0010 MACROBOOO AmZ8000 Assembler 1 0 1 4 CODE TO REAL FROM DATA FORT REG R2 DATAPRT b AmZ8000 Code Figure 2 9 Reading Through the Data Port 2 7 Writing to the Data Port The registers which can be written to through the Data port are the Load Hold and Counter Mode registers for Counters 1 through 5 the Alarm registers for Counters 1 and 2 and the Master Mode register The procedure for writing to these registers is
37. many in stances of course both types of counter usage will be combined to provide the desired function En EH counen ccoo COUNTER 4 LOGIC GROUP a COUNTER 3 LOGIC GROUP EE DR NI 80 COUNTER 2 LOGIC GROUP amp c COUNTER 1 LOGIC GROUP zu ES vss Figure 1 1 General Block Diagram m EUM FUNCTIONAL DESCRIPTION The Am9513 System Timing Controller STC is a support device for processor oriented systems that is designed to enhance the available capability with respect to counting and timing opera tions It provides the capability for programmable frequency syn thesis high resolution programmable duty cycle waveforms retriggerable digital timing functions time of day clocking coin cidence alarms complex pulse generation high resolution baud rate generation frequency shift keying stop watching timing event count accumulation waveform analysis and many more A variety of programmable operating modes and control features allow the Am9513 to be personalized for particular applications as well as dynamically reconfigured under program control The STC includes five general purpose 16 bit counters A variety of internal frequency sources and external pins may be selected as inputs for individual counters with software selectable active high or active low input polarity Both hardware and software gating of each counter is available Three state outputs for each coun
38. nects X1 and X2 in addition to the protection network The resistor is a modestly high value of more than 100kohms Fanout from the driving circuitry into the Am9513 inputs will gen erally be limited by transition time considerations rather than DC current limitations when the loading is dominated by conven tional MOS circuits In an operating environment all inputs should be terminated so they do not float and therefore will not accumulate stray static charges Unused inputs should be tied directly to Ground or VCC as appropriate An input in use will have some type of logic output driving it and termination during operation will not be a problem Where inputs are driven from logic external to the card containing this chip however on board termination should be provided to protect the chip when the board is unplugged and the input would therefore otherwise float A pull up resistor or a simple inverter or gate will suffice Power Supply The Am9513 requires only a single 5V power supply Maximum supply currents are specified in the electrical specification at the high end of the voltage tolerance and the low end of the tempera ture range In addition the current specifications take into ac count the worstcase distribution of processing parameters that may be encountered during the manufacturing life of the product Typical supply current values on the other hand are specified at a nominal 5 0 volts a nominal ambient temperature of 25
39. output logic a 16 bit Load register a 16 bit Hold register and 16 bit Mode register In addition Counter Groups 1 and 2 also include 16 bit Comparators and 16 bit Alarm registers The comparator alarm functions are controlled by the Master Mode register The operation of the Counter Mode registers is the same for all five counters The host CPU has both read and write access to all registers in the Counter Logic Groups through the Data port The counter itself is never directly accessed Load Register The 16 bit read write Load register is used to control the effective length of the general counter Any 16 bit value may be written into the Load register That value can then be transferred into the Counter each time the Terminal Count TC occurs Terminal Count is defined as that period of time when the counter contents 1 8 would have been zero if an external value had not been trans ferred into the counter Thus the terminal count frequency can be the input frequency divided by the value in the Load register In all operating modes either the Load or Hold register will be transfer red into the counter when TC occurs In cases where values are being accumulated in the counter the Load register action can become transparent by filling the Load register with ail zeros Hold Register The 16 bit read write Hold register is dual purpose It can be used in the same way as the Load register thus offering an alternate source for m
40. philosophy of the Am9513 is based on the use of general purpose counters that can be controlled in various ways to produce the functions desired Broadly use of the counters falls into two classic categories a count accumulation and b frequency division In the first case the counter simply accumulates a count of transitions that occur on its input An output that indicates the zero state of the counter would be of only incidental interest The counter value should be available at any time to the associated CPU or it might be compared with some independent value The accumulated count might be modified or the counter input con ditioned by various controls including hardware and software gating functions in any event in these types of applications it is the value of the actual count that is of interest In the case of frequency division on the other hand itis an output waveform that is of interest and the counter input information may be incidental With an output signal that indicates the zero state of the counter selection of the effective length of the counter and the input frequency are controlled to provide the desired output fre quency Additional controls may allow various types of output waveforms to be generated from the base output frequency but the actual counter vaiue will usually not be of direct interest The Am9513 has been designed to handle effectively both modes of operation even intermixed on the same chip In
41. pulse a square wave or a complex duty cycle waveform OUT pulse polarities are individu ally programmable The output circuitry detects the counter state that would have been all bits zero in the absence of a reinitializa tion That information is used to generate the selected waveform type n optional output mode tor Counters 1 and 2 overrides the normal output mode and provides a true OUT signal when the counter contents match the contents of an Alarm register DBO DB7 DB8 DB15 Data Bus Input Output The 16 bidirectional Data Bus lines are used for information exchanges with the host processor HIGH on a Data Bus line corresponds to one and LOW corresponds to zero These lines act as inputs when WR and CS are active and as outputs when RD and CS are active When CS is inactive these pins are placed in a high impedance state After power up or reset the data bus will be configured for 8 bit width and will use only DBO through DB7 DBO is the least sig nificant and DB7 is the most significant bit position The data bus may be reconfigured for 16 bit width by changing a control bit in the Master Mode register This is accomplished by writing an 8 bit command into the low order DB lines while holding the DB13 DB15 lines at a logic high level Thereafter all 16 lines can be used with DBO as the least significant and DB15 as the most significant bit position When operating in the 8 bit data bus environment DB8 DB15 will never be
42. register in parallel When FOUT is gated on or off a transient pulse may be generated on the FOUT signal Disable Prefetch for Write Operations C7 C6 C5 C4 C3 C2 Ci 00 1 1 1 1 1 0 0 1 Coding Description This command disables the prefetch circuitry during Write operations it does not affect Read operations This re duces the write recovery time and allows the user to use block move instructions for initialization of the Am9513 registers Once prefetch is disabled for writing an Enable Prefetch for Write or a Reset command is necessary to re enable the prefetch circuitry for writing Note This command is only available in Am9513 A devices it is an illegal command in the non A Am9513 device Enable Prefetch for Write Operations C7 C6 C5 C4 C3 C2 C1 CO Description This command re enables the prefetch circuitry for Write operations It is used only to terminate the Disable Pre fetch Command Note This command is only available in Am9513 A devices it is an illegal command in the non A 9513 device Coding Master Reset C6 C5 C4 C2 CO Coding Description The Master Reset command duplicates the action of the power on reset circuitry It disarms all counters enters 0000 in the Master Mode Load and Hold registers and enters 0800 hex in the Counter Mode registers Following either a power up or software reset the LOAD com mand should be applied to all the counters to clear any
43. reloading O and counting down to the next MOS 612 Figure 3 5 Conceptual Sequence for Count Down Concatenation 3 3 6 TC will repeated by the order counter until the high order counter has decremented to 1 On the next low order TC the high order counter is driven to TC and reloads The low order counter should reload H rather than 0 and repeat the complete count cycle It can be seen that an important characteristic of the low order counter is that it reloads H once for each high order TC and reloads 0 otherwise This need for the low order counter to selec tively reload 0 or H differs from up concatenation where the low order counter is always reloaded with the same value 0 Figure 3 6 ties the above considerations together in a count repetitively no gating count down concatenation example The low order counter is operated in Mode V in which the gate is used Am9513A Am9513 SOURCE COUNTER 1 GATE INTERNAL TC SOURCE COUNTER 2 Counter 2 Mode Register MOS 613 Figure 3 6 Count Down Concatenation to select either the Load or Hold register as a reload source The high order counter is operated in Mode D with an active high TC output selected in order to properly drive the low order counter s gate In addition the high order counter should be programmed to count on falling edges of the low order counter s internal TC output Figure 3 7 shows timing waveforms generated by this concatena
44. rising source edges and should be programmed for no gating The above requirements can be met by specifying 00 hex in the upper byte of the high order counter s Mode register The low order counter should be programmed to count repetitively The COUNTER 1 INTERNAL TC COUNTER 2 required Mode register settings for Counters 1 and 2 are shown in the figure don t care bits are marked X Note that if the internal TC signal is used to concatenate to the upper counter restrictions are placed on the programming of the low order counter s Output Control field Conversely if external strapping is used to concatenate the counter the low order counter should have an Active High TC output mode selected Up count con catenation may also be used with either level or edge gating For level gating the count source may either be externally gated with external logic or the low order counter may be programmed for level gating as shown in Figure 3 2 In either case the high order counter should be for no gating Recall that while in the TC state the counters will count all source pulses issued to them irrespective of their gating or arming status This can intro duce counting errors when level gating is used in up count con catenation If the gate goes inactive while the low order counter is in TC the low order counter will count the next source edge which drives it out of TC Th
45. sequencing and timing functions The Am9513A supports up or down counting in binary or BCD with hardware or software gating of each counter Its 24 modes of operation are detailed in the Am9513A Data Sheet reprint from AMD included in Appendix C The Am9513A is structured with a series of internal registers that set the mode of operation for each counter These registers are fully described in Appendix C Any combination of the 10 counters in the two Am9513As can be internally cascaded to create a counter of up to 160 bits For example two cascaded counters form a 32 bit counter for longer counting capability Rarely is it practical to cascade more than three counters Cascading is described in Appendix C Chapter 3 of the Am9513A data sheet The timer counters are driven by an on board 5 MHz crystal oscillator On board RC pads let you custom filter each source clock input line for switch debouncing and elimination of unwanted ringing Digital I O Programmable Peripheral Interface The 8255 programmable peripheral interface PPI can be easily configured to solve a wide range of digital real world problems This high performance TTL CMOS compatible chip has 24 parallel programmable digital lines divided into two groups of 12 lines each Group A Port A 8 lines and Port C Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines 3 3 Each group can programmed for one of three modes of operation When
46. signal source or destination device is connected to the appropriate signal pin on the P3 I O connector or on P4 and the low side is connected to any DIGITAL GND Running the 1024DIAG Diagnostics Program Now that your board is ready to use you will want to try it out An easy to use menu driven diagnostics program 1024DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device 2 4 3 HARDWARE DESCRIPTION This chapter describes the features of the TC1024 hardware The major circuits are the timer counters and the digital 1 O lines This chapter also describes the hardware selectable interrupts 3 1 The TC1024 board has two major circuits the timer counters and the digital 1 O lines Figure 3 1 shows the block diagram of the board This chapter describes the hardware which makes up the major circuits and hardware selectable interrupts ADDRESS ADDRESS DECODE INTERRUPT amp CASCADE SELECT 1 FILTER L CIRCUIT 1 VO CONNECTOR BUFFERS AN D PULL UP DOWN RESISTORS IN FER Fig 3 1 TC1024 Block Diagram ON BOARD CONNECTOR Am9513A Timer Counters The Am9513A System Timing Controller contains five general purpose 16 bit timer counters which are capable of performing many different types of counting
47. superior high frequency characteristics An RC network provides a very low cost frequency source but may exhibit large frequency variations over recommended power supply and temperature ranges negating much of the precision available in the Am9513 s counters The RC connection is shown in Figure 2 3b Note that although there is an internal resistor between X1 and X2 because this internal resistance is quite high an external resistor should always be used in the RC operating configurations TO OTHER VO DEVICES ADDRESS DATA BUS TO OTHER OEVICES Figure 2 1 Am9513 5 Interfacing 2 1 1 B2 _ Am25LS158 ADO AD15 ame Ans 52 aw mj TO OTHER VO DEVICES MOS 607 Figure 2 2 AmZ8001 8002 Am9513 Interface 8 CERAMIC NO CONNECTION MOS 185A Note The Am9513A oscillator was changed from the Am9513 The capacitor values in previous designs should be changed to the values shown Figure 2 3 Driving the X1 and X2 Inputs The Am9513 internal oscillator can also be driven by an external signal as shown in Figure 2 3c The Am9513 Electrical Specifica tion should be consulted for the voltage levels required on the X2 input to guarantee proper oscillator operation in this configura tion Most circuits can generate this non TTL level using a pull up resistor and a 74 504 inverter or equivalent In some cases a pull up resistor can be used to increase the high level outpu
48. the Gate XOU DUQQQQU sate eem ED CEL CE TC TOGGLED OUTPUT Peara am OUTPUT TC TOGGLED OUTPUT Figure 1 17v Mode V Waveforms MOS 605 COUNT OUTPUT TC TOGGLED OUTPUT XIII paces Figure 1 17x Mode X Waveforms MODE Hardware Save available in Am9513A only ___ __ x x x Xx Pete Mode X shown Figure 1 17 provides hardware sampling of the counter contents without interrupting the count A Load and Arm command or a Load command followed by an Arm command is required to initialize the counter Once armed a Gate edge starts the counting operation gate edges applied to a disarmed counter are disregarded After application of the Triggering Gate edge the counter will count qualified source edges until the first TC irrespective of the gate level All gate edges applied during the counting sequence will store the current count in the Hold register but they will not interrupt the counting sequence On each TC the counter will be reloaded from the Load register and stopped Subsequent counting requires a new triggering Gate edge counting resumes on the first source edge following the triggering Gate edge Note Mode X is only available in the Am9513 A devices COUNTER MODE CONTROL OPTIONS Each Counter Logic Group includes a 16 b
49. to minimize the read access time to internal Am9513 registers a prefetch circuit is used for all read operations through the Data port Following each read or write operation through the Data port the Data Pointer register is updated to point to the next register to be accessed Immediately following this update the new register data is transferred to a special prefetch latch at the interface pad logic When the user performs a subsequent read of the Data port the data bus drivers are enabled outputting the prefetched data on the bus Since the internal data register is accessed prior to the start of the read operation its access time is transparent to the user In order to keep the prefetched data consistent with the Data Pointer prefetches are also performed 1 7 Counter 1 Hold Reg Counter 1 Mode Reg Counter 1 Load Reg Counter 1 Hold Reg Counter 2 Mode Reg Counter 2 Load Reg Counter 2 Hold Reg Counter 2 Hold Reg Counter 5 Hold Reg HOLD CYCLE Counter 5 Hold Reg Alarm Reg 1 ELEMENT CYCLE Alarm Reg 2 Master Mode Reg Status Reg CONTROL GROUP CYCLE STATUS CYCLE MOS 174A Figure 1 11 Data Pointer Sequencing after each write to the Data port and after execution of the Load Data Pointer command The following rules should be kept in mind regarding Data port Transfers 1 The Data Pointer register should always be reloaded before re
50. to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 25 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set 0 to 4 will be unaffected and we can t say for sure what happens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the TC1024 board functions 47 Initializing the Am9513A The Am9513A has a sophisticated internal architecture which is programmed through a series of internal registers These internal registers are accessed by writing to and reading from only two port locations for each Am9513A on the TC1024 board For Am9513A 1 which contains counters 1 5 the Data Register port is at BA 8 and the Control Register port is at BA 10 For Am9513A 2 which contains counters 6 10 the Data Register port is at BA
51. upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82 55 mA ccu o mn Each of the Control blocks Group and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper 7 4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C
52. y w m w m H W MW M HM Source Edge 0 Counton Rising Edge 1 Count on Falling Edge Gating Control Output Control 000 No Gating 000 Inactive Output Low 001 Active High TCN 1 001 Active High Terminal Count Pulse 010 Active High Level GATE N 1 010 TC Toggled 011 Active High Level GATE N 1 011 Wega 100 Active High Level GATE N 100 Inactive Output High impedance 101 Active Low Level GATE N 101 Active Low Terminal Count Pulse 110 Active High Edge GATE N 110 111 Active Low Edge GATE N 111 illegal Wow m m m Won H Ww ug m ad Note See Figure 1 17 for restrictions on Count Control and Gating Control bit combinations MOS 176 Figure 1 18 Counter Mode Register Bit Assignments TO STATUS REGISTER TC TC TOGGLE SELECT COUNTERS 1 AND 2 ONLY TC CONNECTION TO N 1 COUNTER Figure 1 19 Output Control Logic 1 23 SOURCE a CE IE en N No M C pe E Figure 1 20 Counter Output Waveforms The other output form TC Toggled uses the trailing edge of TC to command or a LOAD or LOAD and ARM command is applied toggle a flip flop to generate an output level instead of a pulse during TC see item 2 above This also means that a counter The toggle output is 1 2 the frequency of TC The TC Toggied that is disarmed or stopped on TC is actually disarmed output will frequently be used to generate variable duty cycle stopped immediately followi
53. 0 the Data Pointer will automatically sequence through one of the cycles shown in Figure 1 11 after reading or writing each register allowing sequential access to internal registers If MM14 1 auto sequencing is disabled and a single internal register can be repetitively accessed without re loading the Data Pointer For convenience bit MM14 can be set or cleared by software command The Pointer is set as follows 1 Using Figures 1 9 and 1 10 select the appropriate Data Pointer Group and Element codes tor the register to be ac cessed Note that two codes are provided for the Hold regis ters to accommodate both the Hold Cycle and Element Cycle autosequencing modes shown in Figure 1 11 If auto sequencing is disabled either Hold code may be used Using the Writing to the Command Register procedure given above write the appropriate Load Data Pointer com mand to the Command register INTERRUPT SERVICE ROUTINE x DISABLE INTERRUPTS SET DATA POINTER TO COUNTER 1 HOLD REG A 019H CMDPRT ENABLE AUTO SEQUENCING CMDPRT CODE TO ACCESS REGISTERS DISABLE AUTO SEQUENCING CMDPRT ENABLE INTERRUPTS AND RETURN O as e w w Kus Ker ese cc Au s 20 T es etes m et gt 8080 RR a AM9513_EXAMPLES MACROB000 28000 Assembler 1 0 1 Page 2 0008 0008 INTSR 9998 0008 000A 000A 000A 000A 000E
54. 091 4196660 L gt H6666066060 055950505050 ah 59 66006000 4c ooooooo 2999000060 00000000 7455 3d 74HCT245 98 0001555505655 85500006 99 20000000 D Q 00000000 EE 99 E 15555555 E 155556555858 bsec 9900990000 Go G u jose A ED 8 00000000 S 000000000 0000000000 0000000000 XCTI CRI e q000000000 56656000000 000000000 Ho00000000 dr 79995 aa ED Pi Fig 1 10 Pull up Pull down Resistor Circuitry 1 10 After the resistor packs are installed you must connect them into the circuit as pull ups or pull downs Locate the three hole pads on the board near the resistor packs They are labeled G for ground on one end and V for 5V on the other end The middle hole is common PA is for Port A PB for Port B PCL is for Port C Lower and PCH is for Port C Upper Figure 1 10 shows a blowup of the pads To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin Figure 1 11 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors CL Ls O PULL DOWN B Fig 1 11 Adding Pull ups and Pull downs to Some Digital I O Lines RC Filters on Source Clock Input Lines On board pads ar
55. 1 lt lt 101 Clear toggle out low for counter N 001 lt lt 101 GT Po ct por seua ST Pe PP Po oats ___ sens pesos made a Ti 1 4 earms neresen Ye 7777777 Cp pepe sate ten rete operas 0 EN EN EHEN 00000 outport cr 0xff02 point to counter 2 mode register table 5 1 outport 9 0 0022 counter 2 mode Put the hex number 1F4 decimal 500 in counter 2 load register outport cr Ox f0a point to counter 2 load register table 5 1 outport dr 0x01f4 counter 2 data 5 5 FOUT 0000 16 0001 divide by 1 0010 divide by 2 0011 divide by 3 0100 divide by 4 0101 divide by 5 0110 divide by 6 0111 divide by 7 1000 divide by 8 1001 divide by 9 1010 divide by 10 FOUT Source 0000 F1 0001 SRC 1 0010 SRC 2 0011 SRC 3 0100 SRC 4 0101 SRC 5 0110 GATE 1 0111 2 1000 3 1001 4 1010 5 1011 divide by 11 1100 divide by 12 1101 divide by 13 1110 divide by 14 1111 divide by 15 1011 F1 1100 22 1101 F3 1110 1111 F5 Compare 2 Enable 0 disabled 1 enabled FOUT Gate 0 FOUT on 1 FOUT off
56. 16 bit operation after initialization Accesses the Am9513A command register for counters 1 5 This chapter explains initialization procedures See the example programs in Chapter 5 and the data sheet included in Appendix C for more information on the operation of the Am9513A 12 Am9513A 2 Data Register Read Write 16 bit operation after initialization Accesses the Am9513A data register for counters 6 10 This chapter explains initialization procedures See the example programs in Chapter 5 and the data sheet included in Appendix C for more information on the operation of the Am9513A BA 14 Am9513A 2 Command Register Read Write 16 bit operation after initialization Accesses the Am9513A command register for counters 6 10 This chapter explains initialization procedures See the example programs in Chapter 5 and the data sheet included in Appendix C for more information on the operation of the Am9513A Programming the TC1024 This section gives you some general information about programming and the TC1024 board Chapter 5 provides some specific programming examples and the Am9513A data sheet in Appendix C provides detailed programming information for all 24 operating modes of the Am9513A These tools will help you as you use the example programs included with the board All of the program descriptions in this section use decimal values unless otherwise speci fied The TC1024 is programmed by writing to and read
57. 24 231256 25 3 145 intel 82C55A WAVEFORNS Continued MODE 2 BIDIRECTIONAL DATA FROM 8060 TO 8265 PERIPHERAL BUS DATA FROM DATA FROM PERIPHERAL TO 8255 8255 TO PERIPHERAL DATA FROM 255 TO 8080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD is permissible INTR IBF MASK STB RD MASK WR i WRITE TIMING READ TIMING DATA BUS Ahi MIGH IMPEDANCE 2 231256 29 A C Testing inputs Are Driven At 2 4V For A Logic 1 And 0 45V For A Logic 0 Timing Measurements Are Made At 2 0V For Logic 1 And 0 8 For A Logic 0 231256 30 Is Set At Various Voltages During Testing To Guarantee The Specification Includes Jig Capacitance 3 146 APPENDIX D WARRANTY D 2 LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES All replaced parts and products become t
58. 259A is arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on The IMR on 8259B is arranged so that bit 0 is for bit 1 is for IRQ9 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determining your IRQ s bit After setting the bit write the new value to I O port 21H IRQO IRQ7 or VO port IRQ8 IRQ15 With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vectors 8 15 are for IRQO IRQ7 and vectors 70H 77H are for IRQ8 IRQ15 If you need to program the source of your interrupts do that next For example if you are using a timer counter to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in before your program started To restore the IMR write the value that was saved when your program started to I O por
59. 3 is in 8 bit bus mode Data Bus pins DB13 DB15 should be held at a logic high whenever CS and WR are both active Command Register The Command register provides direct control over each of the five general counters and controls access through the Data port by allowing the user to update the Data Pointer register The Command Description section of this data sheet explains the detailed operation of each command A summary of all com mands appears in Figure 1 21 Six of the command types are used for direct software control of the counting process Each of these six commands contains a 5 bit S field In a linear select fashion each bit in the S field corresponds to one of the five general counters S1 Counter 1 52 Counter 2 etc When an S bit is a one the specified operation is performed on the counter so designated when an S bit is a zero no operation occurs for the corresponding counter Data Pointer Register The 6 bit Data Pointer register is loaded by issuing the appro priate command through the Control port to the Command regis ter As shown in Figure 1 8 the contents of the Data Pointer register are used to control the Data port multiplexer selecting which internal register is to be accessible through the Data port The Data Pointer consists of a 3 bit Group Pointer a 2 bit Ele ment Pointer and a 1 bit Byte Pointer depicted in Figure 1 9 The Byte Pointer bit indicates which byte of a 16 bit register is to be tran
60. AND TRIGGER LOW ORDER COUNTER VALUES LOW ORDER TC MOS 618 Figure 3 11 Timing Waveforms for Count Down Concatenation with Count Once Feature reload from the Hold register The output of the high order counter can now be set enable counting Level gating be added to count once count down concatenation by using a 3 input AND gate and driving the third input with an external level gate signal Count once count down concatenation with edge gating can be achieved with the circuit shown in Figure 3 12 The flip flop is set by an external synchronous gate edge it is cleared at the end of the count cycle when Counter 2 s TC Toggled output goes low The concatenation examples presented so far have used two counters to create a 32 bit effective count length These config urations can be extrapolated to concatenate 3 or more counters to any desired length Other concatenation variations adventure some users may wish to investigate are those that use the Alarm registers on Counter 1 and 2 to generate unusual count se quences Since these Alarm register configurations usually add much complexity for only a limited increase in functionality they are not discussed in this manual Saving Concatenated Count Values The contents of concatenated counters may be read by issuing a SAVE command to the appropriate counters which will transfer the current counter contents into the counters Hold registers COUNTER 1 INTER
61. APPLICATIONS This chapter steps through an example program to help you understand how the Am9513A registers are programmed The data pointer register and command registers are summarized in tables The master mode and counter mode register bit assignments are also included as well as the frequency scaler ratios 5 1 This chapter provides a more detailed look at an example program using the Am9513A for counting If you are unfamiliar with the Am9513A and how it is programmed walking through this example and the other example programs included on your TC1024 disk may be the best way to understand the many registers and their operation so that you can successfully develop your own programs for your specific applications IMPORTANT Because of the bus release time of the Am9513A AMD recommends you insert a small delay between software accesses to the chip EXAMPLE Counting Program Using Timer Counters 1 2 and 3 This Turbo C program EXAMPLE C on the included disk shows you how to program Am9513A s timer counters 1 2 and 3 to perform a simple counting function In this example counter 1 is used to divide the on board 5 MHz clock by 10 000 The output from counter 1 5 MHz 10 000 500 Hz is used to clock counter 2 Counter 2 is used to divide this 500 Hz clock by 500 The result isa 1 Hz clock which is used to clock counter 3 Counter 3 counts the 1 Hz pulses The count value from counter 3 is displayed on the scr
62. ARAMETERS READ CYCLE Address Stable Before RD Address Hold Time After RD T A Test Address Stable Before WR Address Hold Time After WR cog eeu oz m Ponc E onm T ze ea A en ee E SE Data Hold Time After WA T 30 ns PotsA amp B 30 m 3 142 intel 82 55 s A OTHER TIMINGS tm Peripheral Data Before RD o Peripheral Data After RD R tAK Pulse Width K R NEUEN tes Per Data Before STB High 20 ETA CTE Be DTT ACK 1toOutputFiost 20 250 Er ne 0 to OBF 1 tae SE ee ME EAS STB E __ m tr RD ooNm o nm STB BEC ANE aa ms EA ls 500 e 1toINTR WR 0 to INTR 0 tres Reset Pulse Width NOTE 1 INTR may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 Subsequent Reset pulses may be 500 ns minimum 1 0 1toINTR 1 3 143 BE RS intel 82 WAVEFORMS MODE 0 BASIC INPUT GB A1 tro tor nc 231256 22 MODE 0 BASIC OUTPUT 231256 23 3 144 intel 82 55 WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM PERIPHERAL 231256
63. C Modes during TC This means that TC will never be active for longer G through L With alternating sources and with the TC Tog than one count period and it may in fact be shorter if a STEP gled output selected the duty cycle of the output waveform is 1 24 controlled by the relative Load and Hold values and very fine resolution of duty cycle ratios may be achieved Bit CM7 controls the special gating functions that allow retrigger ing and the selection of Load or Hold sources for counter reload ing The use and definition of CM7 will depend on the status ofthe Gating Control field and bits CM5 and CM6 Hardware Retriggering Whenever hardware retriggering is enabled Modes N and R all active going Gate edges initiate retrigger operations On application of the Gate edge the counter contents will be trans ferred to the Hold register On the first qualified source edge after application of the retriggering Gate edge the Load register con tents will be transferred into the counter Qualified source edges are edges which occur while the counter is gated on and Armed This means that if level gating is used the edge occurring on active going gate transitions will initiate a retrigger Similarly when edge gating is enabled an edge used to start the counter will also initiate a retrigger The first count source edge applied after the Gate edge will not increment decrement the counter but retrigger it If a Load Load
64. CAUTION Remember whenever you close the switches on 52 be sure to remove the Port buffers 010 and 011 from the board Failure to do so may damage the board Mode 2 Operation 52 53 When operating the 8255 in Mode 2 the lines of Port A must be bidirectional and the lines of Port C function as control lines some as outputs and some as inputs When using Mode 2 both the Port A and Port C buffers must be removed and bypassed Figure 1 7 shows the Port A buffers Figure 1 6 shows the Port C buffers and the following steps tell you how to configure the board for Mode 2 operation To remove buffering from Ports A and C Close DIP switches 1 through 8 on 53 Port A Remove 08 from the board Close DIP switches 1 through 8 on 52 Port Remove 010 from the board Remove 011 from the board 4 1024 VO CONNECTOR P4 P3 PIN 10 Fig 1 6 Port C Buffer Circuitry 1024 CONNECTOR 4 BUFFER us Fig 1 7 Port A Buffer Circuitry CAUTION Remember whenever you close the switches on 52 and 53 be sure to remove the buffers 08 U10 and 011 from the board Failure to so may damage the board S4 Interrupt Source Clock Source Select Factory Setting 5 OUT10 EXT6 EXT1 These four single pole double throw switches shown in Figure 1 8 let you select which counter output provides the interrupt source for P5 and P6 and let you select the clock sourc
65. Gate input The Gate inputin Mode S is used only to select the reload source not to start or modulate counting When the Gate is Low the Load register is used when the Gate is High the Hold register is used Note the Low Load High Hold mnemonic convention Once armed the counter will count to TC twice and then disarm itself On each TC the counter will be reloaded from the reload source selected by the Gate Following the second TC an ARM command is required to start a new counting cycle Mode S is shown in Figure 1 17s MODE V Frequency Shift Keying Mode shown Figure 1 17v provides frequency shift keying modulation capability Gate operation in this mode is identical to that in Mode the Gate is Low a LOAD command or a TC induced reload will reload the counter from the Load register If the Gate is High LOADs and reloads will occur from the Hold register The polarity of the Gate only selects the reload source it does not start or modulate counting Once armed the counter will count repetitively to TC On each TC the counter will reload itself from the register determined by the polarity of the Gate Counting will continue in this manner until a DISARM command is issued to the counter Frequency shift keying may be obtained by specify ing a TC Toggled output mode in the Counter Mode register The switching of frequencies is achieved by modulating
66. L COUNTERS 2 3 4 5 MODE LOAD AND HOLD REGISTERS MASTER MODE REGISTER COUNTER 1 ALARM REGISTER COUNTER 2 ALARM REGISTER MOS 501 o 2 a Figure 1 8 Am9513 Register Access Register Register Data Pointer Register Byte Pointer 1 Least Significant Byte Transferred Next 0 Most Significant Byte Transferred Next Element Pointer Group Pointer 00 Mode Register 000 Illegal 01 Load Register Element Cycle Increment 001 Counter Group 1 10 Hold Register 010 Counter Group 2 11 Hold Register Hold Cycle Increment 011 Counter Group 3 100 Counter Group 4 00 Alarm Register 1 101 Counter Group 5 01 Alarm Register 2 Control Cycle Increment 110 10 Master Mode Reg 111 Control Group 11 Status Register No Increment MOS 173A Figure 1 9 Data Pointer Register 1 6 erm acr Mode Load Hold Hold Register Register Register Register Master Mode Register FF17 Alarm 1 Register FF07 Alarm 2 Register FFOF Status Register FF1F Notes 1 All codes are in hex 2 When used with an 8 bit bus only the two low order hex digits should be written to the command port the FF pre fix should be used only for a 16 bit data bus interface Figure 1 10 Load Data Pointer Commands Sequencing is enabled by clearing Master Mode bit 14 MM14 to zero As shown in Figure 1 11 several types of sequencing are available depending on the da
67. MITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE eee
68. Master Mode register bit MM13 should be O and data bus pins DB13 DB15 should be tied high as shown in the diagram Figure 2 2 shows a suggested connection diagram between the Am9513 and an AmZ8001 or AmZ8002 CPU In this diagram the Am9513 appears in both Regular and Special I O space by virtue of the decoding of status lines ST1 ST3 Status line STO should be decoded also if it is necessary to separate the Regular and Special spaces The 28136 is a latched decoder which stores the address information on the rising edge of AS providing the Am9513 with a stable CS for the duration of the transfer The Am25LS158 multiplexer generates RD and WR from the CPU s DS and lines For maximum data bandwidth between the CPU and the Am9513 Master Mode re gister bit MM13 should be set to 1 to configure the Am9513 for a 16 bit data bus width This can be accomplished by writing command opcode FFEF to Am9513 following each reset and power up CLOCK GENERATION An internal oscillator is provided on the Am9513 for generation of timing frequencies to drive the source inputs for the five counters and the source for the FOUT pin Note that a clock signal is not required for reads and writes to the Am9513 In applications which 28001 and 28002 are trademarks of Zilog Inc do not use the internal oscillator the X2 input should be tied either High or Low to prevent accumulation of static charge The X1 output is driven by an i
69. NAL TC 15 0 15 0 Counter 1 Mode Register Counter 2 Mode Register Figure 3 12 Count Down Concatenation with Edge Gating and Count Once Feature Since in count down concatenation the Hold register is used to generate the count sequence in many such applications it may not be feasible to save the low order counter Because the count ripples between concatenated counters the possibility exists that a SAVE command will be issued after the low order counter increments decrements but before the carry borrow ripples through to the high order counter resulting in an incorrect value being saved in the high order counter s Hold register The user can protect against this by examining the contents of the low order counter s Hold register immediately after issuing the SAVE command If the Hold register is equal to the value that would have been expected immediately following generation of a carry borrow signal this indicates that the high order value saved is suspect A new SAVE command should therefore be issued to the high order counter to save a correct count By the time the low order Hold register contents are read and tested and a new SAVE command is issued the high order counter s contents will be stable The Time of Day chapter discusses these consider ations with respect to Time of Day accumulation and includes representative software listing intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE m Comp
70. NS A 1 TC1024 Characteristics Typical E 25 C Interface AT bus compatible Switch selectable base address mapped Jumper selectable interrupts iu c BE CMOS 82C55 Optional NMOS 8255 N mber of lines Eee eee ergo ua een 24 Logic compati DV version seen REFERS TTL CMOS Configurable with optional I O pull up pull down resistors High level output voltage 4 2V min Low level output voltage 0 45V max High level input voltage eese nnn 2 2V min 5 5V max Low level input voltage 0 3V min 0 8V max High level output current CMOS buffer 12 mA max TTL buffer 16 mA max Low level output current CMOS buffer 24 mA max TTL buffer 64 mA max Input load CUITONE tenen tnn enne 10 pA Input capacitance GOIN ae een da T 10 pF Output capacitance C OUT GFEIMHZ 22a nn 20 pF Timer Counter Lecce eec eee een essen rear aan tm na saa ansa sanos asc asa sane ua Am9513A Ten 16 bit timer counters 2 Am9513A chips Binary or BCD up or down counting Programmable operating modes essen enne 24 Counter input SOUICE External clock 6 9 MHz max on board 5 MHz clock external g
71. Numbers Part Number P4 Connector 7 PC7 PA6 PC6 PAS 5 4 2 2 1 1 PCO 12 VOLTS 45 VOLTS 12 VOLTS DIGITAL GND P4 Mating Connector Part Numbers Manufacturer Part Number B 4 APPENDIX COMPONENT DATA SHEETS AMD Am9513A System Timing Controller Data Sheet Reprint Chapter 1 The Am9513A Am9513 INTRODUCTION Manipulation and coordination of timing parameters and event sequences are universal system attributes At the most funda mental levels of control time sequences are intimately embed ded in the essential hardware and interface concepts of all pro cessors the necessary flows of step by step procedures are inherent in the execution of even the most basic programs At the interface level both internal and external hardware coordination usually require several types of timing oriented exchanges In general control of system and sub system processes will often involve sophisticated levels ot counting sequencing and timing manipulations The specific mix of such activities will of course be application dependent yet counting timing concepts are at least fundamentally involved in all system operations from the simplest sequencing of a hardware interface to the complex interaction of high level processes Time related activities fall into
72. O DB7 The user is not required to drive CS or C D High between successive reads or writes although this is permissible As described in the Setting the Data Pointer section Am9513 service routines should disable interrupts during Data port regis ter accesses if the service routine could be interrupted by another service routine requiring access to the Data port registers Figure 2 10 shows sample programs for writing a 16 bit value to a Data port register The Am8080A 8085A code loads the register by making two byte transfers low byte first to the Am9513 Data port A 16 bit data bus interface is assumed for the AmZ8002 coding example accordingly a single word transfer can be used to load a register This code can be sub stituted into the sample interrupt service routines in Figure 2 7 in the place marked Code to Access Registers CODE TO WRITE TO DATA PORT REG DATAPRT DATAPRT a 8080 Code ee AM9513_EXAMPLES 002E 002E 002E 002 0032 0932 9032 9932 3826 0010 MNNNONNN 2 MACROB000 AmZ8000 Assembler 1 0 1 Page 5 CODE TO WRITE TO DATA PRT REG DATAPRT R2 b AmZ8000 Code Figure 2 10 Writing Through the Data Port 2 8 Chapter 3 Concatenating Counters CONCATENATING COUNTERS The Am9513 counters may be concatenated in a number of different ways These may be conceptually broken down into count up and count down concatenation Count up concatenation will ty
73. RECTIONAL vo rhv CONTROL 7 231256 5 Figure 5 Basic Mode Definitions and Bus Interface 3 128 CONTROL WORD GROUPB PORT C LOWER 1 INPUT 0 OUTPUT PORTS 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE O 1 MODE 1 PORT C UPPER NPUT MODE SELECTION 00 MODEO 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical 1 approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port is being used as status control for Port B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports intel 82C55A Interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request in
74. TC Toggled output mode in the Counter Mode register The initial counter contents control the delay from the ARM command until the output pulse starts The Hold register contents control the pulse duration Mode G is shown in Figure 1 179 MOS 593 Figure 1 17f Mode F Waveforms OOOO E 5 EM he OUTPUT M n TC TOGGLED X OUTPUT M WR Jara COMMAND MOS 594 Figure 1 179 Mode G Waveforms MODE H Software Triggered Delayed Pulse One Shot with Hardware Gating Mode shown in Figure 1 17 is identical to Mode exceptthat the Gate input is used to qualify which source edges are to be counted The counter must be armed for counting to occur Once armed the counter will count source edges that occur while the Gate is active and disregard those source edges that occur while the Gate is inactive This permits the Gate to turn the count process on and off As with Mode G the counter will be reloaded from the Hold register on the first TC and reloaded from the Load register and disarmed on the second TC This mode allows the Gate to contro the extension of both the initial output delay time and the pulse width MODE Hardware Triggered Delayed Pulse Strobe IA Mode shown in Figure 1 17i is identical to except that coun
75. TIATION A OADH 1344 CMIPRT CTRS a 8080 Code 8 9513 EXAMPLES 9000 0000 0000 0000 0000 0000 9000 0000 0000 0000 9000 0000 9000 0000 9004 0008 0008 0008 2 2 2 2 CONST 2 2 2 LD OUT 2 2102 FFAD 3B26 0012 x MACRO8000 AmZ8000 Assembler 1 0 1 1 PROGRAM AM9513_EXAMPLES ORIGIN AM9S513 PORT ADDRESSES CMDPRT 12H DATAPRT 10H dei AM9S13 COMMAND INITIATION R2 0FFADH ZSAVE CTRS 1 3 amp 4 CMDPRT R2 b AmZ8000 Code Figure 2 6 Command Initiation Software Establish a High on the C D input Establish a Low on the CS input Establish a Low on the WR input Sometime after the minimum WAR low pulse duration has been achieved drive WR high taking care the CS C D and data setup times are met see Timing Diagram After meeting the required CS C D and data hold times these signals can be changed see Timing Diagram new read or write operation to the Am9513 should be performed until the write recovery time is met see Timing Dia gram in Electrical Specification Setting the Data Pointer Register The Data Pointer register selects which internal Am9513 register is to be accessed through the Data port Setting the Data Pointer register automatically sets the Byte Pointer to 1 indicating a least significant byte is expected for 8 bit data bus interfacing If Master Mode register bit MM14
76. ____ a een BN Vor Output Low Output Low Voltage 2 5 mA Output High Voltage 2 5 mA Vcc 0 4 100 pA Input Leakage Current Vin to OV Note 1 Output Float Leakage Current 10 pA Vin to OV Note 2 IDAR Darlington Drive Current 12 5 Note 4 mA Ports A B Rext 5000 Port Hold Low Leakage Current 50 300 pA Vout 1 0V Port only Vext 1 7V Port Hold High Leakage Current pA Vour 3 0V Ports A B C Port Hold Low Overdrive Current 30o pa Vout 0 8V Port Hold High Overdrive Current 30 pA Vour 30V Voc Supply Current _ to motes ____ lt z lt lt Voc 5 5V Vin Voc or GND Port Conditions If P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High NOTES TU 1 Pins Ay CS WA RD Reset Data Bus Ports 0 n 3 Outputs open 4 Limit output current to 4 0 mA 3 141 intel 82C55A CAPACITANCE TA 25 C GND OV a input Capacitance NOTE Test Conditions Unmeasured pins returned to GND fo 1 MHz Capacitance 5 Sampled not 100 tested A C CHARACTERISTICS Ta 0 to 70 C 5V 10 GND OV Ta 40 C to 85 C for Extended Temperature BUS P
77. ading from the Data port if command other than Load Data Pointer was issued to the Am9513 following the last Data port read or write The Data Pointer does not have to be loaded again if the first Data port transaction after a command entry is a write since the Data port write will automatically cause a new prefetch to occur 2 Operating modes N O Q R and X allow the user to save the counter contents in the Hold register by applying an active going gate edge If the Data Pointer register had been pointing to the Hold register in question the prefetched value will not correspond to the new value saved in the Hold register To avoid reading an incorrect value a new Load Data Pointer command should be issued before attempting to read the saved data A Data port write to another register will also initiate a prefetch subsequent reads will access the recently saved Hold register data Many systems will use the saving gate edge to interrupt the host CPU In systems such as this the interrupt service routine should issue a Load Data Pointer command prior to reading the saved data Status Register The 8 bit Status register indicates the state of the Byte Pointer bit in the Data Pointer register and the state of the OUT signal for each of the general counters See Figures 1 12 and 1 19 The OUT signals reported are those internal to the chip after the polarity select logic and just before the 3 state interfac
78. and Arm or Step Command occur between the retriggering Gate edge and the first qualified source edge it will be interpreted as a source edge and transfer the Load register contents into the counter Thereafter the counter will count all qualified source edges When some form of Gating is specified CM7 controls hardware retriggering In this case when CM7 0 hardware retriggering does not occur when CM7 1 the counter is retriggered any time an active going Gate edge occurs Retriggering causes the counter value to be saved in the Hold register and the Load register contents to be transferred into the counter When No Gating is specified the definition of CM7 changes In this case when 7 0 the Gate input has no effect on the counting when CM7 1 the Gate input specifies the source selecting either the Load or Hold register used to reload the counter when TC occurs Figure 1 16 shows the various available contro combinations for these interrelated bits Count Source Selection Counter Mode bits CM8 through CM12 specify the source used as input to the counter and the active edge that is counted Bit CM12 controls the polarity for all the sources logic zero counts rising edges and logic one counts falling edges Bits CM8 through CM11 select 1 of 16 counting sources to route to the counter input Five of the available inputs are internal frequencies derived from the internal oscillator see Figure 1 15 for frequency assignment
79. and drives the counter to TC in these modes the reload source for the next TC will be from the opposite reload location in other words the LOAD generated TC will cause the reload sources to alternate just as a TC generated by a source edge would Note that if a second LOAD command is issued during the LOAD generated TC or during any other TC for that matter the second LOAD command will terminate the TC and cause a reload from the source designated for use with the next TC The second LOAD will not alter the reload source for the next TC since the second LOAD does not generate a TC reload sources alternate on 5 only not on LOAD commands Load and Arm Counters C7 C6 C5 C4 C3 C2 CO 0 1 1 S5 S4 S3 S2 S1 Coding Description Any combination of counters as specified in the S field will be first loaded and then armed This command is equivalent to issuing a LOAD command and then ARM command A LOAD and ARM command which drives a counter to TC gen erates the same sequence of operations as execution of a LOAD command and then an ARM command In modes which disarm on TC Modes A C and N O and Modes G I and S if the current TC is the second in the cycle the ARM part of the LOAD and ARM command will re enable counting for another cycle In modes which alternate reload sources Modes G L the ARMing operating will cause the next TC to reload from the HOLD regis ter irrespective of which reload source the current TC use
80. ate can be mod ulated throughout the count cycle to stop and start the counter ee ARM COMMAND care COUNT TC OUTPUT IA TC TOGGLED OUTPUT MOS 590 Figure 1 17 Mode Waveforms MODE 0 Rate Generator with No Hardware Gating 1 1 ee ee Mode D shown in Figure 1 17d is typically used in frequency generation applications In this mode the Gate input does not affect counter operation Once armed the counter will count to TC repetitively On each TC the counter will reload itself from the Load register hence the Load register value determines the time between TCs A square wave rate generator may be obtained by specifying the TC Toggled output mode in the Counter Mode register MODE E Rate Generator with Level Gating free Bel ee Mode E shown in Figure 1 17e is identical to Mode D exceptthe counter will only count those source edges which occur while the Gate input is active This feature allows the counting process to be enabled and disabled under hardware control A square wave rate generator may be obtained by specifying the TC Toggled output mode m JA N NININE NI COUNT TC OUTPUT MN x NP GE NER TC TOGGLED OUTPUT Figure 1 17d Mode D Waveforms MOS 591 COUNT TC OUTPUT TC TOGGLED OUTPUT e Ace MOS 592 Figure 1 17e Mode E Waveforms 1 14
81. ate input or adjacent counter output Counter nennen Available externally used as PC interrupts or internally cascaded to adjacent counter Counter External input counter output or software control Miscellaneous Inputs Outputs 5 volts 12 volts digital ground bus sourced External interrupt input Frequency output Current Requirements 350 mA 5 volts Connectors P3 50 pin right angle shrouded box header P4 20 box connector Environmental Operating temperature 010 70 C Storage temperature 40 to 85 C Humidity 0 to 90 non condensing Size 3 875 H x 6 370 99mm x 162mm APPENDIX P3 AND P4 CONNECTOR PIN ASSIGNMENTS 1 P3 Connector 5 1 1 2 5 GATE1 3 2 6 outi 5 6 outs src2 7 SRC7 GATE2 9 GATE7 A ouT7 13 SRC8 GATE3 49 outs 47 outs SRC4 SRC9 GATE4 62 GATES 23 OUT9 25 SRC10 GATES 7 GATE10 OUTS OUT10 EXTINT 61 62 DIGITAL GND rour 63 DIGITAL GND 8969 ec Pci 67 PB7 PB6 3 02 143 2 2909 PBo 12 VOLTS 6268 5 VOLTS 12 VOLTS 29 60 DIGITAL GND Mating Connector Part
82. ate with all other addressable internal locations The Data Pointer register controls the Data port addressing Among the registers accessible through the Data port are the Master Mode register and five Counter Mode registers one for each counter The Master Mode register controls the pro grammable options that are not controlled by the Counter Mode registers Each of the five general purpose counters is 16 bits long and is independently controlled by its Counter Mode register Through this register a user can software select one of 16 sources as the counter input a variety of gating and repetition modes up or down counting in binary or BCD and active high or active low input and output polarities Associated with each counter are a Load register and a Hold register both accessible through the Data port The Load register is used to automatically reload the counter to any predefined value thus controlling the effective count period The Hold regis ter is used to save count values without disturbing the count process permitting the host processor to read intermediate counts In addition the Hold register may be used as a second Load register to generate a number of complex output waveforms All five counters have the same basic control logic and control registers Counters 1 and 2 have additional Alarm registers and comparators associated with them plus the extra logic necessary for operating in a 24 hour time of day mode F
83. atible with all Intel and Most m Control Word Read Back Capability Other Micropresssore Direct Bit Set Reset Capability m High Speed Zero Wait State Operation with 8 MHz 8086 88 and oe Capability on all 1 0 80186 188 Available in 40 Pin DIP and 44 Pin PLCC Available in EXPRESS m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 O device which is designed for use with all Intel and most other microprocessors provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255 5 In MODE 0 each group of 12 I O pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82 55 is fabricated on Intel s advanced CHMOS technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages m 24 Programmable 1 0 Pins W OWECTIONAL DATA BUS 231256 1 Figure 1 82C55A Block Diagram
84. d This command should not be used during asynchronous operations Disarm Counters C7 C amp S C4 C3 C2 C1 1 1 0 55 54 53 52 851 Description Any combination of counters as specified by the 5 field will be disabled from counting disarmed counter will cease all counting independent of other control conditions The only exception to this is that a counter in the TC state will always count once in order to leave TC before DISARMing This count may be generated by a source edge by a LOAD or LOAD and ARM command the LOAD and ARM command will negate the DISARM command or by a STEP command A disarmed counter may be updated using the LOAD command and may be read using the SAVE command A count process may be re sumed using an ARM command See the ARM command de scription for further details Save Counters C7 C6 C5 C4 C2 C1 Description Any combination of counters as specified by the 5 field will have their contents transferred into their associated Hold register The transfer takes place without interfering with any Coding Coding 1 27 counting that may be underway This command will overwrite any previous Hold register contents The SAVE command is de signed to allow an accumulated count to be preserved so that it can be read by the host CPU at some later time Disarm and Save Counters C7 C6 C5 C4 C3 C2 1 0 0 S5 54 3 52 Coding 51 Description Any combination of coun
85. d This step must be executed every time you start up reset or reboot your computer The 8255 is initialized by writing the appropriate control word to port BA 6 The contents of your control word will vary depending on how you want to configure your VO lines Use the control word description in the previous 1 O map section to help you program the right value In the example below a decimal value of 128 sets up the 8255 so that all I O lines are Mode 0 outputs Remember that if you want to use Mode 1 or Mode 2 operation you must remove the Port A and or Port C buffers from the board and close the buffer bypass switches Chapter 1 explains how to do this in paragraphs covering 52 and 53 1 0 0 0 0 0 0 0 pr os os oa os pz ps no Digital VO Operations Once the 8255 is initialized you can use the digital 1 O lines to control or monitor external devices 4 8 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time f
86. d into the counter Counting will resume on the second source edge after a retrigger MODE Rate Generator with Synchronization Event Counter with Auto Read Reset x x x Mode Q shown in Figure 1 17q provides a rate generator with synchronization or an event counter with auto read reset The counter must first be issued an ARM command before counting can occur Once armed the counter will count all source edges which occur while the Gate is active and disregard those edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off After the issuance of an ARM command and the application of an active Gate the counter will Count to TC repetitively On each TC the counter will reload itself from the Load register The counter may be retriggered at any time by presenting an active going Gate edge to the Gate input The retriggering Gate edge will transfer the contents of the counter into the Hold register The first qualified source edge after the retriggering Gate edge will transfer the contents of the Load register into the Counter Counting will resume on the second qualified source edge after the retriggering gate edge Qualified source edges are active going edges which occur while the Gate is active GATE Sole GND CON TC OUTPUT OUTPUT MODE R Retriggerable One Shot amp e Lac pgs pex poe Mode R shown
87. d of 16 see Figure 1 15 FREQUENCY SCALER BCD Scaling MM15 1 Frequency Fi OSC F2 Fi 10 F3 F1 100 F4 F1 1 000 F5 F1 10 000 Figure 1 15 Frequency Scaler Ratios 1 10 lolo fof o fo folio Reload Source OME pex s I9 w aper por A Repetition OM fof ol ej MEREN Con _________ 00 LEVEL EDGE LeveL EDGE Lever bae Lever eae Goure to TG oreo wer asam x x x Court 1 TC tice thon lA O ER Count to TC repeatediy without disarming pur cs Gate input does counter input as el Count only during active gate level Start count on active gate edge and stop count on next TC Start count on active gate edge and stop count on second TC No hardware retriggering x x x x BE Reload counter from Load Register on TC px x x x x x OT T Reload counter on each TC alternating reload M X EXE NAS x X source between Load and Hold Registers Transfer Load Register into counter on each TC that gate is LOW transfer Hold Register into counter on each TC that gate is HIGH On active gate edge transfer counter into Hold Register and then reload counter from Load Register comem Jm gt 51 X
88. de AM9513 EXAMPLES 0026 0026 0026 0026 002A 002A 002A 3804 0012 MACRO8000 78000 Assembler EJECT 1 0 1 Page 3 CODE TO READ FROM STATUS REGISTER RO CMIIPRT b AmZ8000 Code Figure 2 8 Reading the Status Register 2 6 Reading From the Data Port The registers which can be read from the Data port are the Load Hold and Counter Mode registers for Counters 1 through 5 the Alarm registers for Counters 1 and 2 the Master Mode register and the Status register The Status register can also be read from the Control port Reading the Status register with a 16 bit data bus interface will return undefined information on DB8 DB15 The procedure for reading these registers is as follows 1 Priorto performing the actual read operation the Data Pointer should be set to point to the register to be read as outlined in the Setting the Data Pointer section of this document In cases where auto sequencing of the Data Pointer is used the Pointer has to be set only once to the first register in the sequence When auto sequencing is disabled repetitive ac cesses can be made to the same register without reloading the Data Pointer each time Special care must be taken to reset the Data Pointer after issuing a command other than Load Data Pointer to the Am9513 or when operating a counter in modes N O Q or R See the Prefetch Circuit sec
89. driven active by the Am9513 DB8 through DB12 may optionally be used as additional Gate inputs see Figure 1 6 If unused they should be held high When pulled low a GATENA signal will disable the action of the corresponding counter N gating DB13 DB15 should be held high in 8 bit bus mode whenever CS and WR are simultaneously active CS Chip Select Input The active low Chip Select input enables Read and Write opera tions on the data bus When Chip Select is high the Read and Write inputs are ignored The first Chip Select signal after power up is used to clear the power on reset circuitry If Chip Selectis tied to ground permanently the power on reset circuitry may not function such a configuration the software reset command must be issued following power up to reset the Am9513 RD Read Input The active low Read signal is conditioned by Chip Select and indicates that internal information is to be transferred to the data bus The source will be determined by the port being addressed and for Data Port reads by the contents of the Data Pointer register WR and RD should be mutually exclusive WR Write input The active low Write signal is conditioned by Chip Select and indicates that data bus information is to be transferred to an internal location The destination will be determined by the port being addressed and for Data Port writes by the contents of the Data Pointer register WR and RD should be mutually exclusive
90. e edges only not to inactive going edges Similarly the phrase gate edges refers only to active going gate edges Also again to avoid verbosity and euphuism the descriptions of some modes state that a counter is stopped or disarmed on a TC inhibiting further counting As is fully explained in the TC section of this document for these modes the counter is actually stopped or disarmed following the active going source edge which drives the counter out of TC In other words since a counter in the TC state always counts irrespective of its gating or arming status the stopping or disarming of the count sequence is delayed until TC is terminated MODE A Software Triggered Strobe with No Hardware Gating KNEE EE REGE EN Mode shown Figure 1 17 is of the simplest operating modes The counter will be available for counting source edges when it is issued an ARM command On each TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting Counting will resume when a new ARM command is issued MODE B Software Triggered Strobe with Level Gating Mode B shown in Figure 1 17b is identical to Mode A except that Source edges are counted only when the assigned Gate is active The counter must be armed before counting can occur Once armed the counter will count all source edges which occur while the Gate is active and disregard t
91. e 2 4 Data Bus Transfers AD hex which saves the contents of Counters 1 3 and 4 in their associated Hold registers In both the Am8080A 8085A and AmZ8002 coding examples the command is loaded into an internal CPU register and output to the appropriate port Note that in the AmZ8002 case since a 16 bit data bus inter face is assumed the upper byte of data output to the Command port must be FF hex The procedure for executing a command is as follows 1 Establish the appropriate command on the DBO DB7 lines Figure 1 21 lists the command codes When using the Am9513 in 16 bit mode data bus lines DB8 DB15 should be set high during the write operation In 8 bit data bus mode DB13 DB15 should be set high during the write operation THIS IS A SAMPLE INITIALIZATION SEQUENCE FOR THE AM9S13 COUNTER TIMER 12 10 R1 amp FFFF CMDPRT R1 ASEND RESET Ril FF SF 3 1 ADAD ALL COUNTERS RistFFEF CHDFRT R13 ACOMMAND 16 BIT MODE Riy FF175 CHDFRT R15 TO MASTER MODE REG R1 2CEF DATAFPRT R1 AMASTER MODE SETTING 1 012 1 TO CNTR 1 MODE REG Figure 2 5 Am9513 Initialization 2 3 2 CMDPRT DATAPRT cc Wes we TE ws e T les 9 c cc aH gt m 100H AM9S 13 PORT ADDRESSES 012H 010H AM9513 COMMAND INI
92. e Triggered Strobe with Level Gating and Hardware Retriggering Mode N shown in Figure 1 17n provides software triggered strobe with level gating that is also hardware retriggerable The counter must first be issued an ARM command before counting can occur Once armed the counter will count all source edges which occur while the gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off After the issuance of an ARM command and the application of an active Gate the counter will count to TC Upon reaching TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting Counting will resume upon the issuance of a new ARM command All active going Gate edges issued to an armed counter will cause a retrigger operation Upon application of the Gate edge the counter contents will be saved in the Hold register On the first qualified source edge after application of the retrig gering gate edge the contents ofthe Load register will be transfer red into the counter Counting will resume on the second qualified source edge after the retriggering Gate edge Qualified source edges are active going edges which occur while the Gate is active care COUNT em CES EI CI CE ED TC TOGGLED OUTPUT MOS 599 F
93. e buffer circuitry Bits SR6 and SR7 may be 0 or 1 The Status register OUT bit reflects an active high or active low TC output or a TC Toggled output as programmed in the Output Control Field of the Counter Mode register Thatis it reflects the exact state of the OUT pin When the Low Impedance to Ground Output option CM2 CMO 000 is selected the Status register will reflect an active high TC Output When a High Impedance Output option 2 100 is selected the Status register will reflect an active low TC output For Counters 1 and 2 the OUT pin will reflect the comparator output ifthe comparators are enabled The Status register bit and OUT pin are active high CM2 0 and active low if CM2 1 When the High Impedance option is selected and the comparator is enabled the status register bit will reflect an active high com parator output When the Low Impedance to Ground option is selected andthe comparator is enabled the status register bit will an active low comparator output The Status register is normally accessed by reading the Control port see Figure 1 8 but may also be read via the Data port as part of the Control Group BYTE POINTER OUT 1 OUT 3 MOS 587 Figure 1 12 Status Register Bit Assignments DATA PORT REGISTERS Counter Logic Groups As shown in Figures 1 2 and 1 3 each of the five Counter Logic Groups consists of a 16 bit general counter with associated con trol and
94. e count Gating Control 010 TC toggled 000 no gating 011 not used 001 active high TCN 1 100 inactive output high impedance 010 active high level gate N 1 101 active low terminal pulse count 011 active high level gate N 1 110 not used 100 active high level gate N 111 not used 101 active low level gate N 110 active high edge gate N 111 active low edge gate N Fig 5 2 Counter Mode Register Bit Assignments outport cr Oxff03 point to counter 3 mode register table 5 1 outport dr 0x002a counter 3 mode Put the hex number 0000 in counter 3 load register outport cr 0xff0b point to counter 3 load register table 5 1 outport dr 0x0000 counter 3 data outport cr 0x0067 load and arm counters 1 2 amp 3 table 5 2 5 7 FREQUENCY SCALER BCD Scaling MM15 1 Binary Scaling MM15 0 With On board With On board Frequency 5 MHz Clock 5 MHz Clock F1 Lm F1 10 000 500 Hz F1 65 536 76 3 2 Fig 5 3 Frequency Scaler Ratio The main program for taking a total of 25 readings is 3 0 clrscr while j 25 outport cr 0x00a4 save counter 3 in hold register table 5 2 outport cr Oxff13 point to counter 3 hold register table 5 1 result inport dr read counter 3 data printf 5d result print result delay 1000 1 5 8 APPENDIX TC1024 SPECIFICATIO
95. e counter will then stop counting until the gate goes active again This effectively introduces a 1 count error into the accumulated count The maximum error that can be introduced is one extra count each time the gate is applied This worst case error will occur only if the gate is always applied when the low order counter is in the TC state For many applications which use the gate infrequently this small potential error is of no significance Applications sensitive to small count errors or appli cations with many gate on gate off cycles should use external gating logic to inhibit source pulses Edge gating functions can also be used in up count concatena tion An edge gating circuit with concatenated counters should function in a logically identical manner to a single edge gated counter In other words after an edge is applied to the concate nated counters they should count until both reach TC A new edge should be required to repeat the cycle Direct concate nation of two counters as was done for level gating up count SOURCE SOURCE COUNTER 1 OUT GATE GATE INTERNAL SOURCE COUNTER 2 15 ec o T Counter 1 Mode Register Counter 2 Mode Register Figure 3 2 Count Up Concatenation with Level Gating E concatenation will not work In such an arrangement the low order counter once triggered will count to TC once and then stop awaiting a new gate edge This is unsatisfactory since we want the low order co
96. e for counters 1 and 6 S4 1 This switch provides the output of counter 5 or the output of counter 2 as the available interrupt source at P5 The factory setting is OUTS Figure 1 9 shows how this switch is connected S4 2 This switch provides the output of counter 10 or the output of counter 7 as the available interrupt source at P6 The factory setting is OUT10 Figure 1 9 shows how this switch is connected S4 3 This switch controls the clock source for counter 6 The source can be provided externally from the P3 connector or it can be provided from the output of counter 5 cascading counter 6 to counter 5 The factory setting is external EXT6 SRC 6 at the connector Figure 1 9 shows how this switch is connected S4 4 This switch controls the clock source for counter 1 The source can be provided externally from the P3 connector or it can be provided from the output of counter 10 looping counter 10 s output back around to counter 1 The factory setting is external EXT1 SRC 1 at the VO connector Figure 1 9 shows how this switch is connected 54 OUT2 OUT7 OUT5 OUT10 1 2 3 4 OUT5 OUT10 EXT6 EXT1 Fig 1 8 Interrupt Source Clock Source Select SPDT Switch S4 1 8 1024 CONNECTOR 9513 1 U2 54 4 COUNTER I a N C PIN 1 1 PIN 3 AGATE 1 4 21 4 GATE 4 PIN 23 OUT 4 COUNTER PIN 25 sro 5 5 PIN 27 1 5
97. e modes will reload from the Hold register on the first TC and alternate reload sources thereafter reload from the Load register on the second TC the Hold register on the third etc Load Counters except when XXX 111 001 000 Coding C7 C6 C5 C4 C2 Ci Figure 1 22 Am9513 Unused Command Codes 1 0 55 54 53 52 SI Description Any combination of counters as specified in the 5 field will be loaded with previously entered values The source of information for each counter will be either the associated Load 7 2 Coding S register the associated Hold register as determined by the 0 1 55 S4 53 S2 51 operating configuration in the Mode register The Load Hold contents are not changed This command will cause a transfer independent of any current operating configuration for the Arm Counters Description Any combination of counters as specified by the S field will be enabled for counting A counter must be armed counter It will often be used as a software retrigger or as counter before counting can commence Once armed the counting pro initialization prior to active hardware gating cess may be further enabled or disabled using the hardware gating facilities This command can only arm or do nothing for a If a LOAD or LOAD and ARM command is executed during the given counter a zero in the 5 field does not disarm the counter cycle preceding TC the count
98. e provided to add custom filtering on each of the 10 source clock input lines These RC pads located in the upper right area of the board let you build a switch debouncing circuit or a circuit to eliminate uwanted ringing on the clock input Simply calculate the values you want to use to achieve the desired results and solder the components onto the board Figure 1 12 shows a switch debouncing circuit for the TC1024 source clock inputs Table 1 3 lists the resistor capacitor pairs for each source clock input line FROM 1000 TO AM9513A CONNECTOR SOURCE INPUT 1902 F 1 2nRC 1 2r 100 10uF F 159 Hz Fig 1 12 Typical Switch Debouncing Filter Circuit Table 1 3 Source Clock RC Filters Source Clock Resistor Capacitor Number Number Number C21 C22 CHAPTER 2 BOARD INSTALLATION The TC1024 is easy to install in your PC AT or compatible computer This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 1024DIAG board diagnostics program included on your example software disk to verify that your board is working 2 1 Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the board at the edges and do not touch the components or connectors Before installing t
99. e the duty cycle of the output waveform lt can affect both the high and low portions of the output waveform 22 un Figure 1 17j Mode J Waveforms MOS 597 sour V V V V V VDDD PPD eMC TN TC OUTPUT TC TOGGLED OUTPUT a rums A E PETER MOS 598 Figure 1 17k Mode K Waveforms 1 17 MODEL Hardware Triggered Delayed Pulse One Shot x x x x x px Tx L shown Figure 1 171 is similar Mode J except that counting will not begin until a Gate edge is applied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded The counter will start counting source edges after the triggering Gate edge and counting will proceed until the second TC Note that after application of a triggering Gate edge the Gate input will be disregarded tor the remainder of the count cycle This differs from Mode K where the gate can be modulated throughout the count cycle to stop and start the counter On the first TC after application of the triggering Gate edge the counter will be reloaded from the Hold register On the second TC the counter will be reloaded from the Load register and counting will stop until a new gate edge is issued to the counter Note that unlike Mode K new Gate edges are required after every second TC to continue counting MODE N Softwar
100. ector shown in Figure 1 3 lets you connect the output of counter 7 or 10 whichever is selected on S4 2 to any of 11 interrupt channels IRQ9 highest priority channel through IRQ12 IRQ14 IRQ15 and then back to IRQ3 through IRQ7 lowest priority Chapter 4 explains interrupt channel prioritization in detail To activate a channel you must install a jumper across the desired IRQ channel Figure 1 3a shows the factory setting Figure 1 3b shows the interrupt source connected to IRQ9 If you use multiple interrupts make sure each source is assigned to a different IRQ channel Fig 1 3a y e Factory Setting a P6 IRQ 15 14 121110 97 6 5 4 3 Fig 1 3b Interrupt Source Connected to IRQ9 2 P6 IRQ 15 14 121110 97 6 5 4 3 Fig 1 3 Counter OUT 7 10 Interrupt Channel Select Jumper P6 P7 Interrupt Source Channel Select Factory Setting No Connection This wire wrap header connector shown in Figure 1 4 lets you connect any of 11 interrupt sources to any of the 11 available interrupt channels by wire wrapping between the appropriate pins on the header Designed to provide maximum flexibility in interrupt source selection the interrupt sources provided are PC3 which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI EXT an external interrupt you can route onto the board through the P2 I O connector and eight of the 10 counter outputs counters 5 and 10 1 4 are not prov
101. een This value should start at 0 and increment once each second COUNTER 1 COUNTER 2 DIVIDER 10 000 DIVIDER 500 COUNTER 3 The first lines of the program initialize the board The address in the variable BA must match the setting of the base address switch S1 on the board The factory setting of S1 is 300 hex 768 decimal int board result dr cr board 768 dr board 12 cr board 14 Now reset the Am9513A timer counter chip see Table 5 2 outport cr O0xff AM9513A MASTER RESET Next set up the Am9513A master mode register see Figure 5 1 These are the settings we will use Scaler Control binary division Data Pointer Control disable increment Data Bus Width 16 bits FOUT Gate FOUT on FOUT Divider divide by 16 FOUT Source F1 see Figure 5 3 Compare 2 Enable disabled Compare 1 Enable disabled Time of Day Mode disabled VALUE HEX 6000 outport cr 0xff17 point to master mode register table 5 1 outport cr 0x00 master mode lsb outport cr 0x60 master mode msb 5 3 Table 5 1 Load Data Pointer Commands Register Register Register Register FF13 FF1B FFO4 FFOC FF14 FFIC FFOS FFOD FF15 FF1D Master Mode Register FF17 Alarm 1 Register FF07 Alarm 2 Register FFOF Status Register FF1F Next set up the counter 1 mode register see Figure 5 2 These are the settings we wil
102. ent the counter by one The STEP command will take effect even on a disarmed counter Load Data Pointer Register Coding C7 C6 C5 C4 C2 C1 E2 G4 G2 Gi G4 G2 G1 000 110 Description Bits in the E and G fields will be transferred into the corresponding Element and Group fields of the Data Pointer register as shown in Figure 1 9 The Byte Pointer bit in the Data Pointer register is set Transfers into the Data Pointer only occur G field values of 001 010 011 100 101 and 111 Values of 000 and 110 for G should not be used See the Setting the Data Pointer Register section of this document for additional details Disable Data Pointer Sequencing C7 C6 C5 C4 C3 C2 Ci 1 1 1 0 1 0 0 co 0 Coding Description This command sets Master Mode bit 14 without affecting other bits in the Master Mode register MM14 controls the automatic sequencing ofthe Data Pointer register Disabling the sequencing allows repetitive host processor access to a given internal location without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode register Enable Data Pointer Sequencing 0 C6 C5 C4 C3 C2 Ci 1 1 1 0 0 0 0 Coding Description This command clears Master Mode bit 14 without affecting other bits in the Master Mode register MM14 controls the automatic sequencing of the Data Pointer register Enabling the sequencing al
103. ephone number and a brief description of the problem 1 BOARD SETTINGS The TC1024 has jumper and switch settings you can change if necessary for your application The board is factory configured as listed in Table 1 1 and shown on the board layout in the beginning of this chapter Should you need to change these settings use these easy to follow instructions before you install the board in your computer To increase your flexibility in using interrupts a wire wrap header is provided at P7 so that you can connect any one of 11 interrupt sources to any one of 11 interrupt channels Note that by installing resistor packs at the locations labeled to the right of the 8255 PPI and soldering jumpers as desired on the associated pads you can configure your 8255 digital I O lines to be pulled up or pulled down This procedure is explained near the end of this chapter Pads are provided in the upper right area of the board so that you can add custom resistor capacitor filtering on each clock source input line for switch debouncing and to eliminate unwanted ringing 1 1 Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switches on the TC1024 board Fig ure 1 1 shows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of
104. er will go immediately to TC This occurs because the LOAD operation is performed by generating a pseudo count pulse internal to the 9513 and the Am9513 is expecting to go into TC on the next count pulse The reload source used to reload the counter will be the same as that which ARM and DISARM commands can be used to gate counter operation on and off under software control DISARM commands entered while a counter is in the TC state will not take effect until the counter leaves TC This ensures that the counter never latches up in a TC state The counter may leave the TC state would have been used if the TC were generated by a source because of application of a count source edge execution of a edge rather than by the LOAD operation LOAD or LOAD and ARM command or execution of a STEP Execution of LOAD LOAD and ARM command while a command counter is in TC will cause the TC to end For Armed counters in 1 26 modes except S or V LOAD source used will be that to be used for the upcoming TC The LOADing operation will not alter the selection of reldad source for the upcoming TC For Dis armed counters in modes except or V the reload sources used will be the LOAD register For modes or V the reload source will be selected by the GATE input regardless of whether the counter is Armed or Disarmed Special considerations apply when modes with alternating re load sources are used Modes G L If a LOAD comm
105. errupt routine Because the second routine has changed the Data Pointer register the first routine will not read the Hold register 1 contents As can be seen from the above scenario the sequence of operations of setting the Data Pointer register and accessing internal register locations must not be interrupted by another Am9513 service routine One way of ensuring that this restriction is met is to disable interrupts before setting the Data Pointer and not enabling inter rupts until the register accesses are performed Note that when auto sequencing is used interrupts should not be enabled until all registers have been accessed An alternative method of meeting this restriction is to use software semaphores to prevent nesting of Am9513 service routines Figure 2 7 shows sample interrupt service routines which set the Data Pointer register to point to Counter 1 s Hold register and enable Hold cycle auto sequencing by clearing MM14 In AmZ8002 case 16 bit data bus interface is assumed requiring that the upper command byte be FF hex In the coding examples given interrupts are disabled and enabled by software command Since the AmZ8002 architecture loads a new Flag and Control Word FCW when responding to an 0113 DB12 Der oe ptes ws 2 gt Interrupt request the FCW loaded can disable further inter rupts This provides an alternative interrupt inhibiting mechanism for AmZ8002 systems and may be used in lie
106. field of the Counter Mode register is 001 or 010 and active low if the Output Control field is 101 MASTER MODE CONTROL OPTIONS The 16 bit Master Mode MM register is used to control those internal activities that are not controlled by the individual Counter Mode registers This includes frequency control Time of Day operation comparator controls data bus width and data pointer sequencing Figure 1 13 shows the bit assignments for the Mas ter Mode register This section describes the use of each control field Master Mode register bits MM12 MM13 and MM14 can be indi vidually set and reset using commands issued to the Command register In addition they can all be changed by writing directly to the Master Mode register After power on reset or a Master Reset command the Master Mode register is clearedto an ail zero condition This results in the following configuration Time of Day disabled Both Comparators disabled FOUT Source is frequency F1 FOUT Divider set for divide by 16 FOUT gated on Data Bus 8 bits wide Data Pointer Sequencing enabled Frequency Scaler divides in binary 0000 Divide by 16 0001 Divide by 1 0010 Divide by 2 0011 Divide by 3 0100 Divide by 4 0101 Divide by 5 0110 Divide by 6 0111 Divide by 7 1000 Divide by 8 1001 Divide by 9 1010 Divide by 10 1011 Divide by 11 1100 Divide by 12 1101 Divide by 13 1110 Divide by 14 1111 Divide by 15
107. from the computer 51 is factory set at 300 hex 768 decimal The following sections describe the register contents of each address used in the I O map Table 4 1 TC1024 Map Address Register Description Read Function Decimal Program Port A digital output 8255 PPI Port A Read Port A digital input lines lines 0 Program Port B digital output 8255 PPI Port B Read Port B digital input lines lines BA 2 Program Port C digital output 8255 PPI Port C Read Port C digital input lines lines 4 8255 Control Word Program PPI configuration 6 Read data register for Program data register for Am9513A 1 Data Word Counters 1 5 Counters 1 5 BA 8 Read control register for Program control register for Am9513A 1 Control Word Counters 1 5 Counters 1 5 BA 10 Read data register for Program data register for Am9513A 2 Data Word Counters 6 10 Counters 6 10 BA 12 Read control register for Program control register for Am9513A 2 Control Word Counters 6 10 Counters 6 10 BA 14 BA Base Address BA 0 PPI Port A Digital VO Read Write 8 bit operation Transfers the 8 bit Port A digital input and digital output data between the board and an external device A read transfers data from the external device through on board connector P4 and into PPI Port A a write transfers the written data from Port A through P4 to an external device 2 PPI Port B Digital Read Write 8 bit ope
108. function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines 4 10 which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which involve checking to see if any DOS functions are currently active when your ISR is called but such
109. ggled output is active high or active low contents will act the same as application of a source pulse is the level of the output at the start of the count cycle This causing TC to remain active and a TC Toggled output to toggle can be controlled by the Set and Clear Output commands See Figure 1 21 Count Control Counter Mode bits CM3 through CM7 specify the various options TC Terminal Count available for direct control of the counting process CM3 and CM4 On each Terminal Count TC the counter will reload itself from operate independently of the others and control up down and the Load or Hold register TC is defined as that period of time BCD binary counting They may be combined freely with other when the counter contents would have been zero had no reload contro bits to form many types of counting configurations The occurred Some special conditions apply to counter operation other three bits and the Gating Control field interact in complex immediately before and during TC ways Bit CM5 controls the repetition of the count process When CM5 1 counting will proceed in the specified mode until the that commits the counter to go to TC on the next count and counter is disarmed When CM5 0 the count process will retriggering by a hardware Gate edge Modes N O Q and R proceed only until one full cycle of operation occurs This may or a software LOAD or LOAD and ARM command will not occur after one or two TC events The counter is the
110. he board in your computer check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To install the board 1 Turn OFF the power to your AT computer 2 Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this 3 Select any unused expansion slot and remove the slot bracket 4 Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag 5 If you are using the 20 pin P4 connector for 8255 digital I O operations connect the mating connector to it before installing the board in the PC Note that the P3 connector mounting bracket has an oversized cutout to allow space for running the cable to P4 through the same I O slot If you want to run both cables through the same slot you must make these connections before installing the board 6 Holding the board by its edges orient it so that its card edge bus connectors line up with the expansion slot connectors in the bottom of the selected expansion slot 7 After carefully positioning the board in the expansion slot so that the card edge connectors are resting on the computer s bus connectors gently and evenly press down on the board un
111. he property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LI
112. hose edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off On each TC the counter will reload from the Load register and automatically disarm itself inhibiting further counting until a new ARM command is issued COUNT COMMAND OUTPUT wane TENER TC TOGGLED OUTPUT Figure 1 17a Mode A Waveforms 1 12 Bere en on ARM COMMAND XXX DD OE TC OUTPUT TC TOGGLED OUTPUT TE i m MOS 589 Figure 1 17b Mode B Waveforms MODE C Hardware Triggered Strobe E IE Mode shown in Figure 1 17c is identical to Mode except that counting will not begin until a Gate edge is applied to the armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded The counter will start counting on the first source edge after the triggering Gate edge and will continue counting until TC At TC the counter will reload from the Load register and automatically disarm itself Counting will then remain inhibited until a new ARM command and a new Gate edge are applied in that order Note that after application of a triggering Gate edge the Gate input will be disregarded for the remainder of the count cycle This difters from Mode B where the G
113. ided however they are available at 5 and P6 You can wire wrap any source to any of 11 interrupt channels IRQ9 highest priority channel through IRQ12 IRQ14 IRQ15 and then back to IRQ3 through IRQ7 lowest priority Chapter 4 explains interrupt channel prioritization in detail If you use multiple interrupts make sure each source is assigned to a different IRQ channel S8 98764321 TEA Factory Setting IRQ 15 14 121110 97 6 5 4 3 3 3 m OUT 60 98764321 Fig 1 46 EXT Connected 000000 Er to IRQ11 O IRQ 15 14 121110 976543 Fig 1 4 Interrupt Source Channel Select Wire Wrap Header 7 51 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the TC1024 board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the TC1024 has an easily accessible DIP switch S1 which lets you select any one of 32 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any value shown in Table 1 2 The table shows the switch settings and their
114. ient The concatenation examples so far have assured that the count ers are to count repetitively in the sense of counter mode register bit CM5 If count once operation is desired in which the counters require an Arm command after each count cycle dif ferent circuits are required SOURCE When no count once operation is desired the circuit in Figure 3 4 can be used In this application Counter 1 should be programmed for active high level gating and Counter 2 should be programmed for a TC Toggled output During counter initializa tion the following set of commands should be used Initialize Counters 1 and 2 Mode and Load registers LOAD Counters 1 and 2 Clear Counter 2 output ARM Counters 1 and 2 The counters are now ready to count but since Counter 2 s output is low Counter 15 gate will inhibit counting To start counter operation use the Set Counter 2 s output command The counters will then count applied source pulses until Counter 2 reaches TC and toggles its output inhibiting Counter 1 s gate It can be seen that in this application the Set Counter 2 s output behaves as an ARM command It is important that the counting rate be iow enough to ensure that Counter 1 s gate will not go inactive in close proximity to a source edge High speed appli cations using a Counter 1 source period less than the propagation delay from Counter 1 s source to Counter 2 s output should use a flip flop to synch
115. if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is determined by the number of the IRQ Because of the configuration of the two controllers with one chained to the other through IRQ2 the priority scheme is a little unusual IRQO has the highest priority IRQ1 is second highest then priority jumps to IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 and 18 015 and then following IRQ15 it jumps back to IRQ3 IRQ4 IRQS IRQ6 and finally the lowest priority IRQ7 This sequence makes sense if you consider that the controller that handles IRQ8 IRQ15 is routed through IRQ2 8259 Programmable Interrupt Controllers The chips responsible for handling interrupt requests in the PC are the 8259 Programmable Interrupt Control lers The 8259 that handles IRQO IRQ7 is referred to as 8259A and the 8259 that handles IRQ8 IRQ1S is referred to as 8259B To use interrupts you need to know how to read and set the 8259 interrupt mask registers IMR and how to send the end of interrupt EOI command to the 8259s Interrupt Mask Registers IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line in 8259A bit 0 is for IRQO bit 1 is for and so on while in 8259B bit O is for IRQ8 bit 1 is for IRQ9 and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not genera
116. igure 1 171 L Waveforms ARM COMMAND COUNT Figure 1 17n Mode N Waveforms MODE Software Triggered Strobe with Edge Gating and Hardware Retriggering Mode O shown in Figure 1 170 is similar to Mode N except that counting will not begin until an active going Gate edge is applied to an armed counter and the Gate level is not used to modulate ARM COMMAND NSW CS CD 5 Figure 1 170 Mode Waveforms counting The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded Irrespective of the Gate level the counter will count all source edges after the triggering Gate edge until the first TC On the first TC the counter will be reloaded from the Load register and disarmed A new ARM command and a new Gate edge must be applied in that order to initiate a new counting cycle Unlike Modes and L which disregard the Gate input once counting starts in Mode O the count process will be retriggered on all active going Gate edges including the first Gate edge used to start the counter On each retriggering Gate edge the counter contents will be transferred into the Hold register On the first source edge after the retriggering Gate edge the Load register contents will be transferre
117. ilored for a wide variety of applications The counters are clocked by an on board 5 MHz crystal On board RC pads let you custom filter each clock input line for switch debouncing and elimination of unwanted ringing The source gate and output for each counter is available at the P2 I O connector Digital O The TC1024 has 24 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closures trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip The 8255 can be operated in any one of the three available modes Mode 0 Mode 1 or Mode 2 To ensure high driving capacity in Mode 0 CMOS buffers are installed These buffers can be bypassed to support Mode 1 or 2 operation TTL buffers are available on request Pads for installing and activating pull up or pull down resistors are included on the board Installation proce dures are given at the end of Chapter 1 Board Settings What Comes With Your Board You receive the following items in your TC1024 package TC1024 AT interface board Software and diagnostics diskette with Turbo Pascal and Turbo C source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition
118. in Figure 1 17r is similar to Mode Q except that edge gating rather than level gating is used In other words rather than use the Gate level to qualify which source edges to count Gate edges are used to start the counting operation The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded After application of a Gate edge an armed counter will count all source edges until TC irrespective of the Gate level On the first TC the counter will be reloaded from the Load register and stopped Subsequent counting will not occur until a new Gate edge is applied All Gate edges applied to the counter including the first used to trigger counting initiate a retrigger operation Upon appli cation of a Gate edge the counter contents are saved in the Hold register On the first source edge after the retriggering Gate edge the Load register contents will be transferred into the counter Counting will resume on the second source edge after the retrig gering Gate edge Figure 1 17q Mode Q Waveforms ose E COUNT TC OUTPUT TC TOGGLED OUTPUT Figure 1 17r Mode R Waveforms 1 20 MODE 5 px xps xs eee Inthis mode the reload source for LOAD commands irrespective of whether the counter is armed or disarmed and for TC initiated reloads is determined by the
119. ing from the correct port locations on the board These ports were defined in the previous section Because the TC1024 is AT bus compatible reading writing the Am9513As is done in a 16 bit word format All other operations are done in an 8 bit word format High level languages such as Pascal C and C make it very easy to read write these ports The table below shows you how to read from and write to I O ports in Turbo and Turbo Pascal Read 8 Bits Write 8 Bits Read 16 Bits Write 16 Bits Data inportb Address outportb Address Data Data inport Address outport Address Data Turbo Pascal Data Port Address Port Address Data Data PortW Address PortW Address Data In addition to being able to read write the I O ports on the TC1024 you must be able to perform a variety of operations that you might not normally use in your programming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal and C amp a b c a b c a b amp c a blc Pascal MOD DIV AND OR a bMODc a bDIVc a bANDc a bORc Many compilers have functions that can read write either 8 or 16 bits from to port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for 16 bit read Be sure to use the correct function for 8 bit and 16 bit operations with the TC1024
120. intel 82C55A MODE 0 Configurations Continued CONTROL WORD 12 D 04 Dy D D D D D CONTROL WORD 13 D Os 05 D D D D Do Operating Modes MODE 1 Strobed input Output This functional configuration provides a means for transferring 1 O data to or from a specified port in conjunction with strobes or handshaking signals In mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals 3 133 CONTROL WORD 14 D D D D 0 D D CONTROL WORD 15 D De D D D Do 231256 12 Mode 1 Basic functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched e The 4 bit port is used for control and status of the 8 bit data port intel 82 55 Input Control Signal Definition STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one
121. ischarged and consequently for the gate voltage to rise high enough to break down the oxides and destroy the transister All inputs to the Am9513 include protection networks to help prevent damaging accumulations of static charge The protection circuitry is de signed to slow the transistions of incoming current surges and to provide low impedance discharge paths for voltages beyond the normal operating levels Note however that input energy levels can nonetheless be too high to be successfully absorbed Con ventional design storage and handling precautions should be observed so that the protection networks themselves are not overstressed Within the limits of normal operation the input protection circuitry is inactive and may be modeled as a lumped series RC as shown in Figure 1 7a The functionality active input connection during normal operation is the gate of an MOS transistor No active Sources or drains are connected to the inputs so that neither transient nor steady state currents are impressed on the driving signals other than the charging or discharging of the input capacitance and the accumulated leakage associated with the protection network and the input circuit FUNCTIONALLY ACTIVE INTERNAL CIRCUITRY EQUIVALENT INACTIVE n PROTECTION CIRCUITRY b Figure 1 7 Input Circuitry The only exception to the purely capacitive input case is the X2 crystal input As shown in Figure 1 7b an internal resistor con
122. it Counter Mode CM register used to control all of the individual options available with its associated general counter These options include output configuration count control count source and gating control Figure 1 18 shows the bit assignments for the Counter Mode registers This section describes the control options in detail Note that generally each counter is independently configured and does not depend on information outside its Counter Logic Group The Counter Mode register should be loaded oniy when the counter 15 Disarmed Attempts to load the Counter Mode register when the counter is armed may result in erratic counter operation After power on reset or a Master Reset command the Counter Mode registers are initialized to a preset condition The value entered is hex and results in the following control configuration Output low impedance to ground Count down Count binary Count once Load register selected No retriggering F1 input source selected Positive true input polarity No gating Output Control Counter mode bits CMO through CM2 specify the output control configuration Figure 1 19 shows a schematic representation of the output control logic The OUT pin may be off a high imped ance state or it may be inactive with a low impedance to ground The three remaining valid combinations represent the active High active Low or TC Toggle output waveforms One output form available is called Terminal Count
123. ite 4 3 BA 6 8255 PPI Control Word Write 4 4 BA 8 Am9513A 1 Data Register Read Write erersneserssnnsensnennennennnenonnnenanssnonsnoaossnssnnsnnessersonessossnnnnn 4 5 10 Am9513A 1 Command Register Read Write 4 5 12 Am9513A 2 Data Register Read Write eee esee nein then ethernet netta thereon 4 5 14 Am9513A 2 Command Register 4 5 Programming tlie TOO 4 6 Clearing and Setting Bits in a Port 4 6 Initializing the Am9ST3A 4 8 Tnitiahz nsthe 8255 2n 4 8 Digital O Operations recte el tada 4 8 M 4 9 What Isan Interr pt eerte nie 4 9 Interrupt Request Lines erteilen 4 9 8259 Programmable Interrupt Controllers sessi enne eene tenent entente 4 9 Interrupt Mask Registers 4 9 End of Interrupt Command 4 10 What Exactly Happens When
124. l use Gating Control no gating Source Edge rising edge Count Source Selection 1 Count Control disable special gate reload from load count repetitively binary count count down Output Control TC toggled VALUE HEX 0B22 outport cr O0xff01 point to counter 1 mode register table 5 1 outport dr 0x0b22 counter 1 mode Put the hex number 2710 decimal 10 000 in counter 1 load register outport cr Oxff09 point to counter 1 load register table 5 1 outport dr 0x2710 counter 1 data Next set up the counter 2 mode register see Figure 5 2 These are the settings we will use Gating Control gating Source Edge rising edge Count Source Selection TCN 1 Count Control disable special gate reload from load count repetitively binary count count down Output Control TC toggled VALUE HEX 0022 Table 5 2 Am9513A Command Summary Command Code c2 co Command Description 1 35 sa s3 52 51 counting for all selected counters Tr si am s 3 se st Deam s comes _ ss se se 5 vo asc coutsinnotteger _ 95 se 59 fa fo Set toggle out high for counter N 00
125. low Z to gnd Data Bus Width 0 8 bit bus 1 16 bit bus Compare 1 Enable 0 disabled 1 enabled Data Pointer Control 0 enable increment 1 disable increment Time of Day Mode 00 TOD disabled 01 TOD enabled 5 input 10 TOD enabled 6 input 11 TOD enabled 10 input Scaler Control 0 binary division 1 BCD division Fig 5 1 Master Mode Register Bit Assignments Next set up the counter 3 mode register see Figure 5 2 These are the settings we will use Gating Control no gating Source Edge rising edge Count Source Selection TCN 1 Count Control disable special gate reload from load count repetitively binary count count up Output Control TC toggled VALUE HEX 002A 5 6 Count Source Selection Counter Control 0000 TCN 1 0 disable special 0001 SRC 1 1 enable special gate 0010 SRC2 0011 SRC 3 0 reload from load 0100 SRC 4 1 reload from load 0101 SRC 5 hold 0110 1 except in mode X 0111 2 which reloads only 1000 from load 1001 4 1010 5 0 count once 1011 F1 1 count repetitively 1100 F2 1101 0 count 1110 4 1 BCD count 1111 F5 0 count down 1 count up Een aaa SE E aa Source Edge 0 count on rising edge Output Control 1 count on falling edge 000 inactive output low 001 active high terminal puls
126. lows sequential host processor access to sev eral internal locations without repetitive updating of the Data Pointer MM14 may also be controlled by loading a full word into the Master Mode register See the Data Pointer Register sec tion of this document for additional information on Data Pointer sequencing Enable 16 Bit Data Bus C7 C6 C5 C4 C3 C2 Ci 1 1 1 1 1 Coding Description This command sets Master Mode bit 13 without affecting other bits in the Master Mode register MM13 controls the multiplexer in the data bus buffer When MM13 is set no multiplexing takes place and all 16 external data bus lines are used to transfer information into and out of the STC MM13 may also be controlled by loading the full Master Mode register in parallel Enable 8 Bit Data Bus C7 C6 C5 C3 C2 C1 CO Coding Mode register in parallel Gate Off FOUT C5 C4 C2 Ci CO Coding Description This command sets Master Mode bit 12 without controlled by loading the full Master Mode register in parallel 1 28 Gate On FOUT C7 C6 C5 C4 C3 C2 Ci CO 1 1 1 0 0 1 1 0 Coding Description This command clears Master Mode bit 12 without affecting other bits in tne Master Mode register MM12 controls the output status of the FOUT signal When 12 is cleared FOUT will become active and will drive out the selected and divided FOUT signal MM12 may also be controlled by loading the full Master Mode
127. med the counter will count continuously until it is issued a DISARM command On the first TC the counter will be reloaded from the Hold register Counting will then proceed until the second TC at which time the counter will be reloaded from the Load register Counting will continue with the reload source alternating on each TC until a DISARM command is issued to the counter The third TC reloads from the Hold regis ter the fourth TC reloads from the Load register etc A variable duty cycle output can be generated by specifying the TC Toggled output in the Counter Mode register The Load and Hold values then directly control the output duty cycle with high resolution available when relatively high count values are used COUNT VALUE TC OUTPUT MODE Variable Duty Cycle Rate Generator with Level Gating eva ao po Mode K shown in Figure 1 17k is identical to Mode J except that source edges are only counted when the Gate is active The counter must be armed for counting to occur Once armed the counter will count all source edges which occur while the Gate is active and disregard those source edges which occur while the Gate is inactive This permits the Gate to turn the count process on and off As with Mode the reload source used will alternate on each TC starting with the Hold register on the first TC after any ARM command When the TC Toggled output is used this mode allows the Gate to modulat
128. n disarmed extend the time to TC Note that the next count driving the automatically The single or double TC requirement will depend counter to TC can be caused by the application of a count on the state of other control bits Note that even if the counter is Source edge in level gating modes the edge must occur while automatically disarmed upon a TC it always counts the count the gate is active or it will be disregarded by the application source edge which generates the trailing TC edge of a LOAD or LOAD and ARM command see 2 below or by When TC occurs the counter is always reloaded with a value 1 In the clock cycle before TC an internal signal is generated the application of a STEP command from either the Load register or the Hold register Bit CM6 2 LOAD or LOAD and ARM command is executed during specifies the source options for reloading the counter When CM6 the cycle preceding TC the counter will immediately goto TC 0 the contents of the Load register will be transferred into the If these commands are issued during TC the TC state will counter at every occurrence of TC When CM6 1 the counter immediately terminate reload location will be either the Load or Hold Register The 3 When TC is active the counter wili always count the next reload location in this case may be controlled externally by using source edge issued to it even if it is disarmed or gated off a GATE pin Modes S and V or may alternate on each T
129. n external interrupt you can route onto the board through I O connector P3 Chapter 1 tells you how to set the jumpers or configure the wire wrapping on the interrupt header connectors P5 P6 and P7 and Chapter 4 describes how to program interrupts CHAPTER 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program your TC1024 board by writing to and reading from the AT bus in 8 or 16 bit words It provides a complete description of the map and a description of programming operations to aid you in programming The example programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C and Turbo Pascal include source code to simplify your applications programming Chapter 5 contains examples for setting up Am9513A s 16 bit counters for specific applications Defining the VO The map for the TC1024 is shown in Table 4 1 below As shown the board occupies 16 consecutive I O port locations Because of the 16 bit structure of the AT bus every other address location is used even for 8 bit transfers Our programming structure uses the 16 bit command to set up and run the Am9513A All 8255 read write operations are 8 bit operations The base address designated as BA can be selected using DIP switch S1 as described in Chapter 1 Board Settings This switch can be accessed without removing the board
130. nd it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B 14 17 16 19 PORTC PINS 0 3 Lower nibble of Port C PBo 7 20 22 PORT PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer Voc 26 2 SYSTEM POWER sv Power Supply D7_9 27 34 DATA BUS Bi directional tri state data bus lines connected to system data bus RESET RESET A high on this input clears the control register and all ports are set to the input mode WR WRITE CONTROL This input is low during CPU write operations 7_4 37 40 41 44 PORT A PINS 4 7 Upper nibble of 8 bit data output latch buffer and an 8 bit data input latch 1 12 No Connect 23 34 3 125 intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose O component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer
131. ng TC square waves in Operating Modes G through K This may cause count sequences different from what a user might In Mode L the TC Toggled output can be used to generate a expect Since the counter is always reloaded at the start of TC one shot function with the delay to the start of the output pulse and since it always counts at the end of TC the counter contents and the width of the output pulse separately programmable With following TC will differ by one from the reloaded value irrespec selection of the minimum delay to the start of the pulse the output tive of the operating mode used will toggle on the second source pulse following application of the If the reloaded value was 0001 for down counting 9999 BCD for triggering Gate edge BCD up counting or FFFF hex for binary up counting the count Note that the TC Toggled output form contains no implication at the end of TC will drive the counter into TC again regardless of about whether the output is active high or active low Unlike the whether the counter is gated off or disarmed As long as these TC output which generates a transient pulse which can clearly be values are reloaded the TC output will stay active If a TC Tog active high or active low the TC Toggled output waveform only gled output is selected it will toggle on each count Execution of a flips the state of the output on each TC The sole criteria of LOAD LOAD and ARM or STEP command with these counter whether the TC To
132. ns 1 1 1 2 1 3 1 2 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 2 1 3 1 5 1 5 2 5 3 Board Layout Showing Factory Configured Settings eese 1 3 Counter OUT 2 5 Interrupt Channel Select Jumper PS sees 1 4 Counter OUT 7 10 Interrupt Channel Select Jumper P6 esses 1 4 Interrupt Source Channel Select Wire Wrap Header P7 essere 1 5 Base Address Switch Sl 2 20 ote dee ri 1 5 Buffer Silence 1 7 Port A Buffer zu AN 1 7 Interrupt Source Clock Source Select SPDT Switch S4 1 8 Counter Circuitry Showing S4 Switch Connections eene nnne 1 9 Pull up Pull down Resistor Circuitry eese eene nennen nen enen eene 1 10 Adding Pull ups and Pull downs to Some Digital Lines eene 1 11 Typical Switch Debouncing Filter Circuit essent 1 12 I O Connector and P4 On board Connector Pin Assignments esee 2 4 TC1024 Block Diagramm essen 3 3 Master Mode Register Bit Assignments 5 6 Counter Mode Register Bit 5 7 Frequency Scaler Ratio tenente tenente tenentem ntes ntn tnnt nens 5 8 iii INTRODUCTION The TC1024 Advanced Industrial Control board turns your IBM or compatible into high pe
133. ns to be used as gates for a given counter On Counter 4 for example pin 34 pin 35 or pin 36 may be used to perform the gating function This also allows a single Gate pin to simultaneously control up to three counters Counters 1 and 5 are considered adjacent when using 1 001 Gate N 1 010 and Gate N 1 011 controls For codes of 110 or 111 in this field counting proceeds after the specified active Gate edge until one or two TC events occur Within this interval the Gate input is ignored except for the retriggering option When repetition is selected a cycle will be repeated as soon as another Gate edge occurs With repetition selected any Gate edge applied after TC goes active will start a new count cycle Edge gating is useful when implementing a digital single shot since the gate can serve as a convenient firing trigger A 001 code in this field selects the TC output from the adjacent lower numbered counter as the gate This is useful for synchro nous counting when adjacent counters are concatenated COMMAND DESCRIPTIONS The command set for the Am9513 allows the host processor to customize and manage the operating modes and features for particular applications to initialize and update both the inter nal data and control information and to manipulate operating bits during operation Commands are entered directly into the 8 bit Command register by writing into the Control port see Figure 1 8 All available
134. ntroller s Since 8259B generates a request on IRQ2 which is handled by 8259A an EOI must be sent to both 8259A and 8259B for IRQ8 IRQ1S5 Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automati cally pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by these requirements take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not use any DOS functions or routines that call DOS functions from within an ISR DOS 15 not reentrant that is a DOS
135. nverter contained in the Am9513 and accordingly X1 should be left floating to avoid damaging the inverter s output stage Applications using the internal oscillator can drive the X1 and X2 inputs with an RC network an external non TTL level squarewave or a crystal Figure 2 3 shows the recommended methods of connecting different frequency sources to the internal oscillator s input A crystal provides a highly accurate frequency source at moder ate cost and will usually be the preferred method of operation The Am9513 is designed to use a crystal in parallel resonant fundamental mode operation using the connection diagram shown in Figure 2 3a Most series resonant crystals can also be used but the oscillator frequency will be different by up to a few percent from the series resonant crystal s rated frequency Two ceramic capacitors should be connected between X1 and X2 to ground to ensure proper crystal loading The crystal loading is the capacitance the crystal should be driving to ensure on frequency operation and reliable oscillator startup Although the crystal sees the capacitors on X1 and X2 in series and neglects the ground connection in the center the use of two capacitors stabilizes the bias on the crystal by referencing it to ground and provides superior performance over the one capacitor equivalent circuit Ceramic capacitors are the best type for this application because of their stability over time and temperature and their
136. odule definition for the counter The Hold register may also be used to store accumulated counter values for later transfer to the host processor This allows the count to be sam pled while the counting process proceeds without interruption Transfer of the counter contents into the Hold register is ac complished by the hardware interface in some operating modes or by software commands at any time Counter Mode Register The 16 bit read write Counter Mode register controls the gating counting output and source select functions within each Counter Logic Group The Counter Mode Control Options section of this document describes the detailed control options available Figure 1 18 shows the bit assignments for the Counter Mode registers Alarm Registers and Comparators Added functions are available in the Counter Logic Groups for Counters 1 and 2 see Figure 1 2 Each contains a 16 bit Alarm register and a 16 bit Comparator When the value in the counter reaches the value in the Alarm register the Comparator output will go true The Master Mode register contains control bits to individually enable disable the comparators When enabled the comparator output appears on the OUT pin of the associated counter in place of the normal counter output The output will remain true as long as the comparison is true that is until the next input causes the count change The polarity of the Comparator output will be active high if the Output Control
137. ol turning motors on and off These motors turn on when the digital lines controlling them are high The Port A and Port B lines of the 8255 automatically power up as inputs which can float high during the few moments before the board is initialized This can cause external devices connected to these lines to operate erratically By pulling these lines down when the data acquisition system is first turned on the motors will not switch on before the 8255 is initialized To use the pull up pull down feature you must first install resistor packs in any or all of the four locations around the 8255 labeled PA PB PCL and PCH PA and PB take 10 pin packs and PCL and PCH take 6 pin packs Figure 1 10 shows a blowup of this circuitry 3459 0000000000 1009 8 0000000000 50109090 0000000 0000000 4HCT243 5 74HCT243 210000000 0060000 1999097 0990999 0550505509 0000000000 74HCT245 9900000000 00000000000000000000 s OD 500000000000000000000 2 4009555 S 34 00000 00000000 211920000 095550 00000000000000000000 60000 00000000 2056099 99050006000 2889 3 Dooo 000660660600 555 aa 74 245 0500 450000 9951066650556 00000000000000000000 o gt in 1990550505550 E 0000000 0000000 0955505 0006060600000 5 011595555 8555555 0595
138. operating in Mode 1 the on board buffers must be removed from the Port C lines When operating in Mode 2 both Port A and Port C buffering must be removed This procedure is described in Chapter 1 in the S2 and S3 DIP switch discussion The three operating modes are Mode 0 Basic input output Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A in conjunction with strobes or hand shaking signals Mode 2 Strobed bidirectional input output Lets you communicate bidirectionally with an external device through Port A Handshaking is similar to Mode 1 These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C The bidirectional buffers on the 8255 s I O lines monitor the 8255 control word to automatically set their direction Hardware changes to the buffer circuitry are required only when using Mode 1 or Mode 2 where the Port A and or Port C buffers must be removed as described in Chapter 1 Interrupts The TC1024 has several hardware selectable interrupt sources These interrupt sources can be selected using jumpers or wire wrapping on P5 through P7 as described in Chapter 1 Interrupt sources which can be used by the TC1024 are the outputs from all 10 Am9513A counters PC3 which is the INTRA signal from the 8255 PPI PCO which is the INTRB signal from the 8255 PPI and EXT a
139. operating mode for each counter see Figure 1 16 To simplify references to a particular mode each mode is assigned a letter from A through X Representative waveforms for the counter modes are illustrated in Figures 1 17a through 1 17v Because the letter suffix in the figure number is keyed to the mode Figures 1 17m 1 17p 1 17t 1 17u and 1 17w do not exist The figures assume down counting on rising source edges Those modes which automatically disarm the counter CM5 0 are shown with the WR pulse entering the required ARM com mand for modes which count repetitively CM5 1 the ARM command is omitted The retriggering modes N O Q and R are shown with one retrigger operation Both a TC output waveform and a TC Toggled output waveform are shown for each mode The symbols L and H are used to represent count values equal to the Load and Hold register contents respectively The symbols K and represent arbitrary count values For each mode the required bit pattern in the Counter Mode register is shown don t care bits are marked X These figures are designed to clarify the mode descriptions the Am9513 Electrical Specification should be used as the authoritative reference for timing relation ships between signals Appendix B provides a key to the waveform symbols used in these diagrams To keep the following mode descriptions concise and to the point the phrase source edges is used to refer to active going sourc
140. or it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your TC 1024 board can interrupt the processor when a variety of conditions are met such as when any of the 10 timer countdowns is finished Interrupts can also be generated by the 8255 PPI or an external source By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the AT bus has 16 different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by one of the AT s two interrupt control chips One chip handles IRQO through IRQ7 and the other chip handles IRQ8 through IRQ15 The controller which handles IRQ8 IRQ15 is chained to the first controller through the IRQ2 line When an IRQ line is brought high the interrupt controllers check to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress they decide if the new request should supersede the one in progress or
141. or real time opera tion the time of day logic will accept 50Hz 60Hz or 100Hz input frequencies Each general counter has a single dedicated output pin It may be turned off when the output is not of interest or may be configured in a variety of ways to drive interrupt controllers Darlington buf fers bus drivers etc The counter inputs on the other hand are specifically not dedicated to any given interface line Consider able versatility is available for configuring both the input and the gating of individual counters This not only permits dynamic re assignment of inputs under software control but also allows multiple counters to use a single input and allows a single gate pin to control more than one counter indeed a single pin can be the gate for one counter and at the same time the count source for another A powerful command structure simplifies user interaction with the counters A counter must be armed by one of the ARM com mands before counting can commence Once armed the count ing process may be further enabled or disabled using the hardware gating facilities The ARM and DISARM commands permit software gating of the count process in some modes 16 BIT LOAD REGISTER MOS 142 Figure 1 3 Counter Logic Groups 3 4 and 5 The LOAD command causes the counter to be reloaded with the value in either the associated Load register or the associated Hold register It will often be used as a software re
142. pically be used to count events with a precision greater than 16 bits Count down concatenation is typically used to generate output frequencies of high resolution To simplify concatenation the Am9513 provides an internal TC signal from the low order counter which can be selected as a count source in the high order counter s Counter Mode register Thus although any two counters can be concatenated with ex ternal strapping usually adjacent counters will be used to allow use of this internal TC signal In count up concatenation both the high and low order counter s Load register should be cleared to O The low order counter will start counting up from O and increment through 9999 BCD counting is assumed throughout this discussion although binary counting may of course be used On the next source edge the low order counter will go to TC and reload 0 from the Load register The active going TC edge will also increment the high order counter The counters continue counting in this manner with the high order counter incrementing each time the low order counter reaches TC In the examples which follow Counters 1 and 2 will be used as the low order and high order counters respectively In the first up concatenation configuration shown in Figure 3 1 the counters do not use external gating and therefore will free run The high order counter should use the TC output of the low order counter as a source The high order counter should count on
143. puts to the CPU The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset BIT SELECT function of port C 1 2 31415 6 7 This function allows the Programmer to disallow or allow a specific 1 O device to interrupt the CPU with out affecting any other device in the interrupt struc ture BIT SET RESET FLAG 9 ACTIVE INTE flip flop definition 231256 7 BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Figure 7 Bit Set Reset Format Note Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82C55A Operating Modes Mode 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking is required data is simply written to or read from a specified port MODE 0 BASIC INPUT MODE 0 BASIC OUTPUT Mode 0 Basic Functional Definitions Two 8 bit ports and two 4 bit ports e Any port can be input or output e Outputs are latched Inputs are not latched 16 different Input Output configurations are pos sible in this Mode e 231256 8 231256 9 3 130 u intel 82C55A MODE 0 Port Definition GROUP A GROUP B CHEN PORTC _ roma Gereg
144. ration Transfers the 8 bit Port B digital input and digital output data between the board and an external device A read transfers data from the external device through external connector P3 and PPI Port B a write transfers the written data from Port B through P3 to an external device 4 PPI Port Digital VO Read Write 8 bit operation Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through on board connector P4 and into PPI Port C a write transfers the written data from Port C through P4 to an external device The bottom four bits PCO PC3 are also brought out to external connector P3 4 3 6 8255 PPI Control Word Write Only 8 bit operation When bit 7 of this word is set to 1 a write programs the PPI configuration The table below shows the control words for the 16 possible Mode 0 Port I O combinations Set Fla 9 Port Lower 0 output Mode Select 1 input 00 0 01 mode 1 PortB 10 mode2 0 output 1 input Port A 0 output Mode Select 1 input 0 mode 0 1 1 Port Upper _______________ 28 0 output Group A 1 input E 8255 Port I O Flow Direction and Control Words Mode 0 Control Word peu Port
145. rformance timing counting and control system Installed within a single expansion slot in the computer the TC1024 features 10 general purpose 16 bit timer counters two Am9513A chips 24 timer counter modes of operation Binary or BCD up or down counting 16 bit transfers using AT data bus Cascading of up to 10 counters 160 bits Pads for adding filters on clock input lines On board 5 MHz oscillator 24 buffered TTL CMOS 8255 based digital I O lines with optional pull up or pull down resistors 11 hardware configurable interrupts 5 volts only operation Turbo Pascal and Turbo C source code diagnostics program e e o o The following paragraphs briefly describe the major functions of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Am9513A Timer Counter The versatile Am9513A general purpose timer counter provides a variety of timing sequencing and counting functions The Am9513A chip contains five 16 bit counters which can be used individually or internally cascaded to form a counter of up to 80 bits The TC1024 has two Am9513A chips Am9513A 1 contains counters 1 through 5 and Am9513A 2 contains counters 6 through 10 With 24 operating modes up or down counting in binary or BCD and hardware or software gating these counters can be easily ta
146. ronize Counter 2 s outputto Counter 1 s source in order to meet timing parameters TGVEH and TEHGV in the 9513 data sheet High speed applications will end the count cycle with a value slightly larger than 1 in Counter 1 To add level gating to this count once feature simply involves the addition of an AND function before Counter 1 s gate input Now Counter 1 will be inhibited whenever Counter 2 toggles its output or whenever the external gate is driven low Note that this circuit assumes the externally applied gate is synchronous to the count source asynchronous gating signals should be syn chronized with a flip flop Am9513A Am9513 COUNTER 1 OUT INTERNAL TC SOURCE COUNTER 2 Counter 2 Mode Register MOS 610 Figure 3 3 Count Up Concatenation with Edge Gating 3 2 SOURCE LEVEL GATING OPTION EDGE GATING OPTION Am9513A Am9513 SOURCE COUNTER 1 GATE INTERNAL TC COUNTER 2 15 0 Counter 1 Mode Register 15 00 Counter 2 Mode Register MOS 611 Figure 3 4 Count Up Concatenation with Count Once Feature The final case of concatenated up counting comprises edge gating with the count once feature This is achieved through a simple variation of the level gating configuration An external gate signal sets the flip flop and enables counting providing Counter 2 s output is set When Counter 2 reaches TC its output will toggle i e clear and the flip flop
147. rupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your TC1024 program disk for a better under standing of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you write First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must write an end of interrupt command to the 8259 co
148. rystal should be parallel resonant fundamental mode type An RC or LC orother reactive network may be used instead of a crystal For driving from an external frequency source X1 should be left open and X2 should be connected to a TTL source and a pull up resistor FOUT Frequency Out Output The FOUT output is derived from a 4 bit counter that may be programmed to divide its input by any integer value from 1 through 16 inclusive The input to the counter is selected from any of 15 sources including the internal scaled oscillator frequencies FOUT may be gated on and off under software control and when off will exhibit a low impedance to ground Control over the various FOUT options resides in the Master Mode register After power up FOUT provides a frequency that is 1 16 that of the oscillator GATE1 GATE5 Gate Inputs The Gate inputs may be used to control the operations of indi vidual counters by determining when counting may proceed The same Gate input may control up to three counters Gate pins may also be selected as count sources f r any of the counters and for the FOUT divider The active polarity for a selected Gate input is programmed at each counter Gating function options allow level sensitive gating or edge initiated gating Other gating modes are available including one that allows the Gate input to 5V VCC 2 1 GATE 1 1 2 FOUT DB12 GATE SA DB11 GATE 4A DB10 GATE 3A DB9
149. s Ten of the available inputs are interface pins five are labeled SRC and five are labeled GATE The 16th available input is the TC output from the adjacent lower numbered counter The Counter 5 TC wraps around to the Counter 1 input This option allows internal concatenating that permits very long counts to be accumulated Since all five count ers may be concatenated it is possible to configure a counter that is 80 bits long on one Am9513 chip When TCN 1 is the source the count ripples between the connected counters External con nections can also be made and can use the toggle bit for even longer counts This is easily accomplished by selecting a TC Toggled output mode and wiring OUTN to one ofthe SRC inputs Gating Control Counter Mode bits CM15 CM14 CM13 specify the hardware gating options When gating is selected 000 the counter 1 25 will proceed unconditionally as long as it is armed For any other gating mode the count process is conditioned by the specified gating configuration For a code of 100 in this field counting can proceed only when the pin labeled GATEN associated with Counter N is at a logic high level When it goes low counting is simply suspended until the Gate goes high again A code of 101 performs the same function with an opposite active polarity Codes 010 and 011 offer the same function as 100 but specify alternate input pins as Gating Sources This allows any of three interface pi
150. sferred on the next access through the Data port Whenever the Data Pointer is loaded the Byte Pointer bit 15 set to one indicating a least significant byte is expected The Byte Pointer toggles following each 8 bit data transfer with an 8 bit data bus MM13 0 or it always remains set with the 16 bit data bus option MM13 1 The Element and Group pointers are used to select which internal register is to be accessible through the Data port Although the contents of the Element and Group Pointer in the Data Pointer register cannot be read by the host processor the Byte Pointer is available as a bit in the Status register Random access to any available internal data location can be accomplished by simply loading the Data Pointer using the com mand shown in Figure 1 10 and then initiating a data read or data write This procedure can be used at any time regardless of the setting ofthe Data Pointer Control bit MM14 When the 8 bit data bus configuration is being used MM13 0 two bytes of data would normally be transferred following the issuing of the Load Data Pointer command To permit the host processor to rapidly access the various internal registers automatic sequencing of the Data Pointer is provided COMMAND DATA POINTER CONTROL REGISTER REGISTER PORT 8 DATA BUS MULTIPLEXER GROUP AND ELEMENT ADDRESS COUNTER 1 MODE REGISTER PREFETCH ue LATCH M COUNTER 1 LOAD REGISTER 1 HOLD REGISTER ane COUNTE O
151. solutions are well beyond the scope of this discussion The second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most and Pascal interrupt routines automatically do this for you Put the body of your routine here Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H and port if you using IRQ8 IRQ 15 Pop all registers pushed on entrance Most and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb 0x20 0x20 Send EOI command to 8259A for all IRQs outportb 0x20 0xA0 Send EOI command to 8259B if using IRQ8 15 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port 520 20 Send EOI command to 8259A for all IRQs Port 0 520 Send EOI command to 8259B if using IRQ8 15 end Saving the Startup
152. t 2 2 voltage of an MOS device such as on the Am8085A CLK output without the need for a bipolar buffer Care must be taken in this bufferless circuit to choose a pull up resistor low enough to meet the Am9513 s high level voltage needs without choosing a resis tor value so low that the Am8085A has to sink excessively large currents when pulling the CLK signal low REGISTER ACCESS Information Transfer Protocols The control signal configurations for all information transfers on the Am9513 data bus are summarized in Figure 2 4 The interface control logic assumes these conventions 1 RD and WR are never active at the same time 2 RD WR and C D are ignored unless CS is Low The following discussion provides software oriented examples of Am9513 register accesses Software examples are given for an Am8085 CPU with an 8 bit Am9513 data bus interface and for an AmZ8002 CPU with a 16 bit Am9513 data bus interface The descriptions assume that Am9513 Control port CMDPRT is located at address 12 hex and the Am9513 Data port DATAPRT is located at address 10 hex Later sections of this document present complete software listings for representative Am9513 applications Software Initialization Figure 2 5 shows a Z8000 Software Initialization Sequence for the 9513 It is important to note the DUMMY LOAD COUNTER COMMAND this insures proper operation of the part The 16 bit mode command is not used for 8 bit CPUs
153. t 21H for IRQO IRQ7 or VO port A1H for IRQ8 IRQ15 Restore the interrupt vector that was saved at startup with either DOS function 25H set interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 for IRQO IRQ7 and 70H through 77H for TRQ8 IRQIS One of the most common mistakes when writing an ISR is forgetting to issue the EOI command to the appropriate 8259 interrupt controller before exiting the ISR Example Programs Included with the TC1024 is a set of example programs that demonstrate the use of many of the board s features These examples are in written in C and Pascal Also included is an easy to use menu driven diagnostics program 1024DIAG which is especially helpful when you are first checking out your board after installation C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your TC1024 board Timer Counter INTRPTS Shows how to generate interrupts and read the digital I O lines COUNT Shows how to use the Am9513A as a simple counter Digital VO DIGITAL Simple program that shows how to read and write the digital I O lines 4 12 CHAPTER 5 EXAMPLES OF Am9513A
154. t A Bidirectional Bus I O Control Signal Definition INTR Interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations _ Output Operations Output Buffer Full The output will go low to indicate that the CPU has written data out to port A Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit set reset of PCg Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of 3 136 intel 82C55A CONTROL WORD Coo 1 INPUT 0 OUTPUT PORTS 1 0 OUTPUT GROUP 8 MODE 0 MODE 0 1 MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 PERIPHERAL 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before and STB occurs before RD is permissible MASK WR 3 137 MODE 2 AND MODE 0 INPUT CONTROL WORD D D Os D D 0 Do Ll S LPs PCz0 12 INPUT 0 OUTPUT MODE
155. t C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function par lire GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Interrupt Enable Flag Alternate Port C Pin Signal Mode INTE B ACKg Output Mode 1 or STBg Input Mode 1 INTE A2 STB Input Mode 1 or Mode 2 INTE A1 Output Mode 1 or Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 3 140 intel 82C55A ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 Cto 70 C age to the device This is a stress rating only and Storage Temperature 65 C to 150 C functional operation of the device at these or any other conditions above those indicated in the Supply Voltage RN tional sections of this specification is not implied Ex Operating Voltage 4Vto 7V to absolute maximum rating conditions for Voltage on any Input GND 2Vto 6 5V extended periods may affect device reliability Voltage on any Output GND 0 5V to 0 5V Power Dissipation 1 Watt CHARACTERISTICS 0 C to 70 C 5V 10 GND OV TA 40 C to 85 for Extended Temperture TAE Train __
156. ta bus width being used and the initial Data Pointer value entered by command When E1 0 or E2 0 and G4 G2 61 point to a Counter Group the Data Pointer will proceed through the Element cycle The Element field will automatically sequence through the three val ues 00 01 and 10 starting with the value entered When the transition from 10 to 00 occurs the Group field will also be incremented by one Note that the Element field in this case does not sequence to a value of 11 The Group field circulates only within the five Counter Group codes If E2 11 and a Counter Group is selected then only the Group field is sequenced This is the Hold cycle It allows the Hold registers to be sequentially accessed while bypassing the Mode and Load registers The third type of sequencing is the Control cycle If G4 G2 G1 111 and E2 1 11 the Element Pointer will be incremented through the values 00 01 and 10 with no change to the Group Pointer When G4 G2 G1 111 and E2 E1 11 no incrementing takes place and only the Status register will be available through the Data port Note that the Status register can also always be read directly through the Control port For all of these auto sequence modes if an 8 bit data bus is used the Byte pointer will toggle after every data transfer to allow the least and most significant bytes to be transferred before the Element or Group Fields are incremented Prefetch Circuit In order
157. te an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR for IRQO IRQ7 is programmed through port 21H and the IMR for IRQ8 IRQIS is programmed through port A1H For all bits 0 IRQ unmasked enabled 1 masked disabled End of Interrupt EOI Command After an interrupt service routine is complete the appropriate 8259 interrupt controller must be notified When using IRQO IRQ7 this is done by writing the value 20H to I O port 20H only when using IRQ8 IRQ15 you must write the value 20H to I O ports 20H and What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the TC1024 the interrupt controllers check to see if interrupts are enabled for that IRQ and then check to see if other interrupts are active or requested and determine which interrupt has priority The interrupt controllers then interrupt the processor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and anew CS and IP are loaded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the inter
158. ter provide either pulses or levels The counters can be programmed to count up or down in either binary or BCD The accumulated count may be read without disturbing the counting process Any of the counters may be internally concatenated to form an effective counter length of up to 80 bits The Am9513 block diagrams Figures 1 1 1 2 and 1 3 indicate the interface signals and the basic flow of information Internal control lines and the internal data bus have been omitted The control and data registers are all connected to a common internal 16 bit bus The external bus may be 8 or 16 bits wide in the 8 bit mode the internal 16 bit information is multiplexed to the low order data bus pins DBO through DB7 An internal oscillator provides a convenient source of frequencies for use as counter inputs The oscillator s frequency is controlled at the X1 and X2 interface pins by an external reactive network such as a crystal The oscillator output is divided by the Fre quency Scaler to provide several sub frequencies One of the scaled frequencies or one of ten input signals may be selected as an input to the FOUT divider and then comes out of the chip at the FOUT interface pin The STC is addressed by the external system as two locations a Control port and Data port The Control port provides direct access to the Status and Command registers as well as allowing the user to update the Data Pointer register The Data port is used to communic
159. ters as specified by the 5 field will be disarmed and the contents of the counter will be transferred into the associated Hold registers This command is identical to issuing a DISARM command followed by a SAVE command Set TC Toggle Output C7 C6 C5 C4 C3 C2 1 1 1 0 CO 1 N Coding 001 lt N 101 Description The initial output level for TC Toggle mode is set High for counter N selected by N2 1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 1 19 but does not appear the counter output unless TC Toggle mode CM2 CM1 010 is selected Clear TC Toggle Output Coding C7 C6 C5 C4 C3 C2 C1 CO 001 N x 101 Description The initial output level for TC Toggle mode is Cleared Low for counter N selected by N4 N2 N1 001 Counter 1 thru 101 Counter 5 respectively This command conditions the TC Toggle flip flop see Figure 1 19 but does not appear atthe counter output unless TC Toggle mode CM2 CM1 CMO 010 is selected Step Counter Coding C7 Ce C5 C4 C2 CO 001 N lt 101 Description Counter N is incremented or decremented by one depending on its operating configuration If the Counter Mode register associated with the selected counter has its bit cleared to zero this command will cause the counter to decre ment by one If CM3 is set to a logic high this command will increm
160. that may be in a TC state The Data Pointer register should also be setto a legal value since reset does not initialize it A complete reset operation is given in the following 1 Using the procedure given in the Command Initiation sec tion of this document enter the FF hex command to perform a software reset Using the Command initiation procedure enter the LOAD command for all counters opcode 5F hex Using the procedure given in the Setting the Data Pointer Register section of this document set the Data Pointer to a valid code The legal Data Pointer codes are given in Figure 1 10 The Master Mode Counter Mode Load and Hold registers can now be initialized to the desired values Chapter 2 Am9513A Am9513 Interfacing 9513 CPU INTERFACING The Am9513 is designed to interface easily to both the Am8080A 8085A 8 bit family of CPUs and to the AmZ8000 16 bit family of CPUs Master Mode register bit MM13 allows the user to program the Am9513 data bus for either an 8 or 16 bit width allowing Am9513 s data bus to be tailored to match that of the host CPU Figure 2 1 shows an interface between the Am9513 and an Am8085A CPU The 9513 is configured to appear in the CPU s I O space connecting the IO M output of the CPU to the input of the decoder and tying G1 high will memory map the Am9513 In the configuration shown the Am9513 operates with an 8 bit data bus
161. ther functions Pins DB13 through DB15 should be tied high Pins DB8 through 0812 are used as auxiliary gating inputs and are labeled GATE1A through respectively The auxiliary gate pin GATENA is logically ANDed with the gate input to Counter N as shown in Figure 1 14 The output of the AND gate is then used as the gating signal for Counter N Data Pointer Sequencing Bit MM14 controls the Data Pointer logic to enable or disable the automatic sequencing functions When 14 1 the contents of the Data Pointer can be changed only directly by entering a command When 14 0 several types of automatic sequencing of the Data Pointer are available These are de scribed in the Data Pointer register section of this document GATE INPUT MULTIPLEXER AND POLARITY SELECT LOGIC Figure 1 14 Gating Control Thus the host processor by controlling MM14 may repetitively read write a single internal location or may sequentially read write groups of locations Bit MM14 can be loaded by writing to the Master Mode register or can be set or cleared by software command Scaler Ratios Master Mode bit MM15 controls the counting configuration of the Frequency Scaler counter When 15 0 the Scaler divides the oscillator frequency in binary steps so that each sub frequency is 1 16 of the preceding frequency When 15 1 the Scaler divides in BCD steps so that adjacent frequencies are related by ratios of 10 instea
162. til it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the board or to the computer 8 After the board is installed secure the slot bracket back into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer Be sure to observe the keying when connecting your external cable to I O connector External I O Connections Figure 2 1 shows the TC1024 s P3 50 pin I O connector and P4 on board 20 pin connector pinouts Refer to these diagrams as you make your I O connections SRC1 GATE1 OUTt SRC2 GATE2 OUT2 SRC3 OUT3 SRCA 4 OUT4 SRC5 GATES OUT5 EXTINT FOUT PC3 pci PB7 12 VOLTS 12 VOLTS a e e 6 62 69 e a G9 a 69 O O Sl G3 5106 GATE6 OUT6 SRC7 50 Pin SRC8 GATES SRC9 GATE9 OUT9 SRC10 GATE10 OUT10 DIGITAL GND DIGITAL GND PC2 PCO PB6 4 5 VOLTS DIGITAL GND 4 20 Pin 5 VOLTS DIGITAL GND Fig 2 1 Connector and On board Connector Pin Assignments Connecting the Timer Counters and Digital VO For all of these connections the high side of an external
163. ting will not begin until a Gate edge is applied to an armed counter The counter must be armed before application of the triggering Gate edge Gate edges applied to a disarmed counter are disregarded An armed counter will start counting on the first source edge after the triggering Gate edge Counting will then proceed in the same manner as in Mode G Afterthe second TC the counter will disarm itself An ARM command and Gate edge must be issued in this order to restart counting Note that after application of a triggering Gate edge the Gate input will be disregarded until the second TC This differs from Mode where the Gate can be modulated throughout the count cycle to stop and start the counter ne w EUM SS RA OUTPUT Te TOGGLED UI WR ARM COMMAND y Na A BEER Qe cem MOS 595 Figure 1 17h Mode H Waveforms AAA AAA COUNT X VALUE Ped 54 2 TC OUTPUT TC TOGGLED OUTPUT WR ARM COMMAND MOS 596 Figure 1 17i Mode 1 Waveforms 1 16 NAAA A P MODE J Variable Duty Cycle Rate Generator with No Hardware Gating opo ped xc een Mode J shown in Figure 1 17 will find the greatest usage in frequency generation applications with variable duty cycle re quirements Once ar
164. tion configuration Note that the count sequence gen erated never has 0 in the upper counter disregarding the special case where L 0 This means that the value stored in the high order counter should be biased by adding 1 in order to generate the correct divider ratio For example to divide by 39264178 BCD the high order counter s Load register should be set to 3926 1 3927 andthe low order counter s Hold register should be set to 4176 The low order counter s Load register should be set to 0 to ensure proper count value rollover Also note the unusual count sequence on the TC before the low order counter reloads from the Load register For the above example of dividing by 39264178 the counters will count 00010002 00010001 00010000 39279999 39279998 39270002 39270001 39274178 39264177 39264176 39264175 rather than 00010002 00010001 00010000 39274178 39274177 39270002 39270001 39270000 39269999 39269998 39269997 In some applications it may be desirable to level or edge gate with down concatenation Because the low order counter uses the gate to select the reload source the gate input cannot be used to start and stop counting in the low order counter Accordingly external gating logic must be used Figure 3 8 shows the connec tions required for count down concatenations with level gating Level gating is achieved by inhibiting source pulses when the gate goes inactive Edge gating shown in
165. tion of this document for elaboration _ Establish a Low on the C D input Establish a Low on the CS input Establish a Low on RD after waiting for the appropriate CS and C D setup time see Timing Diagram Sometime after RD goes Low the register contents will ap pear on the data bus In both 8 and 16 bit bus modes the low register byte will appear on DBO DB7 In addition in 16 bit bus mode the upper register byte will appear on the 088 0815 For 8 bit bus mode pins DB8 DB15 are not driven by the 9513 gt 0115 10810 0117 6 0118 I B1O 0118 67 This information will remain stable as long as RD is Low Ifthe register value is changed during the read the change will not be reflected by a change in the data being read for the reasons outlined in the Prefetch Circuit section of this document RD can driven High to conclude the read operation after meeting the minimum RD pulse duration CS and C D can change after meeting appropriate hold time requirements see Timing Diagram After waiting the minimum read recovery time see Timing Diagram a new read or write operation can be started For 8 bit bus mode steps 2 through 7 should be repeated to read out the high register byte on DBO DB7 If the Status register is being read in 8 bit mode the two reads will return the Status register each time In 16 bit mode reads from the Status register return undefined data on DB8 DB15 The user
166. to the items included in your TC1024 package Real Time Devices offers a full line of board accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Accessories for the TC1024 include the TB50 terminal board and XB50 prototype terminal board for prototype development and easy signal access and XT50 twisted pair wire flat ribbon cable assembly for external interfacing i 3 Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition and control principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board contact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your tel
167. tput on the associated OUT1 or OUT2 pin The comparator output will be active high if the output control field of the Counter Mode register is 001 or 010 and active low for a code of 101 Once the compare outputis true it will remain so until the count changes and the comparison therefore goes false The two Comparators can always be used individually in any operating mode One special case occurs when the Time of Day option is invoked and both Comparators are enabled The opera tion of Comparator 2 will then be conditioned by Comparator 1 so that a full 32 bit compare must be true in order to generate a true signal on OUT2 OUT1 will continue as usual to reflect the state of the 16 bit comparison between Alarm 1 and Counter 1 FOUT Source Master Mode bits MM4 through MM7 specify the source input for the FOUT divider Fifteen inputs are available for selection and they include the five Source pins the five Gate pins and the five internal frequencies derived from the oscillator The 16th combi nation of the four control bits all zeros is used to assure that an active frequency is available at the input to the FOUT divider following reset FOUT Divider Bits MM8 through MM11 specify the dividing ratio for the FOUT Divider The FOUT source selected by bits MM4 through is divided by an integer value between 1 and 16 inclusive and is then passed to the FOUT output buffer After power on or reset the FOUT divider is set to divide
168. trigger or as counter initialization prior to active hardware gating The DISARM command disables further counting independent of any hardware gating A disarmed counter may be reloaded using the LOAD command may be incremented or decremented using the STEP command and may be read using the SAVE command A count process may be resumed using an ARM command The SAVE command transfers the contents of a counter to its associated Hold register This command will overwrite any previ ous Hold register contents The SAVE command is designed to allow an accumulated count to be preserved so that it can be read by the host CPU at some later time Two combinations of the basic commands exist to either LOAD AND ARM or to DISARM AND SAVE any combination of count ers Additional commands are provided to step an individual counter by one count set and clear an output toggle issue a software reset clear and set special bits in the Master Mode register and load the Data Pointer register Note Separate LOAD and ARM commands should be used for asynchronous operations INTERFACE SIGNAL DESCRIPTION Figure 1 5 summarizes the interface signals and their abbrevia tions for the STC Figure 1 4 shows the signal pin assignments for the standard 40 pin dual in line package 5 volt power supply VSS Ground X1 X2 Crystal X1 and X2 are the connections for an external crystal used to determine the frequency of the internal oscillator The c
169. u of the software commands Reading the Status Register The Am9513 Status register can be read either through the Control port or through the Data port Figure 2 8 shows sample programs reading the Status register contents through the Control port into the accumulator A register of an Am8080A 8085A system or the RO register of an AmZ8002 system It is assumed that the AmZ8002 system has a 16 bit data bus since the status register is only eight bits wide the high byte of register RO is undefined The procedure for reading the Status register through the Control port is given in the following 1 Establish a High on the C D input 2 Establish a Low on the CS input 3 After the appropriate CS and C D setup time see Timing Diagram make RD Low Sometime after RD goes Low the Status register contents will appear on the data bus These lines will contain the informa tion as long as RD is Low If the state of an OUT pin changes while RD is Low this will be reflected by a change in the information on the data bus RD can be driven High to conclude the read operation after meeting the minimum RD pulse duration CS and C D can change after meeting the appropriate hold time requirements see Timing Diagram A new read or write operation to the Am9513 should not be attempted until the read recovery time is met see Timing Dia gram in Electrical Specification 4 CODE TO READ STATUS REGISTER CMDPRT 8080 Co
170. unter to continue counting until the high order counter reaches TC Figure 3 3 shows one method of concatenating counters for edge triggered up counting This method operates the counters in a similar arrangement to that used for level gating with the requirement that each counters output be programmed for an active high TC pulse The external flip flop is set by an external synchronous gate signal When both counters reach TC the flip flop is cleared One potential problem exists with this scheme Once the flip flop clears it will inhibit the low order counter s gate input The low order counter will nevertheless count the next source edge driving itself out of TC However the high order counter will remain in TC When the next triggering gate edge is applied the flip flop will set allowing counting to begin When the low counter reaches its first TC the rising TC edge will cause the high counter to leave TC For a short period of time the propagation delay of the high order counter from source to output both TCs will again be active This could potentially clear the flip flop prematurely To inhibit this the source signal is added as an additional inputto the NAND gate If a relatively siow source is used with a high time greater than the total propagation delay from the source input of low order counter to the output of the high order counter the source input on the NAND gate will inhibit clearing of the flip flop during this trans
171. will clear inhibiting further counting To restart the counter in this configuration the Set Counter 2 output command should be issued and a new gate edge should be applied in the order As in the previous cases the applied gate edge should be synchronous to the Counter 1 source In order to analyze down concatenation it is useful to separately analyze the sequences followed for the high order and low order counters Figure 3 5 shows a typical count down concatenation HIGH ORDER COUNTER TC OUTPUT LOW ORDER COUNTER TC OUTPUT sequence with the high order and low order count sequences labelled The high order counter simply decrements from some initial value L until TC is reached In the following discussion and figures L and H are used to represent the Load and Hold register contents respectively K and N are used to represent arbitrary count values is then reloaded with L and repeats the se quence Note that the high order counter in general will never count to 0 since TC is generated by the source edge occurring while the counter contains 1 and TC reloads the initial value L The count sequence is thus L L 1 2 1 L L7 1 L72 2 1 L The low order counter starts from some initial value H and counts down to TC This TC output will be used to decrement the high order counter by 1 The low order counter is now reloaded with O and counts down through assuming BCD counting 9999 to 1 This sequence of
172. y the falling edge of 0204 WR INTE A Controlled by bit set reset of INTE B Controlled by bit set reset of PC 231256 16 Figure 11 MODE 1 Strobed Output 3 135 82C55A Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed applications CONTROL WORD D De Ds D Dj D3 O D tjr jer o DG z o 0 OUTPUT WR 0 PORT A STROBED INPUT PORT B STROBED OUTPUT CONTROL WORD Dz De Ds D D 0 D Do BOGOR PC s 1 INPUT 0 OUTPUT Rb PORT A STROBED OUTPUT PORT STROBED INPUT 231856 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group only One 8 bit bi directional bus port Port A and 5 bit control port Port Both inputs and outputs latched The 5 bit control port Port is used for control and status for the 8 bit bi directional bus port Por

TC1024 Userts Manual - RTD Embedded Technologies, Inc.

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