KLI-4104 Image Sensor Evaluation Timing Specification
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1. P TG LINE LINE LINE LINE TG INITIALIZE TRANSFER TRANSFER TRANSFER TRANSFER INCREMENT TRANSFER Integration INT_LINES 3 TGperiod PIXX PIXX 1 TGperiod Figure 9 PCI 1424 Frame Grabber Timing Multi Line Integration Mode TGperiod PIX_X i TGperiod i tgd tipd Thd Me Figure 10 AD9845 Timing www onsemi com 12 EVBUM2283 D WARNINGS AND ADVISORIES When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of a Truesense Imaging Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by Truesense Imaging Changes to the firmware are at the risk of the customer ORDERING INFORMATION Please address all inquiries and purchase orders to Truesense Imaging Inc 1964 Lake Avenue ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to Rochester New York 14615 be accurate Phone 585 784 5500 E mail info truesenseimaging com REFERENCES 1 KLI 4104 Device Specification 5 AD984X Timing Generator Board Schematic 2 KLI 4104 Imager Board U2. 52 20 E S A e e EN RC a 40 646 85 00 190 3046 29 30 50 806 81 30 200 3206 25 60 60 966 77 60 210 3366 21 80 www onsemi com EVBUM2283 D Table 10 LOGX PULSEWIDTHS SELECTED VALUES SINGLE LINE INTEGRATION MODE Register Value Pixels Percent Register Value Pixels Percent 0 100 00 120 1926 55 30 86 98 00 150 2431 43 50 166 96 10 160 2591 39 70 DC A a ES NE MN UE 90 1446 66 40 240 3871 10 00 110 1766 59 00 255 4111 4 40 PIXEL RATE CLOCKS GENERATION The pixel rate clocks are derived from the System Clock 3 The inverse of the PIXEL_CLK signal occurs For 30 MHz operation they operate at 1 2 the frequency of 50 percent later than the PIXEL_CLK signal the 60 MHz System Clock The PIXEL_CLK signal is 4 The inverse of the DELAYED_PIX_CLK signal generated from the rising edge of the system clock occurs 75 percent later than the PIXEL_CLK The DELAYED _PIX_CLK signal is generated from the signal falling edge of the System Clock By utilizing both edges of the System Clock four start positions for the pixel rate clocks are achieved 1 The PIXEL_CLK signal 2 The DELAYED_PIX_CLK signal occurs 25 percent later than the PIXEL_CLK signal One of these four signals is chosen to be the input signal source for a particular pixel rate signal and then the position of the signal is optimized using a programmable delay line IC For 30 MHz operation the pixel rate clocks are deriv
3. independent exposure control of each Chroma channel If a non zero value is programmed into a LOGx_STOP register the LOGx pulse will go HIGH on the falling edge of TG2C In Multi Line Integration Mode the LOGx pulse will remain HIGH for 6 pixel periods before the Hclks begin plus 16 pixel periods for each count in the register The range of the 8 bit register data is 0 to 255 so the LOGx pulsewidth can be from 0 to 4086 pixel periods See Figure 5 Table 9 and Table 13 If Multi Line integration is off the Horizontal clocks are suspended during the Luma mid line transfer and the LOGx pulse will therefore be lengthened by the same amount TGperiod if the LOGx register value is greater than 129 See Figure 6 and Table 10 Multi Line Integration Mode The Multi Line Integration mode is controlled by programming a value greater than into the INT_LINES register Each count in this register represents one line of integration time with a minimum of 1 line time of integration Values of 0 and 1 are equivalent except that a value of 0 enables the Luma midline transfer thereby increasing the total line length by TGperiod The range of the 8 bit register is 0 to 255 so integration may be programmed up to 255 line times See Figure 8 Figure 9 and Table 13 Table 9 LOGX PULSEWIDTHS SELECTED VALUES MULTI LINE INTEGRATION MODE Register Value Pixels Percent Register Value Pixels o o o PE AS NS Exposure Percent 55 30
4. the desired integration time has been achieved transported from the photodiodes to the Horizontal CCDs the state machine will enter the LINE_INCREMENT state If Exposure Control Mode is selected for any channel in which the Line Counter is incremented If TF lines have LOGx where x L R G or B will go HIGH as TG2 goes been clocked out of the CCD See Table 5 the state LOW Integration begins on the falling edge of TG2 or the machine proceeds to the CLEAR SETUP state if not www onsemi com 9 EVBUM2283 D the state machine returns to the TG_TRANSFER state and transfers another line of charge into the horizontal register TGL_MIDLINE State The entire KLI 4104 Luma photodiode array contains twice the number of active pixels in each Chroma array but because there are four Luma output channels each of the Luma channels has half the number of active pixels of a Chroma channel Therefore two lines may be read from the Luma channels for every line read from the Chroma channels thus achieving twice the resolution in both the vertical and horizontal dimensions See the KLI 4104 Device Performance Specifications References for details GENERATOR ae STATE SETUP TG_TRANSFER MACHINE INITIALIZE PIXEL COUNTS TIMING GENERATOR STATE MACHINE TG1C TG2C TG2L LOGx H1_CLK H2_CLK PIXEL i Figure 6 Line Timing Single Line Integration Mode In Single Line Integration Mode the charge in the Luma phot
5. EVBUM2283 D KLI 4104 Image Sensor Evaluation Timing Specification Altera Code Version Description The Altera code Firmware version 2 5 described in this document is intended for use in the AD984X Timing Board The code is written specifically for use with the following system configuration Table 1 SYSTEM CONFIGURATION ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL Evaluation Board Kit PN 4H0349 Timing Generator Board 3E8180 AD9845A 12 bit 30 MHz KLI 4104 Imager Board 3E8218 National Instruments Model PCI 1424 Framegrabber Board ALTERA CODE FEATURES FUNCTIONS The Altera Programmable Logic Device PLD has four major functions Timing Generator The PLD serves as a state machine based timing generator whose outputs interface to the KLI 4104 the AD9845A Analog Front End AFE and the PCI 1424 Framegrabber When powered on the video outputs are always in free running mode The behavior of these output signals is dependent upon the current state of the state machine External digital inputs as well as jumpers on the board can be used to set the conditions of certain state transitions See Table 2 In this manner the board may be run using any of the following features Optical Black Clamp Mode e Programmable Electronic Exposure Control Programmable Multi line Integration Semiconductor Components Industries LLC 2014 November 2014 Rev 2 Delay Line In
6. ITIALIZE States falling edge of LOGx if Exposure Control is being used See The timing generator state machine is free running at all Figure 5 times It cycles through the states depending on the jumper settings and DIO inputs and then returns back to the LINE_TRANSFER and LINE_INCREMENT States clear setup state to begin the next frame The clear setup During the LINE_TRANSFER state charge is state is used to reset the internal PLD counters at the transported to the CCD output structure pixel by pixel beginning of each frame A line transfer counter in the PLD is used to keep track of The INITIALIZE state is used to determine the selected how many pixels have been transported and to synchronize operating modes and to synchronize with the the AD9845A timing signals and the PCI 1424 timing INTEGRATE_CLK as needed The values of the JMP 3 0 signals with the appropriate pixels dark pixels for black jumpers and the programmable registers are read and are clamping for example used to determine the timing signals for the subsequent At the end of each line transfer the Multi Line counter is flame checked If Multi Line Integration Mode has been selected by entering a value greater than 1 in the INT_LINES TG_TRANSFER Siate register the CCD will be integrated for that number of line During the TG_TRANSFER state the TG1C TG2C and times without clocking TG1C and TG2x See Figure 9 TG2L clocks are brought to the high level and charge is When
7. K 16 PIXEL CLK RESET CLOCK INVERTED PIXEL CLK 14 00 15 50 18 50 17 00 12 00 11 00 www onsemi com 8 EVBUM2283 D AFE Register Initialization On power up or board reset the AFE registers are programmed to the default levels shown in Table 12 See the AD9845A specifications sheet References for details Table 12 DEFAULT AD9845A AFE REGISTER PROGRAMMING SS DS DS VGA Gain Corresponds to a VGA Stage Gain of 6 0 dB 2 Clamp The Output of the AD9845A will be Clamped to Code 96 during the CLPOB Period CDS Gain Corresponds to a CDS Stage Gain of 0 0 dB Programmable Register Initialization There are five 8 bit programmable registers used to At the end of the AFE Register Initialization the registers control the Multi line integration mode and the electronic are automatically initialized to the default values listed in exposure control LOG These registers are programmed in Table 13 The LOGx_STOP registers adjust the Electronic parallel through the DIO interface DIO 2 0 specify the Exposure controls in 16 pixel increments The INT_LINES register address DIO 10 3 specify the 8 bits of data and register adjusts the Multi line Integration in 1 line DIO11 is the WRITE strobe used to latch the data The data increments values range from 0 to 255 decimal Table 13 DEFAULT PROGRAMMABLE REGISTER PROGRAMMING Register Address Value Decimal DIO 2 0 Description DIO 10 3 CLEAR SETUP and IN
8. LTERA OUTPUTS continued Serial Clock AD9845A Delay Line IC s Not Used for KLI 4104 Operation KLI 4104 TIMING CONDITIONS System Timing Conditions Table 4 SYSTEM TIMING System Clock Period 16 67 ns 60 MHz System Clock Power Stable Delay Tpwr 30 ms Typical Default Serial Load Time Tsload 112 5 us Typical CCD Timing Conditions Table 5 CCD TIMING Pixel Time Description Symbol Counts 30 MHz Notes H1 H1L H2 RESET Period Tpix 1 0 033 us 30 MHz Clocking of H1 H2 RESET TGCCD Delay Ttgd 2 0 07 us NAME HCCD Delay TG2 Clear Thd ttg2 Vertical Transfer Period TGperiod 21 Pix per Line Single Output Tline 4300 RESET Clock Pulse Width Tr www onsemi com 3 EVBUM2283 D AFE Timing Conditions Table 6 AFE TIMING Pixel Time Description Symbol Counts 30 MHz Notes SHP SHD DATACLK Period Tpix 1 0 033 us 30 MHz Clocking of SHP SHD DATACLK SHP Pulse Width Tshp 7 5 ns Tshp is Set by Hardware on Timing Board CLPOB Line Start CLPOB_Is 4190 Line Transfer Counter CLPOB Mode 1 Only CLPOB Line End CLPOB_le 4210 Line Transfer Counter CLPOB Mode 1 Only CLPDM End Pixel CLPDM_pe 4180 I Horizontal Transfer Counter C pats aaa caer p paukena Piet Pate Vera rartorGauner PCI 1424 Timing Conditions CLPDM Start Pixel Table 7 PCI 1424 TIMING Pixel Time Description Symbol Counts 30 MHz PIX Period eet 0 033 us 30 MHz Clocking of PIX Sync
9. Signal LINE Time 4324 144 10 us Single Line Integration Mode Tframe TLine TF TGperiod TF 1 MODES OF OPERATION The 3E8218 Imager Board has seven video output channels to accommodate the Red Green Blue LAO LAE LBO and LBE outputs of the KLI 4104 Any two of these outputs may be connected to the 3E8180 Timing Generator Board at one time using the supplied coaxial cables Black Clamp Mode One of the features of the AD9845A AFE chip is an optical black clamp The black clamp CLPOB is asserted Table 8 OUTPUT MODE JUMPER SETTINGS during the CCD s dark pixels and is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD s black level This feature may be enabled or disabled by setting JMP1 See Table 8 JMP1 Operating Mode LOW CLPOB Mode Enabled HIGH CLPOB Mode Disabled Programmable Operational Modes Several operational modes are selected by programming registers in the Altera PLD using the Discrete Input bits DIO 11 0 DIO11 is the WRITE strobe to the registers its rising edge latches data from DIO 10 3 to the register address in DIO 2 0 The WRITE strobe timing requirements are summarized in Figure 1 www onsemi com EVBUM2283 D wss AN ADDRESS VALD XK WW pata LK CD K DIO11 WRITE tsy 10ns min x S t 2ns min 1 Figure 1 Programmable Register Timing Exposure Control Mode The LOGx inputs to the CCD allow
10. ation please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2283 D
11. ed as shown in Figure 2 SYSTEM CLOCK PIXEL CLOCK i i INVERTED i PIXEL CLOCK i DELAYED PIXEL CLOCK INVERTED DELAYED PIXELCLOCK PIXEL PERIOD Figure 2 30 MHz Pixel Clock Generation Timing www onsemi com 6 EVBUM2283 D TIMING GENERATOR STATE MACHINE DESCRIPTION The Timing Generator State Machine is Free Running at all times The sequence of states is shown in Figure 3 POWER_ON BOARD RESET INITIALIZE TG_TRANSFER LINE_TRANSFER TGL_MIDLINE MIDLINE START ULTI LIN INTEGRATION DONE LINE_INCREMENT Figure 3 Timing Generator State Machine Power On Board Reset State When the board is powered up or the Board Reset button and then serially load the initial default values into the AFE is pressed the Altera PLD is internally reset When this registers Upon completion of the serial load of the AFE occurs state machines in the PLD will first serially load the the board will be ready to proceed according to the output initial default values into the ten delay line IC s on the board mode selected www onsemi com 7 EVBUM2283 D TIMING GENERATOR STATE MACHINE DEFAULT DELAY DEFAULT 2 ne AFE WAIT a POWER ON BOARD RESET CLEAR SETUP INITIALIZE a a oe ALL DONE SCLOCK SDATA SLOAD CH1 SLOAD Tsload CH2 SLOAD Figure 4 Power On Initialization Timing Delay Register Initialization The DS1020 Programmable Silicon De
12. itialization Upon power up or when the BOARD_RESET button is depressed the PLD programs the 10 silicon delay IC s on the Timing Generator Board to their default delay settings via a 3 wire serial interface See Table 11 for details AFE Register Initialization Upon power up or when the BOARD_RESET button is depressed the PLD programs the registers of the two AFE chips on the Timing Generator Board to their default settings via a 3 wire serial interface See Table 12 for details Programmable Register Initialization Upon power up or when the BOARD_RESET button is depressed the PLD initializes the programmable registers within the Altera PLD to their default settings See Table 13 for details Publication Order Number EVBUM2283 D EVBUM2283 D ALTERA CODE I O Inputs Table 2 ALTERA INPUTS POWER_ON_DELAY The Rising Edge of This Signal Clears and Re initializes the PLD SYSTEM_CLK 60 MHz Clock 2X the Pixel Clock Rate INTEGRATE_CLK Integration Clock 1 ms Asynchronous Clock used for Power up Delay JMPO Not Used for KLI 4104 Operation JMP1 Optical Black Mode Select CLPOB HIGH Disable CLPOB Outputs Table 3 ALTERA OUTPUTS Not Used for KLI 4104 Operation LOG_RED LOG Red Clock LOG_LUMA LOG Luma Clock SHP AD9845A Clamp CCD Reset Level S HD PCI 1424 Frame Grabber Line Rate Synchronization www onsemi com 2 AD9845A Sample CCD Data Level EVBUM2283 D Table 3 A
13. lay Lines allow the Horizontal Clocks Reset Clock Clamp Sample and Data Clock signals to be adjusted within the sub pixel timing On Power Up or Board Reset the delay lines are programmed with values stored in the Altera device These values are chosen to comply with the timing requirements of the CCD image sensor See References for details The delay values shown in Table 11 are typical values and may vary on an individual Evaluation Board set For programming purposes the silicon delay lines are cascaded i e the serial output pin of device 1 is tied to the Table 11 DEFAULT DALEY IC PROGRAMMING Delay IC Output Programming Order Signal CH2 AD9845A SHP Delay IC Input Signal Source serial input pin of device 2 and so on Therefore when making an adjustment to one or more delay lines all the delay lines must be reprogrammed The total number of serial bits must be eight times the number of units daisy chained and each group of 8 bits must be sent in MSB to LSB order The total delay on each output signal is calculated as Delay 10 0 0 25 Delay Code ns eq 1 Refer to the Dallas Semiconductor DS1020 Programmable Silicon Delay Line Specification Sheet References for details Delay Code Delay ns Typical Typical AD9845A DATACLK PIXEL CLK 20 50 2 PIXEL CLK 28 17 00 CH1 AD9845A SHP PIXEL CLK 24 16 00 CH2 AD9845A SHD Not Used 1 2 3 4 5 7 0 INVERTED PIXEL CL
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15. odiodes is transferred during the TG_TRANSFER state and again during the TGL_MIDLINE state When the horizontal counter reaches TG2L_MIDLINE_START See Table 5 the Horizontal clocks are suspended and the TG2L clock is activated to transport charge to the Luma Horizontal CCDs The timing of this state is identical to the TG_TRANSFER state except that TG1C and TG2C are not clocked Following the TGL_MIDLINE state the LINE_ TRANSFER state resumes and a new Luma line is read out along with the remaining Chroma line See Figure 6 LINE_TRANSFER www onsemi com CLOCKING STATE MACHINE VOUT_CCD RESET_CCD H2_CCD H1_CCD SHP SHD DATACLK PIX TIMING GENERATOR STATE MACHINE TG1C_CLK TG2C_CLK TG2L_CLK FRAME LINE PIX PIXEL COUNTS EVBUM2283 D TG_TRANSFER LINE TRANSFER Vpix Vsat gt Tpx lt i gt lt Tshp i i gt lt lt Tshd Figure 7 Horizontal Timing Line Transfer TG_TRANSFER TG_TRANSFER LINE TRANSFER TGL_MIDLINE LINE TRANSFER TGperiod lt 1 PIX_X TGperiod Figure 8 PCI 1424 Frame Grabber Timing Single Line Integration Mode TGperiod ttgd tod Thd www onsemi com 11 TIMING GENERATOR STATE MACHINE TG1_CLK TG2_CLK FRAME LINE PIX PIXEL COUNTS TIMING GENERATOR STATE MACHINE TG1_CLK TG2_CLK PBLK CLPDM CLPOB SHP SHD DATACLK PIXEL COUNTS EVBUM2283 D
16. ser Manual 6 Analog Devices AD9845 Product Data Sheet 3 KLI 4104 Imager Board Schematic 28 and 30 MHz operation 4 AD984X Timing Generator Board User Manual ON Semiconductor and the are registered trademarks of Semiconductor Components Industries LLC SCILLC or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in syste
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