Home

XUP Virtex-II Pro User Guide

Contents

1. NET AC97 SDATA OUT LOC E8 NET AC97 SDATA IN LOC 9 NET AC97 SYNCH LOC F7 NET AC97 BIT CLOCK LOC F8 NET AUDIO RESET Z LOC E6 NET BEEP TONE IN LOC 7 NET AC97 SDATA OUT IOSTANDARD LVTTL NET AC97 SDATA IN IOSTANDARD LVTTL NET AC97 SYNCH IOSTANDARD LVTTL NET 97 BIT CLOCK IOSTANDARD LVTTL NET AUDIO RESET Z IOSTANDARD LVTTL NET BEEP TONE IN IOSTANDARD LVTTL NET AC97 SDATA OUT DRIVE 8 NET AC97 SYNCH DRIVE 8 NET AUDIO RESET Z DRIVE 8 NET BEEP TONE IN DRIVE 8 NET AC97 SDATA OUT SLEW SLOW NET AC97 SYNCH SLEW SLOW NET AUDIO RESET Z SLEW SLOW NET BEEP TONE IN SLEW SLOW Virtex ll Pro Development System www xilinx com 115 UG069 v1 0 March 8 2005 1 800 255 7778 7 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE CLOCKING SECTION OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 DEFINE THE CLOCKS FOR THE MGTS MGT CLK P LOC F16 MGT CLK N LOC G16 NET EXTERNAL CLOCK P LOC 015 NET EXTERNAL CLOCK N LOC 15 NET MGT CLK P IO
2. Signal Direction MICH Bin jd Type SDRAM DQ 33 I O 55 Y30 SSTL2 II SDRAM DO 34 I O 57 U24 SSTL2 II SDRAM DOQ 35 I O 60 U23 SSTL2 II SDRAM DO 36 I O 146 V26 SSTL2 II SDRAM DQI 37 I O 147 V25 SSTL2 II SDRAM DO 38 I O 150 Y29 SSTL2 II SDRAM DO 39 I O 151 AA29 SSTL2 II SDRAM DOS 4 I O 56 V23 SSTL2 II SDRAM DM 4 0 149 W28 SSTL2 II SDRAM DO 40 I O 61 Y26 SSTL2 II SDRAM DOQ 41 I O 64 AA28 SSTL2 II SDRAM DQI 42 I O 68 AA27 SSTL2 II SDRAM DOQI 43 I O 69 W24 SSTL2 II SDRAM DOI 44 I O 153 W23 SSTL2 II SDRAM DOQI 45 I O 155 AB28 SSTL2 II SDRAM DOI 46 I O 161 AB27 SSTL2 II SDRAM DQJ 47 I O 162 AC29 SSTL2 II SDRAM DOS 5 I O 67 AA25 SSTL2 II SDRAM DMI 5 0 159 W27 SSTL2 II SDRAM DOI 48 I O 72 AB25 SSTL2 II SDRAM DOI 49 I O 73 AE29 SSTL2 II SDRAM DO 50 I O 79 AA24 SSTL2 II SDRAM DO 51 I O 80 AA23 SSTL2 II SDRAM DOQ 52 I O 165 AD28 SSTL2 II SDRAM DQ 53 I O 166 AD27 SSTL2 II SDRAM DO 54 I O 170 AF30 SSTL2 II SDRAM DOQ 55 I O 171 AF29 SSTL2 II SDRAM DOS 6 I O 78 AC25 SSTL2 II SDRAM DM 6 0 169 W26 SSTL2 II ISDRAM WO 83 A 56124 SDRAM DQI 57 I O 84 AG30 SSTL2 II 32 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the DIMM Module DDR SDRAM Table 2 5 DDR SDRAM Connections Continued XILINX
3. 1 106 Additional Hardware Required 106 EMAC Web Server Test 106 AC07 Audio a E Y aw V DREN 109 Additional Hardware Required 109 Digital Passthrough Test 109 FIFO Loopback Test 110 Game Sounds Test 110 System ACE T6SE creati rud eio e Ret D 111 System ACE Test 111 DDRSDRAM Test o RR Re Ree e e e Ee RU E es 112 Additional Hardware Required 112 Test Procedure 22 Rat dra E d s eg ace d 112 Expansion Port peek cag aza ex eR S e ted kane l t aa 113 Additional Hardware Required 113 DE be Bek be 113 Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 Appendix E User Constraint Files Appendix F Links to the Component Data Sheets FPGA Related 137 Configuration Sources 5
4. Table 2 11 Upper Middle Expansion Header Pinout Continued Pin Signal ii ExPp OType 43 EXP IO 36 01 5 32 LVTTL 45 EXP IO 37 V1 5 33 LVTTL 47 EXP IO 38 T5 J5 34 LVTTL 49 EXP IO 39 T6 5 35 LVTTL 51 VCC3V3 15 3 6 3 53 VCC3V3 75 3 6 3 55 J5 3 J6 3 57 VCC5VO 15 2 16 2 59 VCC5VO 5 2 16 2 2 GND J5 1 J6 1 2 4 GND J5 1J6 1 6 GND J5 1 161 8 GND a 5 1 6 1 10 GND J5 1 J6 1 12 J5 1 J6 1 2 14 J5 1 J6 1 16 J5 1 J6 1 18 J5 1 J6 1 20 GND J5 1 J6 1 22 GND J5 1 J6 1 24 GND J5 1J6 1 26 GND 5 J5 1 J6 1 28 GND J5 1 J6 1 30 GND J5 1 J6 1 32 GND J5 1 J6 1 z 34 GND J5 1J6 1 36 GND J5 1 J6 1 38 GND J5 1 J6 1 40 GND J5 1 J6 1 2 42 J5 1J6 1 5 44 5 J5 1 J6 1 E www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 Using the Expansion Headers and Digilent Expansion Connectors 5 XILINX Table 2 11 Upper Middle Expansion Header Pinout Continued Pin Signa Pin EXP pin OType 46 GND J5 1J6 1 e 48 GND 5 J5 1 J6 1 50 GND J5 1J6 1 52 GND J5 1J6 1 a 54 GND J5 1J6 1 56 GND J5 1 J6 1 58 GND J5 1 J6 1 60 GND J5 1 J6 1 Table 2 12 Lower Middle Expansion Hea
5. 82 Figure B 10 Switching to Configuration Mode 82 Figure B 11 Initializing the JTAG 83 Figure B 12 Assigning the MCS File to the 83 Figure B 13 Programming the 84 Figure B 14 PROM Programming 85 Figure B 15 iMPACT PROM Programming Transcript Window 85 Appendix C Restoring the Golden FPGA Configuration Figure C 1 Operation Mode Selection Configure Devices 88 Figure C 2 Selecting Boundary Scan 89 Figure C 3 Boundary Scan Mode Selection Automatically Connect to the Cable and Identify the JTAG Chain 90 Figure 4 Assigning New PROM Configuration 91 Figure C 5 Erasing the Existing PROM Contents 92 Figure C 6 Transcript Window for the Erase Command 92 Figure C 7 Selecting the Program 93 Figure C 8 PROM Programming 94 Figure 9 1 PROM Programming Transcript Window 95 Appendix D Using the Golden FPGA Configuration
6. Pixel DCM Verilog Horizontal Timing Parameters S Clock Settings H Active HSynch HBP H Total MHz M D Pixels Pixels Pixels Pixels Pixels 800 x 600 75 Hz 50 00 1 2 600 1 2 23 626 800 x 600 85 Hz 55 00 11 20 600 1 3 18 622 1024 x 768 60 Hz 65 00 13 20 768 3 6 DU 806 1024 x 768 72 Hz 75 00 15 20 768 1 3 24 796 1024 768 75 Hz 80 00 8 10 768 2 4 29 803 1024 x 768 85 Hz 95 00 19 20 768 2 4 38 812 1280 x 1024 60 Hz 110 00 11 10 1024 3 5 42 1074 1280 x 1024 72 Hz 130 00 13 10 1024 2 4 40 1070 1280 x 1024 9 75 Hz 135 00 27 20 1024 1 3 38 1066 1280 1024 85 Hz 150 00 3 2 1024 1 3 28 1056 1200 x 1600 60 Hz 160 00 16 10 1200 1 3 40 1244 1200 x 1600 70 Hz 180 00 18 10 1200 1 3 38 1242 The connections between the FPGA and the XSGA output DAC and connector are listed in Table 2 7 along with the required I O characteristics Table 2 7 XSGA Output Connections hips FPGA Signal Direction DAC or Output Pin Type Drive Slew Connector Pin VGA OUT RED 0 40 G8 LVTTL 8mA SLOW VGA RED 1 41 9 LVTTL 8mA SLOW VGA OUT RED 2 42 G9 LVTTL 8mA SLOW VGA OUT RED 3 43 9 LVTTL 8mA SLOW VGA OUT RED 4 44 10 LVTTL 8mA SLOW VGA RED 5 45 D7 LVTTL 8mA SLOW VGA OUT RED 6 46 7 LVTTL 8mA SLOW VGA OUT RED 7 47 10 8mA SL
7. EDK PLB DDR SDRAM Controller CORE _ _ _ DDR Clock Signal I O Configuration Clocking DQS DDR I O Configuration amp Clocking Output Enable DDR Clock 0 1 2 DOS SYS n s SYS s DQ I O Control signal RAS CAS DM CSn DDR I O Configuration amp Clocking SYS Clk n s SYS 5 SYS n s SYS Ck n s ug069 23 021505 Figure 2 10 Clock Generation for the DDR SDRAM Virtex ll Pro Development System www xilinx com 29 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Xilinx has qualified several different types of PC2100 memory modules for use in the XUP Virtex II Pro Development System These modules cover various densities organizations and features The qualified memory modules are identified in Table 2 4 For an updated list of supported modules consult the XUP Virtex II Pro Development System support Web site at http www xilinx com univ xupv2p html The data bus width number of ranks address range clock latency and output type are all parameters that are used by the DDR memory controller design to create the correct memory controller for the user application Table 2 4 Qualified SDRAM Memory Modules Crucial amp Technology Memory Number of Unbuffered or CAS Part Number Organization Ranks Registered Latency CT6472Z265 18T 512 MB 64M X 72 Dual Unbuffered 2 5 CT64647265 16T 512 MB 64M X 64 Dual Unbuff
8. NET RX DATA VALID LOC 7 NET ERROR LOC 72 NET RX CLOCK LOC M8 NET RX DATA IOSTANDARD LVTTL NET RX ERROR IOSTANDARD LVTTL NET RX CLOCK IOSTANDARD LVTTL NET RX DATA VALID IOSTANDARD LVTTL NET ENET RESET Z LOC G6 NET CARRIER SENSE LOC C5 NET COL DETECT LOC D5 NET ENET SLEWO LOC B3 NET ENET SLEW1 LOC A3 NET MDIO LOC M5 NET MDC LOC M6 NET MDINIT Z LOC G5 NET PAUSE LOC J4 NET SSN DATA LOC 073 NET ENET RESET Z IOSTANDARD LVTTL NET ENET RESET Z DRIVE 8 NET ENET RESET Z SLEW SLOW NET CARRIER SENSE IOSTANDARD LVTTL NET COL DETECT IOSTANDARD LVTTL ERNET Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 119 XILINX Appendix E User Constraint Files UCF d ENET SLEWO IOSTANDARD LVTTL SLEW1 IOSTANDARD LVTTL ENET SLEWO DRIVE 8 SLEW1 DRIVE 8 5 d 5 d 5 d pg 3 BI pg DN T ENET SLEWO SLEW SLOW T ENET SLEW1 SLEW SLOW NET MDIO IOSTANDARD LVTTL NET MDC IOSTANDARD LVTTL NET MDIO DRIVE 8 NET MDC DRIVE 8 NET MDIO SLEW SLOW NET MDC SLEW SLOW z 158 5 3 MDINIT Z IOSTANDARD LVTTL 5 d PAUSE IOSTANDARD LVTTL PAUSE DRIVE 8 PAUSE SL
9. Boundary Scan Slave Desktop Configuration ne xct32p xc2vp30 File File File TDO Assign New Configuration File 2 Lookin MY DESIGN vlea MY DESIGN PROM mcs File name DESIGN ROM mcs Open Files oftype mcs Files mcs w 2 Figure B 12 Assigning the MCS File to the 18 Select BYPASS as the configuration files for the System ACE controller and the Virtex lI Pro FPGA Virtex ll Pro Development System www xilinx com 83 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix B Programming the Platform FLASH PROM User Area 19 Right mouse click on the icon for the XCF32P PROM and select Program from the drop down menu as shown in Figure B 13 8 untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help D S H Bs A Boundary Scan Slave SelectMAP Desktop Configuration 7 Verify Xc Erase _ ank Check Readback Get Device ID Get Device Checksum Get Device Signature Usercode Get Device Customer Code IDCODE Looping TDI Assign New Configuration Figure B 13 Programming the PROM 20 The iMPACT software responds with a form that allows the user to specify which design revisions are to be programmed and the programming options for t
10. Ei s NET HS IO IOSTANDARD LVTTL NET HS CLKOUT IOSTANDARD LVTTL NET HS CLKIN IOSTANDARD LVCMOS25 NET HS CLKIO IOSTANDARD LVTTL T HS LOC AF6 T HS IO 2 LOC AE5 5 10131 LOC 8 T HS IO 4 LOC AB7 T HS IO 5 LOC AE4 T HS IO 6 LOC AE3 T HS IO 7 LOC AF4 T HS IO 8 LOC AF3 T HS IO 9 LOC AC6 T HS IO 10 LOC AC5 HS IO 11 LOC AF2 HS IO 12 LOC AFL HS IO 13 LOC HS IO 14 LOC AD3 HS IO 15 LOC AA8 HS IO 16 LOC 7 HS IO 17 LOC AE2 HS IO 18 LOC 1 HS IO 19 LOC AB6 HS TO 20 LOC AB5 HS IO 21 LOC 8 HS IO 22 LOC Y7 HS IO 23 LOC AD2 HS IO 24 LOC HS 101251 LOC L7 HS IO 26 LOC L8 HS IO 27 LOC Gl HS IO 28 LOC G2 HS TO 29 LOC G3 HS IO 30 LOC G4 d zd zl el d d 3 3 3 d 4 d 3 d a pi d z oc c c oz zi uic vi wi Zi Z E Hj pO LE LED HA DM B3 DER S D 3 DEP 14 1231 PEG Ud pH BO DB DE BA P ON DU 3 BE LED 14 G d T HS IO 31 LOC 05 T HS 101321 LOC 76 T HS 101331 LOC FI T HS IO 34
11. Edit Mode Operations Output Help D S x System PROM Formatter SVF STAPL XSVF Revision h xcf32p 69 08 Full xcevp30 my_design bit Figure B 10 Switching to Configuration Mode 15 Make sure that the XUP Virtex II Pro Development System is powered up and that either a USB cable or a PC4 cable connects the board to the PC that is running the iMPACT software 16 Select the Initialize Chain command shown in Figure B 11 82 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 5 XILINX 8 untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D X Ese Boundary Scan Slave 5 Figure B 11 Initializing the JTAG Chain The iMPACT software then interrogates the system and reports that there are at least three devices in the JTAG chain The first device is the XCF32P the second device is the System ACE controller and the third device is the Virtex II Pro FPGA Any additional devices shown in the JTAG chain will reside on optional expansion boards 17 Select the MCS file that you created earlier as the configuration file for the XCF32P PROM and click Open as shown inFigure B 12 untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D s X E 86 ss 55 131 2 55 O S 2
12. O untitled Configuration Mode iMPACT Fle Edt View Mode Operations Output Help Da X E 5 88 56 12 2 031 z zz S P Boundary Scan Slave Desktop Configuration Specify Xilinx PROM Device Auto Select PROM Selecta PROM xcfp fxcf32p Position 0 xcf32p Number of Revisions 2 Delete All Figure B 4 Selecting an XCF32P PROM with Two Revisions Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 79 1 800 255 7778 5 XILINX 80 Appendix Programming the Platform FLASH PROM User Area 7 Clickon Next twice to bring up the Add Device File screen shown in Figure B 5 B untitled File Generation Mode iMPACT Edit View Mode Operations Output Help D s x 2 O S I System ACE PROM Formatter SVF STAPL XSVF x Revision 0 Starting Address Max 8 Hex Digits 0 Now start adding device file s Add File lt Back Mext gt Help Figure B 5 Adding a Device File 8 Clickon Add File and navigate to your design directory and select the bit file for your design as shown in Figure B 6 9 Click on Open and answer No when prompted to add another design file to Revision 0 G untitled File Generation Mode IMPACT Edit View Mode Operations Output Help
13. lign RANGE SLICE X38Y152 SLICl FAST LOC GT X2Y1 P X39Y153 LVI CTL n 1 bk E HE HE FE fk FE HE FE HE E FE HE FE HE FE AP FE AP FE HE AP AP AL FE H HE E HE HE FE HE FE FE FE HE HE FE HE FE HE FE FE FE HE FE FE HE HE HE E FE H HE H A H SATA 2 HOST logic REA GROUP PHASE EA GROUP PHASE A SAT SAT SA LIGN 2 LIGN 2 GRP PORT2 IDLE LOC C15 PORT2 IDLE IOSTANDARD PORT2 IDLE SLEW 2 5 pou P 5 z Z gt E Ltd EJ HERE HE THEE HH HEHE HE H SMA MGT HEE HEE HH FE FE HE E HH HH FE HE HH HE HE HH H HE H EET IEEE I TH n RANGE SLICE_X50Y152 SLICI FAS P X51Y153 1 LVTTL ne 1 HE HE HE He HE FE HE FE HE E HE HE FE HE FE FE HE HE AP HE f H EE E HE HE HE HE FE FE FE HE E FE HE FE HE FE FE FE HE FE HE E HE HE HE FE H HE H A H INST hierarchical_path_to_mgt SMA GT X3Y1 INST hierarchical path to al n lign LOC GT X3Y1 SMA MGT logic AREA GROUP PHASE AI AREA GROUP PHASE LIGN 3 LIGN 3 GRP www xilinx com 1 800 255 7778 RANGE SLICE X74Y152 SLICl P I X75Y153 Virtex ll Pro Development System UGO69 v1 0 March 8 2005 XILINX Appendix F Links to the Component Data Sheets This appendix provides links to the manufacturer
14. GNO Bs sre ii DL a DOU 1 ARR A 14 L ar 25555 4 W 4 p l a La 1 i av eeu PEE A SYNCHRONOUS 16 44 48 veas REGULATOR So 35 58 1 Ot 4 GNO 2 cous 4 JA _ ___ VSENSE a POWERPAD ou AON PI 14069 04 021505 Figure 2 1 Typical Switching Power Supply Virtex ll Pro Development System www xilinx com 19 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Because of the analog nature of the MGTs the power for those elements are created by low noise low dropout linear regulators Figure 2 2 shows the power supply for the MGTs FIXED 2 5V LDO VCCSV8 VCC_MGT 1 427 C429 C428 6 3V 1000PF 6 3V C430 0 1UF C431 l T 6 3v OUT vir GND case 1000 330UF 6 3V LT1963AEQ 25 asi 0 1UF FERRITE BEAD 2961666671 GND MGT 000069 05 010605 2 2 Configuring the FPGA At power up or when the RESET RELOAD push button 5 1 is pressed for longer than 2 seconds the FPGA begins to configure The two configuration methods supported JTAG an
15. zd SDRAM DQ 53 LOC AD27 SDRAM DQ 52 LOC AD28 SDRAM DO 51 LOC AA23 SDRAM DQ 50 LOC AA24 SDRAM DQ 49 LOC AE29 SDRAM 0 48 LOC 25 E d E zl DE HELD DESEE LEE RED DD DE p Dg 5 d NET SDRAM DOS 5 LOC AA25 NET SDRAM DM 5 LOC W27 NET SDRAM 471 LOC AC29 NET SDRAM DQ 46 LOC AB27 NET SDRAM DQ 45 LOC AB28 NET SDRAM DQ 44 LOC W23 NET SDRAM DQ 43 LOC W24 NET SDRAM DQ 42 LOC 27 NET SDRAM DO 41 LOC AA28 NET SDRAM DO 40 LOC Y26 1 T SDRAM DOS 4 LOC V23 2 T SDRAM DM 4 LOC W28 T SDRAM DQ 39 LOC AA29 T SDRAM DQ 38 LOC 29 El d SDRAM DQ 37 LOC V25 SDRAM DO 36 LOC V26 SDRAM DO 35 LOC U23 SDRAM 0 34 LOC U24 SDRAM DO 33 LOC Y30 SDRAM DQ 32 LOC V27 3 E 4 ET dj dE EL BI BS BJ Dg p pu 4 NET SDRAM DOS 8 LOC T23 NET SDRAM DM 8 LOC U22 NET SDRAM CB 7 LOC U28 NET SDRAM CB 6 LOC T27 NET SDRAM CB 5 LOC T28 NET SDRAM CB 4 LOC T25 NET SDRAM CB 3 LOC T26 NET SDRAM CB 2 LOC V30 NET SDRAM CB 1 LOC U30 NET SDRAM CB 0 LOC R28 Virtex ll Pro Development System www xilinx com 131 00069 v1 0 March 8 2005 1 800
16. NET SDRAM 1 LOC K26 NET SDRAM A 13 LOC M23 NET SDRAM A 12 LOC M24 NET SDRAM A 11 LOC F30 NET SDRAM A 10 LOC F28 NET SDRAM A 9 LOC K24 NET SDRAM A 8 LOC J24 NET SDRAM A 7 LOC D26 NET SDRAM A 6 LOC G26 NET SDRAM A 5 LOC G25 NET SDRAM 41 LOC K30 NET SDRAM A 3 LOC M29 NET SDRAM A 2 LOC L26 NET SDRAM A 1 LOC N25 NET SDRAM A 0 LOC M25 130 www xilinx com Virtex Il Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 XILINX FEFE E FE FE HE HE HE HE FE HE HE FE E HE E FE HE FE FE FE FE FE FE FE FE FE FE HE FE FE FE FE HE FE FE FE HE HE HE HE HE HE HEHE NET REQUIRED FOR XMIL IMPLEMENTATION HEE HE HE HE HE HE HE FE FE HE HE HE FE FE FE HE FE FE HE FE HE FE FE FE HE FE FE A A A A A AA HE HE HE HEHE HHE NET RST_DQS_DIV LOC P27 NET RST_DQS_DIV LOC P26 NET SDRAM DOS 7 LOC AH26 NET SDRAM_DM 7 LOC W25 NET SDRAM_DQ 63 LOC AH29 NET SDRAM_DQ 62 LOC AH27 NET SDRAM_DQ 61 LOC AG28 NET SDRAM_DQ 60 LOC AD25 NET SDRAM_DQ 59 LOC AD26 NET SDRAM_DQ 58 LOC AG29 NET SDRAM_DQ 57 LOC AG30 NET SDRAM_DQ 56 LOC AF25 5 d SDRAM DOS 6 LOC AC25 T SDRAM DM 6 LOC W26 T SDRAM DQ 55 LOC AF29 T SDRAM DQ 54 LOC AF30
17. Signal Direction MOI n jue Type SDRAM DQI 58 I O 87 AG29 SSTL2 II SDRAM_DOQJ59 I O 88 AD26 SSTL2 II SDRAM DOQ 60 I O 174 AD25 SSTL2 II SDRAM DO 61 I O 175 AG28 SSTL2 II SDRAM DQI 62 I O 178 AH27 SSTL2 II SDRAM DQI 63 I O 179 AH29 SSTL2 II SDRAM DOQS 7 I O 86 AH26 SSTL2 II SDRAM DM 7 0 177 W25 SSTL2 II SDRAM CB 0 I O 44 R28 SSTL2 II SDRAM CB 1 I O 45 U30 SSTL2 II SDRAM CB 2 I O 49 V30 SSTL2 II SDRAM CB 3 I O 51 T26 SSTL2 II SDRAM CB 4 I O 134 25 SSTL2 II SDRAM CB 5 I O 135 T28 SSTL2 II SDRAM CB 6 I O 142 T27 SSTL2 II SDRAM CB 7 I O 144 U28 SSTL2 II SDRAM DOS 8 I O 47 123 SSTL2 II SDRAM DM 8 0 140 U22 SSTL2 II SDRAM A 0 48 25 SSTL2 II SDRAM 43 N25 SSTL2 II SDRAM A2 41 126 SSTL2 II SDRAM A 3 130 29 SSTL2 II SDRAM A 4 37 K30 SSTL2 II SDRAM A 5 32 G25 SSTL2 II SDRAM A 6 125 26 SSTL2 II SDRAM A 7 29 D26 SSTL2 II SDRAM A 8 122 SSTL2 II SDRAM A 9 27 K24 SSTL2 II SDRAM A 10 141 28 SSTL2 II SDRAM A 11 118 SSTL2 II SDRAM A 12 115 24 SSTL2 II Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 33 XILINX Chapter 2 Using the System Table 2 5 DDR SDRAM Connections Continued Signal Direction SDRAMA 3 aw M23 sm SDRAM 137 27 SS
18. 3 5 5 5 m 2 5 5 5 5 5 5 2 5 45 46 EXP IO 47 EXP IO 48 EXP IO 49 EXP IO 50 EXP IO 51 EXP IO 52 EXP IO 53 EXP IO 54 EXP IO 55 EXP IO 56 EXP IO 57 EXP IO 58 EXP IO 59 EXP IO 60 EXP IO 61 EXP IO 62 EXP IO 63 EXP IO 64 EXP IO 65 EXP IO 66 EXP IO 67 EXP IO 68 EXP IO 69 EXP IO 70 EXP IO 71 EXP IO 72 EXP IO 73 EXP IO 74 EXP IO 75 EXP IO 76 EXP IO XUP V2PRO D CIRCUIT BOARD LOC T8 LOC U4 LOC U5 LOC V2 LOC W2 LOC T9 LOC U9 LOC V3 LOC V4 LOC W1 LOC 1 LOC U7 LOC U8 LOC V5 LOC V6 LOC Y2 LOC AA2 LOC V7 LOC V8 LOC W3 LOC W4 LOC 1 LOC ABI LOC W5 LOC W6 LOC Y4 LOC Y5 LOC AA3 LOC AA4 LOC W7 LOC W8 LOC AB3 IOSTANDARD LVTTL CHARACTERISTICS FOR THE EVELOPMENT DEC 8 2004 RIGHT LOW SPI SYST Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 127 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE HIGH SPE EXPANSION PORT OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004
19. AUP U2Pro BuiltIn Self Test Main Menu Rev 1 1 12 14 2004 Test SATA port with Aurora loopback Test Ethernet with WEB example Test 8 97 audio codec Test System ACE Test DDR SDRAM Quit Figure D 5 Selecting the SATA Port Tests 7 After entering 1 from the Main Menu in the terminal window select which of the two serial ATA pairs you would like to run the test on See Figure D 6 Tera Term COMI VT File Edit Setup Control Window Help 1 SATA Test Menu erify the SATA cable is connected between SATAO Host and SATA1 Target or SATA2 Host and SATA1 Target Run loop test SATAA Host and SATA1 Target Run loop test on SATA2 Host and SATA1 Target Quit Figure D 6 Selecting the Specific SATA Port to Test 8 After selecting one of the two tests the screen will clear and the reset link status is displayed as shown in Figure D 7 Tera Term COMI VT File Edit Setup Control Window Help urora Test System Uersion 2 1 Figure D 7 Resetting the MGTs This indicates that the MGTs were correctly reset and that at least one of the two serial ATA transceivers is able to establish link up status The screen will also clear and the second test status menu will be displayed Note The link status line is highlighted showing that both transceivers have bidirectional communications links established and are transmitting and receiving data www xilinx com Virtex
20. 2 Makesure that the XUP Virtex II Pro Development System is powered up and that either a USB cable or a PC4 cable connects the board to the PC that is running the iMPACT software Xilinx University Program Virtex ll Pro Development Systemwww xilinx com 87 00069 v1 0 March 8 2005 1 800 255 7778 5 XILINX 88 System Appendix C Restoring the Golden FPGA Configuration 3 Startup iMPACT and select Configure Devices as shown in Figure C 1 O untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D s m ela agn ss t EE 0 p Boundary Scan Slave Serial SelectMAP Desktop Configuration Operation Mode Selection x What do you wantto do first 8 Configure Devices Prepare Configuration Files Load Configuration File cdf pdr Figure C 1 Operation Mode Selection Configure Devices 4 Clock on Next and select the Boundary Scan Mode from the option menu shown in Figure C2 www xilinx com Xilinx University Program Virtex ll Pro Development 1 800 255 7778 06069 v1 0 March 8 2005 5 XILINX alaa zl Configure Devices Figure C 2 Selecting Boundary Scan Mode Xilinx University Program Virtex ll Pro Development Systemwww xilinx com 001069 v1 0 March 8 2005 1 800 255 7778 89 XILINX Appendix C Restoring the Golden FPGA Configuration 5 Click on Next and then select Automatically connect to the cable
21. DIP switch SW9 with both of the switches up or closed 2 Plug in the external 5V power supply and turn on the board by sliding SW11 up towards the ON label LEDs D14 GOLDEN CONFIG D19 PROM CONFIG and D4 DONE should be on 3 Observe the status of the four user LEDs D7 10 LED 3 LED 2 and LED 1 should flash at different rates and LED 0 should be on steady indicating that the DCMs in the FPGA are locked to the clock signals flashing LED 3 indicates that the 100 MHz system clock is present A flashing LED 2 indicates that the 75 MHz MGT clock is present A flashing LED 1 indicates that the 32 MHz System ACE clock is present Asteady on LED 0 indicates that the DCMs are locked 4 After about 5 seconds the LEDs should shop flashing and their function changes to indicate the status of the USER INPUT DIP switch SW7 If a switch is down or open the corresponding LED will be off if the switch is up or closed the LED will be on LED 3 shows the status of USER INPUT switch 3 LED 2 shows the status of USER INPUT switch 2 LED 1 shows the status of USER INPUT switch 1 LED O shows the status of USER INPUT switch 0 Virtex ll Pro Development System www xilinx com 99 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test 5 Briefly less than 2 seconds press the RESET RELOAD push button SW1 This should resu
22. EXP IO 18 LOC N1 5 d 5 3 5 3 E zl m d E d m d 2 d 5 d 5 3 T EXP IO 19 LOC P1 T EXP IO 20 LOC P8 T EXP IO 21 LOC P7 5 d EXP IO 22 LOC N4 EXP IO 23 LOC N3 T EXP IO 24 LOC P3 T EXP IO 25 LOC P2 EXP IO 26 LOC R8 T EXP IO 27 LOC R7 T EXP IO 28 LOC P5 T EXP IO 29 LOC P4 T EXP IO 30 LOC R2 T EXP IO 31 LOC T2 T EXP IO 32 LOC R6 T EXP IO 33 LOC R5 T EXP IO 34 LOC R4 T EXP IO 35 LOC R3 a EXP IO 36 LOC Ul EXP IO 37 LOC V1 5 d T EXP IO 38 LOC T5 T EXP IO 39 LOC T6 T EXP IO 40 LOC T3 T EXP IO 41 LOC 5 d EXP IO 42 LOC U2 EXP IO 43 LOC U3 EXP IO 44 LOC 7 5 3 E Ed PE bd Dj Dj bd b o b B b ob Dj Dj Dd PJ B B EJ B PJ Dd Dd EJ Bl bj Dl Bd j 5 3 NET EXP_IO_ IOSTANDARD LVTTL 126 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 3 XILINX PINOUT AND IO DRIVE EXPANSION PORT OF THE REVISION C PRINTED ZazazzzZzZaZzZazZz zizZZIZZZZZIZIZIZIZIZIZ IZIZ Ej Ed bd bj b bd Ed bd Ed bd bd Fj Ed bd Ltd Ed bd bd Ed Dd pd tn 5 5 5 E m E m 2 3 5
23. LOC F2 T HS IO 35 LOC T HS IO 36 LOC F4 T HS IO 37 LOC K7 T HS IO 38 LOC K8 T HS IO 39 LOC EL T HS IO 40 LOC E2 T HS CLKOUT LOC T HS CLKIN LOC B16 T HS CLKIO LOC E3 128 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 XILINX PINOUT AND IO DRIVE CHARACTERISTICS FOR THI E OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 SW 0 LOC 11 NET SW 1 LOC AD11 NET SW_2 LOC AF8 NET SW 3 LOC AF9 NET SW 0 IOSTANDARD LVCMOS25 NET SW 1 IOSTANDARD LVCMOS25 NET SW 2 IOSTANDARD LVCMOS25 NET SW 3 IOSTANDARD LVCMOS25 PINOUT AND IO DRIVE CHARACTERISTICS FOR THE PORTS OF THE XUP V2PRO D REVISION C PRINTI Xj EVELOPMENT SYSTEM ED CIRCUIT BOARD DEC 8 2004 NET KBD CLOCK LOC AG2 NET KBD DATA LOC AGI NET MOUSE CLOCK LOC AD6 NET MOUSE DATA LOC AD5 NET KBD CLOCK IOSTANDARD LVTTL NET KBD DATA IOSTANDARD LVTTL NET MOUSE CLOCK IOSTANDARD LVTTL NET MOUSE DATA IOSTANDARD LVTTL NET KBD CLOCK DRIVE 8 NET KBD DATA DRIVE 8 NET MOUSE CLOCK DRIVE 8 NET MOUSE DATA DRIVE 8 NET KBD CLOCK SLEW SLOW NET KBD DATA SLEW SLOW NET MOUSE CLOCK
24. RX DATA 3 I K1 LVTTL RX DATA VALID I M7 LVTTL _ 1 J2 LVTTL RX CLOCK I 8 ENET RESET Z G6 LVTTL 8mA SLOW CARRIER SENSE I C5 LVTTL COL DETECT I D5 LVTTL ENET_SLEW0 O B LVTTL 8mA SLOW ENET_SLEW1 O A3 LVTTL 8mA SLOW MDIO I O M5 LVTTL 8 mA SLOW MDC O M6 LVTTL 8 SLOW MDINIT Z I G5 LVTTL PAUSE J4 LVTTL 8 SLOW SSN_DATA I 73 LVTTL 8 mA SLOW Using System ACE Controllers for Non Volatile Storage In addition to programming the FPGA and storing bitstreams the System ACE controller can be used for general purpose non volatile storage Each System ACE controller provides an MPU interface to allow a microprocessor to access the attached CompactFlash or IBM Microdrive allowing this storage media to be used as a file system The MPU interface provides a useful means of monitoring the status of and controlling the System controller as well as CompactFlash card READ WRITE data The MPU is not required for normal operation but when it is used it provides numerous capabilities This interface enables communication between an MPU device a CompactFlash card and the FPGA target system The MPU interface is composed of a set of registers that provide a means for communicating with CompactFlash control logic configuration control logic and other resources in the System ACE controller This interface can be used to read the identity of a Co
25. SLEW SLOW NET MOUSE DATA SLEW SLOW USER SWITCHES PS 2 Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 129 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE DDR SDRAM SECTION OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET SDRAM DQ IOSTANDARD SSTL2 NET SDRAM CB IOSTANDARD SSTL2 II SDRAM DOS IOSTANDARD SSTL2 II NET SDRAM DM IOSTANDARD SSTL2 II NET SDRAM CK IOSTANDARD SSTL2 II NET SDRAM CK Z IOSTANDARD SSTL2 II NET SDRAM A IOSTANDARD SSTL2 II NET SDRAM BA IOSTANDARD SSTL2 II NET SDRAM RAS 2 IOSTANDARD SSTL2 II NET SDRAM CAS 2 IOSTANDARD SSTL2 II NET SDRAM WE 2 IOSTANDARD SSTL2 II NET SDRAM 5 2 IOSTANDARD SSTL2 II NET SDRAM CKE IOSTANDARD SSTL2 II NET SDRAM CK2 LOC AB23 NET SDRAM CK2 27 LOC AB24 NET SDRAM CK1 LOC AD29 NET SDRAM 2 LOC AD30 NET SDRAM CKO LOC AC27 NET SDRAM 2 LOC AC28 NET SDRAM CKEO LOC R26 NET SDRAM 1 LOC R25 NET SDRAM SO 2 LOC R24 NET SDRAM 61 Z LOC R23 NET SDRAM RAS 2 N29 NET SDRAM CAS 2 LOC 127 NET SDRAM WE 2 LOC N26 NET SDRAM BAO LOC M26
26. answer y the Web server will be started as shown Figure D 12 If you answer uu n n you will repeat step 1 JE Tera Term VT File Edit Setup Control Window Help AUP U2Pro BuiltIn Self Test Main Menu Rev 1 0 12 13 2004 Test SATA port with Aurora loopback Test Ethernet with WEB example Test fiC97 audio codec Test System ACE DDR SDRAM MAC Address 88 11 22 33 44 55 make sure it is allowed in your network Input your IP address hit ENTER directly for default previous address 192 168 0 32 128 187 114 140 Are you sure this address is correct y n gt EB server IP 128 187 114 146 EB server started ype http 128 187 114 146 8686 in your browser to test the WEB server Follow the instruction on the WEB page to stop the WEB server Figure D 12 Web Server Running Virtex ll Pro Development System www xilinx com 107 UG069 v1 0 March 8 2005 1 800 255 7778 5 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test 2 Opena Web browser and type in http YOUR XUP PRO BOARD IP ADDRESS 8080 in for the address and you will see a Web page sent from the XUP Pro board as shown in Figure D 13 a http 128 187 114 140 8080 Microsoft Internet Explorer File Edit View Favorites Tools Help 480 Gen B Da Address http 128 187 114 140 8080 Figure D 13 Web Server Display 3 You can click the Submit button
27. are used to select the bank and starting column location for the burst address DDR SDRAM provides for 2 4 8 or full page programmable Read or Write burst lengths The allowable burst lengths depend on the specific DDR SDRAM used on the DIMM module This information can be obtained from the serial presence detect SPD EEPROM An auto precharge function can be enabled to provide a self timed precharge that is initiated at the end of the burst sequence As with standard SDRAMs the pipelined multibank architecture of DDR SDRAMs allows for concurrent operation thereby providing high effective bandwidth by hiding row precharge and activation time The modules incorporate a serial presence detect SPD function implemented using a 2048 bit EEPROM The first 128 bytes of the EEPROM are programmed by the module manufacturer to identify the module type and various SDRAM timing parameters The remaining 128 bytes of EEPROM are available for use as non volatile memory The EEPROM is accessed using a standard bus protocol using the SDRAM SCL serial clock and 50 SDA serial data signals Data on the SDRAM SDA signal can change only when the clock signal SDRAM SCL is low Changes in the SDRAM SDA data signal when SDRAM SCL is high this indicates a start or stop bit condition as shown in Figure 2 6 A high to low transition of SDRAM SDA when SDRAM SCL is high indicates a start bit condition the start of all commands A low to high tr
28. m E m 2 5 5 3 5 5 5 m 60 61 62 63 64 65 66 67 68 69 EXP IO 70 EXP IO 71 EXP IO 72 EXP IO 73 EXP IO 74 EXP IO 75 EXP IO 76 EXP IO 77 EXP IO 78 EXP IO 79 EXP TO LOC LOC AA2 LOC V7 LOC V8 LOC W3 LOC W4 LOC AAI LOC ABI LOC W5 LOC W6 LOC Y4 LOC Y5 LOC AA3 LOC 4 LOC 7 LOC W8 LOC ABI LOC AB4 LOC LOG AC2 IOSTANDARD CHARACTI ER OF THE XUP V2PRO DEVELOPMENT SYSTI CIRCUIT BOARD DEC 8 2004 ERISTICS FOR THE LOWER LVTTL lt XUP Virtex II Pro Development System UG069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 125 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE LEFT LOW SPE EXPANSION PORT OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 E s 5 d EXP IO 8 LOC N6 EXP IO 9 LOC N5 EXP IO 10 LOC L5 EXP IO 11 LOC L4 EXP IO 12 LOC 2 EXP IO 13 LOC N2 EXP IO 14 LOC P9 EXP IO 15 LOC R9 EXP IO 16 LOC M4 EXP IO 17 LOC M3
29. 1 575V and LED D19 1 5V OK should be on 6 Install the Shorting Jumper Block on JP2 LED D17 2 5V OK should be off and D6 RELOAD PS ERROR should be on Remove the Shorting Jumper Block 7 Install the Shorting Jumper Block on JP6 LED D19 1 5V OK should be off and D6 RELOAD PS ERROR should on Remove the Shorting Jumper Block 8 Turn the circuit board over 9 Connect the negative lead of the multimeter to the negative side of C433 and the positive lead to the positive side of C433 The meter should read between 2 375V and 2 625V verifying the correct voltage for the MGT termination 10 Connect the negative lead of the multimeter to the negative side of C428 and the positive lead to the positive side of C428 The meter should read between 2 375V and 2 625V verifying the correct voltage for the MGT power supply 11 Turn the circuit board component side up Clock Push Button DIP Switch LED and Audio Amp Test This test verifies the presence of the various clocks push buttons DIP switches audio amplifier and the beep tone passthrough capability of the audio CODEC The four user LEDs are used to verify the operation of the clocks and to display the status of the user DIP switches Pressing each of the push buttons results in a different tone from the headphones Additional Hardware Required external power supply Headphones Test Procedure 1 Set the CONFIG SOURCE PROM VERSION
30. 2 22 86 22 55 CR E s 22 00 S X Boundary Scan Slave Desktop Configuration xc2vp30 1 Assign New Configuration File 2 Lookin BIST k File name hw bist bit Files oftype Design Files Cancel All Bypass 2 Figure 7 Assigning a Configuration File to the FPGA Any additional files required by the design can specified at this time Right click on the Virtex II Pro FPGA and select Program to program the device as shown in Figure A 8 Operations Output Help e iix igi gw ave Serial SelectMAP Desktop Configuration sux i 2 Verify BYPASS hw_bi Get Device ID Get Device Signature Usercode Figure A 8 Programming the FPGA 76 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 lt XILINX Appendix B Programming the Platform FLASH PROM User Area XUP Virtex II Pro Development System contains an XCF32P Platform FLASH PROM that is used to contain a known Golden configuration and a separate User configuration These two FPGA configurations are supported by the design revisioning capabilities of the Platform FLASH PROM s The Golden configuration is stored Revision 0 and is write erase protected and the User configuration is stored in
31. 2 Using the System Configuring the Power 19 Configuring the FPGA HERR S ERROR EO PR Ed 20 Clock Generation and 23 Using the DIMM Module DDR SDRAM 24 Using the XSGA Owdtp ut I ae 34 Using the AC97 Audio CODEC and Power 39 Using the LEDs and Switches 43 Using the Expansion Headers and Digilent Expansion Connectors 44 Using the CPU Debug Port and CPU 58 Using the Serial Ports coercere eR kaa e RR OR RR t Ea 60 Using the Fast Ethernet Network 4 62 Using System ACE Controllers for Non Volatile Storage 65 Using the Multi Gigabit Transceivers 67 06069 v1 0 March 8 2005 www xilinx com Virtex ll Pro Development System Appendix A Configuring the FPGA from the Embedded USB Configuration Port Appendix B Programming the Platform FLASH PROM User Area Appendix C Restoring the Golden FPGA Configuration Appendix D Using the Golden FPGA Configuration for System Self Test Hardware Based 98 Power Supply
32. 2 15 1 16 1 60 GND J5 1J6 1 Table 2 14 Left Digilent Expansion Connector Pinout PIN Signal Pin HeaderPin 1 GND J1 4 EVEN PINS 3 VCC3V3 5 EXP IO 9 N5 J1 29 LVTTL 7 EXP IO 11 J1 33 LVTTL 9 EXP IO 13 N2 71 37 LVTTL 11 EXP IO 15 R9 7141 LVTTL 13 EXP IO 17 M3 J1 45 LVTTL 15 EXP IO 19 P1 J1 49 LVTTL 17 EXP IO 21 P7 J2 13 LVTTL 19 EXP IO 23 N3 J2 17 LVTTL 21 EXP IO 25 P2 221 LVTTL 23 EXP IO 27 R7 J2 25 LVTTL 25 EXP IO 29 P4 2 29 LVTTL 27 EXP IO 31 2 2 33 LVTTL 29 EXP IO 33 R5 J2 37 LVTTL 31 EXP IO 35 R3 J241 LVTTL 33 EXP IO 37 V1 J2 45 LVTTL 35 EXP IO 39 T6 J2 49 LVTTL Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 53 XILINX Chapter 2 Using the System Table 2 14 Left Digilent Expansion Connector Pinout Continued PIN Signal pin HeaderPin OType 31 EXP IO 35 R3 J241 LVTTL 33 EXP IO 37 V1 J2 45 LVTTL 35 EXP IO 39 T6 J2 49 LVTTL 37 EXP IO 41 T4 J3 13 LVTTL 39 EXP IO 43 U3 J3 17 LVTTL 2 VCC5VO 4 EXP IO 8 N6 7127 LVTTL 6 EXP IO 10 L5 J1 31 LVTTL 8 EXP IO 12 M2 J1 35 LVTTL 10 EXP IO 14 9 11 39 LVTTL 12 EXP IO 16 M4 J1 43 LVTTL 14 EXP IO 18 N1 J1 47 LVTTL 16 EXP IO 20 P8 72 11 LVTTL 18 EXP IO 22 4 J2 15 LVTTL 20 EXP IO 24 P3 J2 19 LVTTL 22 EXP IO 26 R8 2 23 LVTTL 24 EXP IO 28 5 J2 27 LVT
33. 8 Xilinx University Program Virtex ll Pro Development Systemwww xilinx com 93 001069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix C Restoring the Golden FPGA Configuration Advanced PROM Programming Options x Design Revision and Customer Code Select Design Revision and Enter Customer Code 64 Hex Digits Design Read Write Erase Verify Customer Revision Protect Protect Code RP PWE va Rei fo MA 0 Reva pw Term Pwa Default Revision 8 m Operating Mode 1 0 Configuration e Slave clocked by external clock Parallel Mode w Master select clock source Usercade Enter 8 Hex Digits Usercode Internal Clack FFFFFFFF Clock Frequency Load FPGA 6 External Glock M Figure C 8 PROM Programming Options 12 Click on OK to begin programming the PROM The iMPACT transcript window shows the sequence of operations that took place and looks similar to Figure C 9 94 www xilinx com Xilinx University Program Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 BATCH CMD Program p 1 defaultVersion 0 selectMap8 ver 0 wp PROGRESS START Starting Operation Validating chain Boundary scan chain validated successfully Validating chain scan chain validated successfully 11 Putting devi
34. Audio Test Menu Begin playing the audio from the PC or other audio source The sound should be heard from the headphones or speakers for about 10 seconds The terminal window output for the FIFO Loopback test is shown in Figure D 17 Pec ecce Tera Term COM1 VT File Edit Setup Control Window Help ACI Fifo Loopback Test Initializing audio chip Playing audio Fifo Loopback test complete lt Type to return to menu gt Figure D 17 FIFO Loopback Test Completion Game Sounds Test Procedure 1 Select 3 from the AC97 Audio Test Menu 2 Game sounds should be heard out the headphones or speakers for about 5 seconds 3 The terminal window output for the Game Sounds test is shown in Figure D 18 110 www xilinx com Virtex ll Pro Development System 1 800 255 7778 UGO69 v1 0 March 8 2005 Processor Based Tests XILINX Tera Term COM1 VT File Edit Setup Control Window Help 1697 Game Sounds Test ame Sounds test complete lt Type to return to menu 41 Figure D 18 Game Sounds Test Completion At any time during the audio tests when one of the push buttons is pressed the corresponding beep is also played on the output jack System ACE Test This test begins when 4 is selected from the BIST Main Menu It checks the functionality of the SYSACE controller interface System ACE Test Procedure 1 After you selected 4 in the BIST Main Menu the program ch
35. D I x me 28 88 z GE sz zz o PROM Formatter SVF STAPL XSVF Revision h li ax Look in a MY DESIGN ek Ey my design bit Filename mydesgnbt Open Files oftype Design Files yi Cancel 2 Figure 6 Adding the Design File to Revision 0 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 7 XILINX 10 Note that Revision 0 is highlighted in green this is where the Golden configuration will be placed in the PROM By selecting your design file for Revision 0 you are just reserving space in the PROM for the Golden configuration Your design file will not overwrite the Golden configuration because it is write erase protected If the design file was created with the Startup Clock set to JTAG iMPACT will issue a warning that the Startup Clock will be changed to CCLK in the bitstream programmed into the PROM This warning is shown in Figure B 7 and can be safely ignored WARNING iMPACT 1050 Startup Clock has been changed to Cclk in the bitstream stored in memory but the original bitstream file remains unchanged L Figure 7 Startup Clock Warning 11 Once you answer No when prompted to add another design file to Revision 0 the green revision highlight will move to Revision 1 You will be prompted to add your design file to R
36. DRAM DQ 12 LOC L23 DRAM DQ 11 LOC G30 DRAM DQ 10 LOC G28 DRAM DQ 9 LOC G27 DRAM DQ 8 LOC J26 DRAM DQS 0 LOC E30 DRAM DM 0 LOC U26 DRAM DQ 7 LOC E28 DRAM DO 6 LOC E27 DRAM DQ 5 LOC H26 DRAM DQ 4 LOC H25 DRAM DQ 3 LOC D30 DRAM DQ 2 LOC D29 DRAM DO 1 LOC D28 DRAM DQ 0 LOC C27 DRAM SDA LOC AF23 DRAM SCL LOC AF22 DRAM SDA IOSTANDARD LVCMOS25 DRAM SCL IOSTANDARD LVCMOS25 132 www xilinx com 1 800 255 7778 Virtex ll Pro Development System UGO69 v1 0 March 8 2005 XILINX PINOUT AND IO DRIVE CHARACTERISTICS FOR THE SYST MPU PORT OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET CF MPA 0 LOC AF21 NET CF MPA 1 LOC AG21 NET CF MPA 2 LOC AC19 NET CF MPA 3 LOC AD19 NET CF MPA 4 LOC AE22 NET CF MPA 5 LOC AE21 NET CF MPA 6 LOC AH22 NET CF MPA IOSTANDARD LVCMOS25 NET CF MPA DRIVE 8 NET CF MPA SLEW SLOW NET CF MPD 0 LOC 15 NET CF MPD 1 LOC AD15 NET CF MPD 2 LOC AG14 NET MPD 3 LOC 14 NET CF MPD 4 LOC 14 NET MPD 5 LOC AD14 NET CF MPD 6 LOC 15 NET CF MPD 7 LOC 15 NET CF MPD 8 LOC AJ9 NET CF MPD 9 LO
37. Device Antipattern 1 Test Device Antipattern 2 Test Data Walking 1 s Test Data Walking s Test Address Walking 1 s Test Address Walking s Test Device Pattern 1 Test Device Pattern 2 Test Device Antipattern 1 Test Device Antipattern 2 Test emory test complete lt to return to menu SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS SUCCESS 5 XILINX Figure D 20 DDR SDRAM Test Completion 2 In the case of an error the following is an example of what would be printed Running Data Walking l s Test FA Address 0x00000000 Expected 0x0000000100000001 Expansion Port Test L ED 0x0000000000000001 Actual This test verifies the connectivity of the FPGA to the four expansion headers the two low speed expansion ports and the single high speed expansion port The design creates a walking one pulse across the 80 bit expansion bus This test signal is also applied to the 64 bit low speed Digilent expansion port and the 43 bit high speed Digilent expansion port It is important that no expansion boards be connected to the XUP Virtex II Pro Development System when this test is running This is to avoid any potential contention between the outputs of the FPGA driving the expansion ports and any output from the installed expansion boards Additional
38. Hardware Required e Oscilloscope Test Procedure 1 This test begins when 6 is selected from the BIST Main menu It checks the functionality of the low speed and high speed expansion ports 2 There is a second prompt before the test starts as shown in Figure 0 21 Virtex ll Pro Development System www xilinx com UG069 v1 0 March 8 2005 1 800 255 7778 113 57 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test Hi Tera Term COM1 VT A xj File Edit Setup Control Window Help 114 xpansion Connector Walking Ones Test ARNING Make sure no expansion boards are connected to the expansion connectors t ype y to continue n to cancel ug076 21 021005 Figure D 21 Confirming Start of the Expansion Port Walking Ones Test 3 Connect the oscilloscope ground lead to any of the pins on the top row of J1 J4 These are all ground GND pins If J1 J4 are not installed then connect the oscilloscope ground lead to the GND pin of J36 the DEBUG PORT This pin is clearly identified on the PCB silkscreen Sequentially check each of the non power pins on the lower rows of J1 J4 You should see a 20 ns pulse with a 1 6 us period at each pin If the pulse is not observed there is a broken trace on the PCB or the level shifters are damaged If the period is not correct two non adjacent signals are shorted together If the pulse width is not correct two or more adjacent sig
39. IO 17 AE2 39P 3 LVTTL 56 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the Expansion Headers and Digilent Expansion Connectors XILINX Table 2 16 High Speed Digilent Expansion Connector Pinout Continued Virtex ll Pro Development System 06069 1 0 March 8 2005 Signal 45 23 HS IO 18 1 39N 3 LVTIL A24 HS IO 19 AB6 40P 3 LVTIL A25 HS IO 20 AB5 40N 3 LVTIL A26 HS IO 21 Y8 41P 3 LVTTL A27 HS IO 22 Y7 41N 3 LVTTL A28 HS IO 23 AD2 42P 3 LVTTL A29 HS IO 24 ADI 42N 3 LVTTL A30 HS IO 25 L7 41P 2 LVTTL A31 HS IO 26 L8 41N 2 LVTTL A32 HS IO 27 G1 40 2 LVTTL A33 HS IO 28 G2 40N 2 LVTTL A34 HS IO 29 G3 39P 2 LVTIL A35 HS IO 30 G4 39N 2 LVTIL A36 HS IO 31 5 38P 2 LVTTL A37 HS IO 32 J6 38P 2 LVTTL A38 HS IO 33 F1 37P 2 LVTTL A39 HS IO 34 F2 37P 2 LVTTL 40 HS IO 35 F3 36P 2 LVTTL 41 HS IO 36 F4 36N 2 LVTIL A42 HS IO 37 K7 35P 2 LVTTL A43 HS IO 38 8 35N 2 LVTIL 44 HS IO 39 E1 34P_2 LVTTL A45 HS_IO_40 E2 34N_2 LVTTL A46 GND 47 HS CLKOUT E4 33N 2 LVTIL 48 GND 49 VCC5VO 50 VCC5VO 01 SHIELD 02 GND B03 LS EXP FPGA TDO www Xilinx com 57 XILINX Chapter 2 Using the System Table 2 16 High Speed Digilent Expansion Connector Pinout Continue
40. IO 9 LOC N5 NET EXP IO 10 LOC L5 NET EXP IO 11 LOC L4 NET EXP IO 12 LOC M2 NET EXP IO 13 LOC N2 NET EXP IO 14 LOC P9 NET EXP IO 15 LOC R9 NET EXP IO 16 LOC M4 NET EXP IO 17 LOC M3 NET EXP IO 18 LOC N1 NET EXP IO 19 LOC P1 NET EXP IOSTANDARD LVTTL 122 www xilinx com Virtex ll Pro Development System 1 800 255 7778 UGO69 v1 0 March 8 2005 3 XILINX PINOUT AND IO DRIVE EXPANSION REVISION C PRINTED z z z z zz zz z z z z 24224222224 Ej td Ed Ed b bd Ed bd m Hd mi Bd bd bd Dd m E 5 5 5 E m E m 2 5 5 3 5 5 5 m EXP IO 20 EXP IO 21 EXP IO 22 EXP IO 23 EXP IO 24 EXP IO 25 EXP IO 26 EXP IO 27 EXP IO 28 EXP IO 29 EXP IO 30 EXP IO 31 EXP IO 32 EXP IO 33 EXP IO 34 EXP IO 35 EXP IO 36 EXP IO 37 EXP IO 38 EXP IO 39 EXP TO LOC P8 LOC P7 LOC N4 LOC N3 LOC P3 LOC P2 LOC R8 LOC R7 LOC P5 LOC P4 LOC R2 LOC LOC R6 LOG R5 LOC R4 LOC R3 LOC Ul LOC V1 LOC 5 LOC T6 IOSTANDARD CHARACTI ER OF THE XUP V2PRO DEVELOPMENT SYSTI CIRCUIT BOARD DEC 8 2004 ERISTICS FOR THE LVTTL UPPER MIDDLE EM V
41. LVCMOS 8mA MPD 2 1 63 LVCMOS25 8mA www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the Multi Gigabit Transceivers XILINX Table 2 20 System ACE Connections Continued Signal Direction M VO Type Drive MPD 3 1 62 LVCMOS25 8mA MPDIA 1 61 14 LVCMOS25 8mA MPD 5 1 60 ADI4 LVCMOS25 8mA MPD 6 1 0 59 15 LVCMOS25 8mA CF MPD 7 1 0 58 15 LVCMOS25 8mA MPDI8 I O 56 AJ9 LVCMOS25 8mA MPD 9 1 53 9 LVCMOS25 8mA 1 0 52 10 LVCMOS5 8mA CF_MPD 11 1 0 51 AF9 LVCMOS25 8 12 1 50 ADI2 LVCMOS25 8mA MPD 13 1 0 49 12 LVCMOS25 8 CF_MPD 14 1 0 48 10 LVCMOS25 8mA CF_MPD 15 1 0 47 AF10 LVCMOS25 8mA CFMP CEZ 42 16 LVCMOS25 8mA CF MP OE Z 77 ADI7 LVCMOS25 8mA WE Z 76 16 LVCMOS25 8mA MPIRQ I 41 ADI6 LVCMOS25 MPBRDY 39 16 LVCMOS25 Using the Multi Gigabit Transceivers The embedded multi gigabit transceiver core is based on Mindspeed s SkyRail technology Eight transceiver cores are available in each of the FPGAs that can be used on the XUP Virtex II Pro Development System The transceiver core is designed to operate at
42. Loopback data from the CODEC s line in is read into the FPGA then sent back out to the CODEC to be played on the output channels line out amp out 3 GameSounds data stored in memory on the FPGA is sent to the CODEC to be played on the output channels line out amp out Additional Hardware Required e Audio cable that connects the line out of a PC or other audio source to the line in on the XUP Virtex II Pro Development System e Headphones or speakers connected to the line out or amp out jack on the Virtex II Pro Development System e Audio sample ready to be played from the PC or other audio source Digital Passthrough Test Procedure 1 Select 1 from the AC97 Audio Test Menu 2 Begin playing the audio from the PC or other audio source 3 Thesound should be heard out the headphones or speakers for about 10 seconds 4 Theterminal window output for the Digital Passthrough test is shown in Figure D 16 Virtex ll Pro Development System www xilinx com 109 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test Tera Term COM1 VT File Edit Setup Control Window Help 8 97 Audio Passthrough Test Initializing audio chip Playing passthrough audio Passthrough test complete lt to return to menu Figure D 16 Digital Passthrough Test Completion FIFO Loopback Test Procedure Select 2 from the AC97
43. RXPPAD7 A12 SATA PORT2 IDLE C15 MGT TXN MGT X3Y1 TXNPAD9 7 USER MGT TXP MGT X3Y1 TXPPAD9 A6 MGT RXN MGT X3Y1 RXNPAD9 A4 X3Y1 RXPPAD9 A5 MGT CLK N G16 BREFCLK MGT CLK P F16 EXTERNAL CLOCK N F15 BREFCLK2 EXTERNAL CLOCK P G15 The MGTs utilize differential signaling between the transmit and receive data ports to minimize the effects of common mode noise and signal crosstalk With the use of high speed serial transceivers the interconnect media causes degradation of the signal at the receiver Effects such as inter symbol interference ISI or data dependent jitter are produced This loss can be large enough to degrade the eye pattern opening at the receiver beyond that which results in reliable data transmission The RocketIO MGTs allow the user to set the initial differential voltage swing and signal pre emphasis to negate a portion of the signal degradation to increase the reliability of the data transmission In pre emphasis the initial differential voltage swing is boosted to create a stronger rising or falling waveform This method compensates for high frequency loss in the transmission media that would otherwise limit the magnitude of the received waveform The initial differential voltage swing and signal pre emphasis are set by two user defined RocketIO transceiver attributes The TX DIFF CTRL attribute sets the voltage difference between the diff
44. Revision 1 Programming the XCF32P Platform FLASH PROM is supported by iMPACT v6 3 01i or later download software using Boundary Scan IEEE 1149 1 IEEE 1532 mode from either the embedded Platform Cable USB J8 or the PC4 cable connection 727 The bit file created by the Xilinx implementation tools must be converted to an MKS file before it can be programmed into the Platform FLASH PROM 1 Start IMPACT and select Prepare Configuration Files as shown in Figure B 1 untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D d X 2 2 at 86 12 55 EE E o S P operation mode sezon O What do you wantto do first Configure Devices Prepare Configuration Files Load Configuration File cdf pdr 5 Figure B 1 Operation Mode Selection Prepare Configuration Files Virtex ll Pro Development System www xilinx com 77 UG069 v1 0 March 8 2005 1 800 255 7778 7 XILINX 78 Appendix B Programming the Platform FLASH PROM User Area 2 Click on Next and select PROM File in the Prepare Configuration Files option menu shown in Figure B 2 O untitled Configuration Mode iMPACT Edit View Mode Operations Output Help DG X 2 esie ae 12 CE 2 o p 92 Boundary Scan Slave Serial SelectMAP Desktop Configuration Prepare Configuration Files i Nx lwantto create C System ACE
45. SDRAM 24 The XUP Virtex II Pro Development System is equipped with a 184 pin Dual In line Memory Module DIMM socket that provides access up to 2 GB of Double Data Rate SDRAM The DDR SDRAM is an enhancement to the traditional Synchronous DRAM It supports data transfer on both edges of each clock cycle effectively doubling the data throughput of the memory device The DDR SDRAM operates with a differential clock CLK and CLK Z the transition of CLK going high and CLK Z going low is considered the positive edge of the CLK commands address and control signals are registered at every positive edge of the CLK Input data is registered on both edges of the data strobe DOS and output data is referenced to both edges of DOS as well as both edges of CLK A bidirectional data strobe is transmitted by the DDR SDRAM during Reads and by the FPGA DDR SDRAM memory controller during Writes DOS is edge aligned with the data for Reads and center aligned with the data for Writes www xilinx com Virtex ll Pro Development System 00069 v1 0 March 8 2005 Using the DIMM Module DDR SDRAM XILINX Read and Write accesses to the DDR SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence Accesses begin with the registration of an Active command which is followed by a Read or Write command The address bits registered coincident with the Read or Write command
46. VOA 96 Por lt PTT lt Peo 12 02 1 1 02 6L 1 1 2 5 2 oa A 5 _________ gt t Yl 0HOC lt 30019 TAXId LNO Z LNO HONAS dWOO VDA 1no v9 9308 1n0 V9 LNO v9 73118 LNO 1no v9 23018 1no v9 18018 LNO 03118 1no v9 1N33H9 LNO 9N33H5 1nO VIA SN33H5 1nO LNO N33H5 1nO VIA ZN33H5 1nO IN33H5 LNO 1 VDA 2084 1no v9A 9038 LNO 1n0 V9 vase LNO V9A SAY LNO 1no v9 LNO V9A 100 XSGA Output Figure 2 11 Virtex ll Pro Development System www xilinx com 36 06069 v1 0 March 8 2005 Using the XSGA Output XILINX Table 2 6 lists the Verilog parameter values and the DCM settings for various XSGA output formats Note The highlighted settings are exact VESA settings the others are approximations Table 2 6 DCM and XSGA Controller Settings for Various XSGA Formats Pixel DCM Verilog Horizontal Timing Parameters Clock Settings H Active HSynch HBP H Total MHz M D Pixels Pixels Pixels Pixels Pixels 640 x 480 60 Hz 25 00 1 4 640 16 96 48 800 640 x 480 72 Hz 31 25 5 16 640 24 40 128 832 640 x 480 75 Hz 3
47. and identify the Boundary Scan as shown in Figure C 3 G Untitled Configuration Mode iMPACT Edit View Mode Operations Output Help 0 s H e EE E 2 22 0 Boundary Scan Slave Serial SelectMAP Desktop Configuration x 8 Automatically connectto cable and identify Boundary Scan chain C Enter a Boundary Scan Chain Back Finish Cancel Help Figure 3 Boundary Scan Mode Selection Automatically Connect to the Cable and Identify the JTAG Chain 6 Click on Finish and the iMPACT software then interrogates the system and reports that there are at least three devices in the JTAG chain The first device is the XCF32P PROM the second device is the System ACE controller and the third device is the Virtex II Pro FPGA Any additional devices shown in the JTAG chain reside on optional expansion boards 7 Navigate to the directory where you saved the V2Pro BIST mcs file Select this file as the Configuration file for the XCF32P PROM the first device in the JTAG chain identified by iMPACT as shown in Figure C 4 Click on the Open button 90 www xilinx com Xilinx University Program Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 5 XILINX G untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help x 2 20 P Boundary Scan Slave Desktop Configurat
48. and the new User configuration is transferred to the FPGA 86 www xilinx com Virtex ll Pro Development System 1 800 255 7778 UGO69 v1 0 March 8 2005 7 XILINX Appendix C Restoring the Golden FPGA Configuration The Virtex II Pro Development System contains an XCF32P Platform FLASH PROM that is used to contain a known Golden configuration and a separate User configuration These two FPGA configurations are supported by the design revisioning capabilities of the Platform FLASH PROMs The Golden configuration is stored in Revision 0 and is write erase protected and the User configuration is stored in Revision 1 Programming of the XCF32P Platform FLASH PROM is supported by iMPACT v6 3 01i or later download software using Boundary Scan IEEE 1149 1 IEEE 1532 mode from either the embedded Platform Cable USB 78 or the cable connection 727 The latest Golden configuration file can be obtained from the XUP Virtex II Pro Development System support Web site at http www xilinx com univ xup2vp html This configuration file is used to verify the proper operation of the complete system 1 Download the V2Pro BIST zip file and extract the files to a directory of your choice The ZIP file contains two files V2Pro BIST mcs the data file that will be loaded into the PROM and XUP V2Pro BIST cfi afilethat describes the design revision structure in the PROM
49. by the pull up resistor So both sections of the signal are high but at different voltage levels If the FPGA actively pulls the signal low the MOS FET begins to conduct and pulls the peripheral side low as well If the peripheral side pulls the signal low the FPGA side is initially pulled low via the drain substrate diode of the MOS FET After the threshold is passed the MOS FET begins to conduct and the signal is further pulled down via the conducting MOS FET Table 2 18 identifies the PS 2 signal connections to the FPGA Table 2 18 Keyboard Mouse and RS 232 Connections Signal Direction FPGA Pin I O Type Drive Slew IKBDCLOCK WO AG OTL 8mA SLOW KBD DATA I O AGI LVTTL 8 mA SLOW MOUSE CLOCK I O AD6 LVTTL 8 mA SLOW MOUSE DATA AD5 LVTIL 8 mA SLOW RS232 TX DATA LVCMOS25 8 mA SLOW RS232_RX_DATA I AJ8 LVCMOS25 RS232 DSR OUT AD10 LVCMOS25 8mA SLOW RS232_CTS_OUT AE8 LVCMOS25 8mA SLOW RS232 RTS IN I AK8 LVCMOS25 Using the Fast Ethernet Network Interface The 10 100 Ethernet is a network protocol defined by the IEEE 802 3 standard which includes 10 Mb s Ethernet and 100 Mb s Ethernet The Virtex II Pro Development System has been designed to support Internet connectivity using an Ethernet connection 62 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the Fast Ethernet Network Interfa
50. different capacity FPGAs be used on the Virtex II Pro Development System with no change in functionality Table 1 1 lists the Virtex II Pro device features Table 1 1 XC2VP20 and XC2VP30 Device Features Features 2 20 XC2VP30 Slices 9280 13969 Array Size 56 x 46 80 x 46 Distributed RAM 290 Kb 428 Kb Multiplier Blocks 88 136 Virtex ll Pro Development System www xilinx com 15 06069 v1 0 March 8 2005 XILINX Chapter 1 Virtex ll Pro Development System Table 1 1 XC2VP20 and XC2VP30 Device Features Continued Features XC2VP20 XC2VP30 Block RAMs 1584 Kb 2448 Kb DCMs 8 8 PowerPC RISC Cores 2 2 Multi Gigabit Transceivers 8 8 Figure 1 3 identifies the I O banks that are used to connect the various peripheral devices to the FPGA AC97 Audio SXGA port 10 100 Ethernet 256M x 64 72 DDR SDRAM DIMM MODULE EXPANSION CONNECTORS OVER VOLTAGE CLAMPS LEDs amp SWITCHES PS 2 KBD amp MOUSE PUSH BUTTONS RS 232 06069 03 012105 Figure 1 3 VO Bank Connections to Peripheral Devices Power Supplies and FPGA Configuration 16 The XUP Virtex II Pro Development System is powered from a 5V regulated power supply On board switching power supplies generate 3 3V 2 5V and 1 5V for the FPGA and peripheral components and linear regulators power the MGTs The board has provisioning for current measurement for all of the FPGA d
51. expansion headers C449 tenn 1641 m o a VIRTEX II PRO ear DEVELOPMENT SYSTEM Figure 2 14 Expansion Headers XUP Virtex ll Pro Development System UGO69 v1 0 March 8 2005 44 www xilinx com Using the Expansion Headers and Digilent Expansion Connectors 3 XILINX In addition to the two low speed expansion connectors a single 100 pin high speed connector is also provided This connector provides 40 single ended user I Os or 34 differential pairs with additional clock resources These signals are not shared with any other connector Table 2 17 provides the pinout information The front mounted Digilent expansion connectors low speed and high speed provide the capability of extending the JTAG based configuration bitstream to the attached peripheral cards if required For pinout information on the Digilent peripheral boards that are compatible with the XUP Virtex II Pro Development System consult the Digilent Web site at http www digilentinc com Note Table 2 10 through Table 2 16 the power rails available on the expansion headers and connectors are color coded so they can be easily located in the pinout tables Table 2 10 Top Expansion Header Pinout Pin Signal 1 VCC2V5 _ _ _ 3 VCC2V5 _ _ _ 5 VCC3V3 _ J5 3 16 3 _ 7 VCC3V3 _ J5 3 16 3 _ 9 VCC3V3 _ J5
52. or third party tools CPU TCK CPU TDI CPU TDO 15 1 Bur 16 2 GND CPUTRST 3 3V 0069 15 082404 CPU TMS CPU HALT 2 Figure 2 15 CPU Debug Connector Pinouts The JTAG debug resources are not hardwired to specific pins and are available for attachment in the FPGA fabric making it possible to route these signals to whichever FPGA pins the user prefers to use The signal pin connections used on the XUP Virtex II Pro Development System are identified in Table 2 17 along with the recommended I O characteristics Level shifting circuitry is provided for all signals to convert from the 3 3V levels at the connector to the 2 5V levels at the FPGA Table 2 17 CPU Debug Port Connections and CPU Reset Signal Direction FPGA Pin Type DRIVE Slew PROC RESET Z I 5 CPU 16 525 12 SLOW CPU TDI I AF15 LVCMOS25 CPU_TMS I AJ16 LVCMOS25 CPU 15 LVCMOS25 CPU TRST I AC21 LVCMOS25 _ CPU_HALT_Z I AJ23 LVCMOS25 The RESET RELOAD pushbutton SW1 provides two different functions depending on how long the switch is depressed If the switch is activated for more than 2 seconds the Virtex lI Pro Development System undergoes a complete reset and reloads the selected configuration If however the switch is activated for less than 2 seconds a Virtex ll Pro Development System www
53. pending Xilinx Inc does not represent that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2005 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Virtex ll Pro Development System UGO69 v1 0 March 8 2005 The following table shows the revision history for this document Version Revision 03 08 05 1 0 Initial Xilinx releas
54. port used on the XUP Virtex II Pro Development System The implementation of the PS 2 mouse port is identical except for the signal names and the part reference designator The bidirectional level shifter shown in Figure 2 18 is used to interconnect two sections of the PS 2 port each section with a different power supply voltage and different logic levels The level shifter for each signal consists of one discrete N channel enhancement MOS FET The gate of the transistor must be connected to the lowest supply voltage VCC3V3 the source connects to the signal on the lower voltage side and the drain connects to the signal on the higher voltage side Virtex ll Pro Development System www xilinx com 61 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System lt VCC3V3 BIDIRECTIONAL LEVEL VCC5VO gt SHIFTER R105 R106 2 0 R107 3K3 lt lt KBD_CLOCK 153 HZ0805E601R 00 T ny 154 HZ0805E601R 00 UPPER STACKED_PS2_6PIN 442 470PF 470PF Q 21 5 GND 2 21 5 00069 18 101804 Figure 2 18 PS 2 Serial Port Implementation If no device is actively pulling the signal low the pull up resistor pulls up the signal on the FPGA side The gate and source of the MOS FET are both at the same potential and the MOS FET is not conducting This allows the signal on the peripheral side to be pulled up
55. should be a 2 pixel black stripe This test makes sure that all color channels can be driven individually and in groups Additional Hardware Required external power supply SVGA display with cable capable of showing 640 x 480 at 60 Hz image Test Procedure 1 Set the CONFIG SOURCE PROM VERSION DIP switch SW9 with both of the switches up or closed 2 Plugin the external 5V power supply and turn on the board by sliding SW11 up towards the ON label LEDs D14 GOLDEN CONFIG D19 PROM CONFIG and D4 DONE should be on 3 Connect the SVGA display to the SVGA output connector J13 Seven distinct color bars should be visible in the middle of the display with a black stripe between each color 100 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Processor Based Tests XILINX Silicon Serial Number and PS 2 Serial Port Test This test verifies the operation of the two PS 2 ports as well as the one wire interface to the Silicon Serial Number The board serial number is displayed on the SVGA display along with the key that was pressed on the 5 2 connected keyboard A separate field on the SVGA display is used for each of the PS 2 ports Additional Hardware Required external power supply SVGA display with cable capable of showing a 640 x 480 at 60 Hz image PC keyboard Test Procedure 1 Set the CONFIG SOURCE PROM VERSI
56. with a stereo power amplifier TPA6111A made by Texas Instruments The AC97 compliant audio CODEC is widely used as the audio system in PCs and MACS ensuring availability of drivers for these devices The LM4550 audio CODEC supports the following features Greater than 90 dB dynamic range e 18 bit ZA converter architecture e 18 bit full duplex stereo CODEC e Four analog line level stereo inputs one is used on the Virtex II Pro Development System e Two analog line level stereo outputs e Mono MIC input with built in 20 dB preamp selectable for two sources one used e VREF OUT reference voltage provides bias current for Electret microphones Power management support e Full duplex variable sample rates from 4 kHz to 48 kHz in 1 Hz increments Virtex ll Pro Development System www xilinx com 39 06069 v1 0 March 8 2005 XILINX 40 Chapter 2 Using the System e Independently adjustable input volume controls with mute and a maximum gain of 12 dB and attenuation of 34 5 dB in 1 5 dB steps enhancement PC Beep tone input passthrough to Line Out The TPA6111A audio power amplifier supports the following features e Fixed Gain Stereo Power Amplifier delivers 150 mW per channel into 16Q e Click and Pop suppression The National Semiconductor LM4550 uses 18 bit Sigma Delta A Ds and D As providing 90 dB of dynamic range The implementation on this board shown in Figure 2
57. xilinx com 59 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System processor reset pulse of 100 microseconds is applied to the PROCESSOR RESET Z signal The RESET RELOAD circuit is shown in Figure 2 16 FPGAVINT R162 R163 154 OHM 1 PROCESSOR RESET 2 gt gt RESET Z 0 1 RESET RELOAD E an ug069 16 021505 Figure 2 16 RELOAD and CPU RESET Circuit Using the Serial Ports 60 Serial ports are useful as simple low speed interfaces These ports can provide communication between a Host machine and a Peripheral machine or Host to Host communications The XUP Virtex II Pro Development System provides two different types of serial ports a single 5 232 port and two 5 2 ports RS 232 standard specifies output voltage levels between 5V to 15V for a logical 1 and 5V to 15V for a logical 0 Inputs must be compatible with voltages in the range 3V to 15V for a logical 1 and 3V to 15V for a logical 0 This ensures that data is correctly read even at the maximum cable length of 50 feet These signaling levels are outside the range of voltages that can be supported by the Virtex II Pro family of FPGAs requiring the use of a transceiver The connector is a DCE style that allows the use of a straight through 9 pin serial cable to connect to the DTE style serial port connector available on most personal computers and workstations A null modem cable
58. 1 32 GND J5 1J6 1 34 GND J5 1J6 1 36 GND J5 1J6 1 38 GND J5 1J6 1 40 GND J5 1 J6 1 42 GND J5 1 6 1 50 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the Expansion Headers and Digilent Expansion Connectors Table 2 12 Lower Middle Expansion Header Pinout Continued XILINX Pin Signa Is EXPPi OType 44 GND J5 1J6 1 46 GND 5 J5 1J6 1 48 GND J5 1 J6 1 50 GND J5 1J6 1 52 GND 75 1761 54 GND J5 1J6 1 2 56 GND J5 1J6 1 58 GND J5 1J6 1 60 GND _ J5 1J6 1 Table 2 13 Bottom Expansion Header Pinout Pin Signal Pin EXPRin 1O Type 1 VCC5VO 15 2 16 2 3 VCC5VO J5 2 J6 2 5 J5 3 J6 3 7 15 3 6 3 9 15 3 6 3 11 EXP IO 60 Y2 J6 18 LVTTL 13 EXP IO 61 2 16 21 LVTIL 15 EXP IO 62 V7 J6 20 LVTIL 17 EXP IO 63 V8 J6 23 LVTIL 19 EXP IO 64 W3 J6 22 LVTTL 21 EXP IO 65 WA J6 25 LVTTL 23 EXP IO 66 AAI 16 24 LVTTL 25 EXP IO 67 1 16 27 LVTIL 27 EXP IO 68 W5 J6 26 LVTTL 29 EXP IO 69 W6 J6 29 31 EXP IO 70 Y4 16 28 LVTIL 33 EXP IO 71 Y5 J6 31 LVTIL 35 EXP IO 72 AA3 J6 30 LVTIL 37 EXP IO 73 4 16 33 LVTIL Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 51 XILINX Chapter 2 Using the System Tab
59. 1 46 15 1 161 www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 Using the Expansion Headers and Digilent Expansion Connectors XILINX Table 2 10 Top Expansion Header Pinout Continued Pin Signal Exp pin lO Type 48 GND 15 1 16 1 50 GND J5 1J6 1 52 GND J5 1J6 1 54 a 1 161 5 56 GND J5 1J6 1 58 15 1 16 1 60 GND _ J5 1J6 1 Table 2 11 Upper Middle Expansion Header Pinout Pin Signa Pin EXP pin OType 1 VCC5VO E J5 2J6 2 8 VCC5VO 5 15 2 16 2 5 VCC3V3 J5 3 16 3 7 VCC3V3 5 3 J6 3 9 VCC3V3 5 3 16 3 11 EXP IO 20 P8 J5 16 LVTTL 13 EXP IO 21 P7 J5 17 LVTTL 15 EXP IO 22 4 5 18 17 EXP IO 23 N3 5 19 LVTTL 19 EXP IO 24 P3 J5 20 LVTTL 21 EXP IO 25 P2 J5 21 LVTTL 23 EXP IO 26 R8 5 22 LVTTL 25 EXP IO 27 R7 5 23 LVTTL 27 EXP IO 28 P5 J5 24 LVTTL 29 EXP_IO_29 P4 J5 25 LVTTL 31 EXP_IO_30 R2 J5 26 LVTTL 33 EXP IO 31 T2 5 27 35 EXP IO 32 R6 5 28 37 EXP IO 33 R5 5 29 LVTTL 39 EXP IO 34 R4 J5 30 LVTTL 41 EXP_IO_35 R3 J5 31 LVTTL Virtex ll Pro Development System www xilinx com 47 06069 v1 0 March 8 2005 XILINX 48 Chapter 2 Using the System
60. 1 25 5 16 640 18 96 42 796 640 x 480 85 Hz 35 71 5 14 640 32 48 108 828 800 x 600 60 Hz 40 00 4 10 800 40 128 88 1056 800 600 72 Hz 50 00 1 2 800 56 120 64 1040 800 x 600 75 Hz 50 00 1 2 800 16 80 168 1064 800 x 600 85 Hz 55 00 11 20 800 32 64 144 1040 1024 768 60 Hz 65 00 13 20 1024 24 136 160 1344 1024 x 768 72 Hz 75 00 15 20 1024 16 96 172 1308 1024 768 75 Hz 80 00 8 10 1024 24 96 184 1328 1024 x 768 Q 85 Hz 95 00 19 20 1024 48 96 208 1376 1280 x 1024 9 60 Hz 110 00 11 10 1280 52 120 256 1708 1280 x 1024 72 Hz 130 00 13 10 1280 16 144 248 1688 1280 1024 9 75 Hz 135 00 27 20 1280 16 144 248 1688 1280 1024 85 Hz 150 00 3 2 1280 40 144 224 1688 1200 x 1600 60 Hz 160 00 16 10 1600 56 192 296 2144 1200 1600 70 Hz 180 00 18 10 1600 40 184 256 2080 Pixel DCM Verilog Vertical Timing Parameters Clock Settings y Active VSynch VBP V Total MHz M D Pixels Pixels Pixels Pixels Pixels 640 x 480 60 Hz 25 00 1 4 480 9 2 29 520 640 480 72 Hz 31 25 5 16 480 10 3 29 522 640 480 75 Hz 31 25 5 16 480 11 2 31 524 640 x 480 85 Hz 35 71 5 14 480 1 3 23 507 800 x 600 60 Hz 40 00 4 10 600 1 4 23 628 800 x 600 72 Hz 50 00 1 2 600 37 6 23 666 Virtex ll Pro Development System www xilinx com 37 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Table 2 6 DCM and XSGA Controller Settings for Various XSGA Formats Continued
61. 10 Figure D 17 FIFO Loopback Test 110 Figure D 18 Game Sounds Test Completion 111 Figure D 19 System ACE Test 111 Figure D 20 DDR SDRAM Test Completion 113 Figure D 21 Confirming Start of the Expansion Port Walking Ones Test 114 Appendix E User Constraint Files UCF Appendix F Links to the Component Data Sheets 06069 v1 0 March 8 2005 www xilinx com XUP Virtex ll Pro Development System Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 Tables Chapter 1 Virtex ll Pro Development System Table 1 1 XC2VP20 and XC2VP30 Device Features 15 Chapter 2 Using the System Table 2 1 System Configuration Status 22 Table 2 2 Clock Connections 050224 Re RI ete E e rr REEF 23 Table 2 3 SPD EEPROM Contents 27 Table 2 4 Qualified SDRAM Memory Modules 30 Table 2 5 DDR SDRAM Connections 30 Table 2 6 DCM and XSGA Controller Settings for Various XSGA Formats 37 Table 2 7 XSGA Output 38 Table 2 8 AC97 Audio CODEC Connectio
62. 12 allows for full duplex stereo A D and D A with one stereo input and two mono inputs each of which has separate gain attenuation and mute control The mono inputs are a microphone input with 2 2V bias and a beep tone input from the FPGA The BEEP_TONE_IN TTL level is applied to both outputs even if the CODEC is held in reset to allow test tones to be heard The CODEC has two stereo line level outputs with independent volume controls One of the line level outputs drives the audio output connector and the second line level output drives the on board power amplifier shown in Figure 2 13 The power amplifier is capable of producing 150 mW of continuous power per channel into 16 loads such as headphones The assertion of the AUDIO AMP SHUTDOWN signal by the CODEC causes the audio power amplifier to turn off The TPA6111A audio power amplifier contains circuitry to minimize turn on transients that is click or pops Turn on refers to either power supply turn on or the device coming out of CODEC controlled shutdown When the device is turning on the amplifiers are internally muted until the bypass pin has reached half the supply voltage The turn on time is controlled by C9 The power amplifier was included to support two output modes line out mode and power amp output mode The line level output attenuation is controlled by the CODEC volume control register 04h and the power amp output attenuation is controlled by CODEC volume control regist
63. 2 iMPACT Cable Selection Drop Down Menu 72 Figure A 3 iMPACT Cable Communication Setup Dialog 73 Figure 4 Initializing the 74 Figure 5 Properly Identified JTAG Configuration Chain 75 Figure A 6 Assigning Configuration Files to Devices in the JTAG Chain 75 Figure 7 Assigning a Configuration File to the FPGA 76 06069 v1 0 March 8 2005 www xilinx com Virtex ll Pro Development System Figure 8 Programming the 76 Appendix B Programming the Platform FLASH PROM User Area Figure B 1 Operation Mode Selection Prepare Configuration Files 77 Figure B 2 Selecting PROM 78 Figure B 3 Selecting a PROM with Design Revisioning Enabled 79 Figure B 4 Selecting an XCF32P PROM with Two Revisions 79 Figure B 5 Adding a Device 80 Figure B 6 Adding the Design File to Revision 0 80 Figure B 7 iMPACT Startup Clock 81 Figure B 8 Adding the Design File to Revision 1 81 Figure B 9 Generating the MCS
64. 2 2 RUE AREA eae Rie awed 137 DDR SDRAM Modules EC HC ERR E ORAL Da 137 Audio Processing vii 4 C ERR RR o s 138 XSGA Video DUIpUE ERR ie EROR Roe ARE RECEN REM TREE DR 138 Ethernet Networking iac og dc de n e OE ACE EA ITE ASESOR a 138 Power Supplies ie ka dra k ka be a See ed e add deb deed 138 06069 v1 0 March 8 2005 www xilinx com XUP Virtex ll Pro Development System Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 Figures Chapter 1 Virtex ll Pro Development System Figure 1 1 Virtex II Pro Development System Block Diagram 14 Figure 1 2 Virtex II Pro Development System Board Photo 15 Figure 1 3 Bank Connections to Peripheral Devices 16 Chapter 2 Using the System Figure 2 1 Typical Switching Power Supply 19 Figure2 2 MGT POWER deci e ERI eee oe dete deeds 20 Figure 2 3 Configuration Data 22 Figure 2 4 External Differential Clock Inputs 24 Figure 2 5 Alternate Clock Input 24 Figure 2 6 Definition of Start and Stop Conditions 25 Figure 2 7 Acknowledge Response from Receive
65. 255 7778 7 XILINX Appendix E User Constraint Files UCF 2222222422224 E Dd bd Ltd ee bd Ld bd m z z z z zz 4 Ej Dd Dd Ltd Ed b bd m Ld m 222222222424 Dd Ltd Ed Dj bd bd Dd m 2222222424222 E Dd bd bd Ed Dd bd Dd bd EJ 5 z 2 Ej 3 5 5 5 5 5 2 2 3 5 5 5 5 2 5 5 5 El 2 5 El 5 5 Ej gi gn gi SI SI SI SI i ai ai gi gI gI 51 SI SI Si SI ai e gi gI a n Si en gi G i e e gI Si SI SI SI SI en S Si G G DRAM DOS 3 LOC P29 DRAM DM 3 LOC T22 DRAM DQ 31 LOC N28 DRAM DQ 30 LOC N27 DRAM DQ 29 LOC P24 DRAM DQ 28 LOC 23 DRAM DQ 27 LOC P30 DRAM DQ 26 LOC M28 DRAM DQ 25 LOC M27 DRAM DQ 24 LOC R22 DRAM DQS 2 LOC M30 DRAM DM 2 LOC w29 DRAM DQ 23 LOC K28 DRAM DQ 22 LOC K27 DRAM DQ 21 LOC N24 DRAM DQ 20 LOC N23 DRAM DQ 19 LOC 129 DRAM DQ 18 LOC K29 DRAM DQ 17 LOC J28 DRAM DO 16 LOC J27 DRAM DOS 1 LOC 729 DRAM DM 1 LOC V29 DRAM DQ 15 LOC H28 DRAM DQ 14 LOC H27 DRAM DQ 13 LOC L24
66. 3 16 3 _ 11 EXP IO 0 K2 LVTTL 13 EXP IO 1 L2 LVTTL 15 EXP IO 2 N8 LVTTL 17 EXP IO 3 N7 LVTTL 19 EXP IO 4 K4 LVTTL 21 EXP IO 5 K3 LVTTL 23 EXP IO 6 L1 LVTTL 25 EXP IO 7 M1 LVTTL 27 EXP IO 8 N6 J5 4 LVTTL 29 EXP IQ 9 N5 J5 5 LVTTL 31 EXP IO 10 L5 J5 6 LVTTL 33 EXP IO 11 7 LVTTL 35 EXP IO 12 M2 J5 8 LVTTL 37 EXP IO 13 N2 J5 9 LVTTL 39 EXP IO 14 9 J5 10 LVTTL 41 EXP IO 15 R9 J5 11 LVTTL 43 EXP IO 16 M4 J5 12 LVTTL Virtex ll Pro Development System www xilinx com 45 06069 v1 0 March 8 2005 XILINX 46 Chapter 2 Using the System Table 2 10 Top Expansion Header Pinout Continued Pin Signa pin Exp pin Type 45 EXP_IO_17 M3 15 13 47 EXP IO 18 N1 J5 14 LVTTL 49 EXP IO 19 P1 5 15 LVTTL 51 VCC3V3 5 3 16 3 53 VCC3V3 5 3 6 3 55 VCC3V3 5 3 6 3 57 VCC2V5 59 VCC2V5 5 2 GND 1161 4 J5 1J6 1 E 6 GND J5 1 J6 1 8 GND J5 1 J6 1 10 e J5 1 J6 1 12 15 1 161 14 GND J5 1 J6 1 16 GND 1161 5 18 J5 1 J6 1 20 GND 15 1 161 F 22 GND gt J5 1J6 1 E 24 GND J5 1J6 1 26 J5 1J6 1 28 15 1 161 30 J5 1 J6 1 32 15 1 161 u 34 GND J5 1 161 36 GND J5 1 J6 1 38 GND J5 1 J6 1 40 GND J5 1J6 1 42 15 1 161 2 44 116
67. 3 Year of manufacture BCD 94 Week of manufacturer BCD 95 98 Module serial number 99 127 Reserved 128 255 User defined contents The DIMM module is supplied with three differential clocks These three clock signals are matched in length to each other and the DDR SDRAM feedback signals to allow for fully synchronous operation across all banks of memory The DDR SDRAM clocks are driven by Double Data Rate DDR output registers connected to a Digital Clock Manager DCM with an optional external feedback connection The DDR SDRAM controller logic is described 05425 PLB Double Data Rate DDR Synchronous DRAM SDRAM Controller www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 Using the DIMM Module DDR SDRAM XILINX The Xilinx PLB DDR SDRAM controller is a soft IP core designed for Xilinx FPGAs that support different CAS latencies and memory data widths set by design parameters The DDR SDRAM controller logic instantiates DDR input and output registers on the address data and control signals so the clock to output delays match the clock output delay The DDR SDRAM clocking structure as shown in Figure 2 10 is a simplified version of the clocking structure mentioned in 05425 EDK DCM CORE am CLE L dj ea al m d adc ice cc D w G 100 Mhz SYS clock
68. 5 LVTTL 12 EXP IO 54 W1 13 39 LVTTL 14 EXP IO 56 U7 18 43 16 EXP IO 58 V5 18 47 18 EXP IO 60 Y2 74 11 LVTTL 20 EXP IO 62 V7 J4 15 LVTTL 22 EXP IO 64 W3 4 19 LVTTL 24 EXP IO 66 AAI JA 23 LVTTL 26 EXP IO 68 W5 J4 27 LVTTL 28 EXP IO 70 Y4 JA 31 LVTTL www Xilinx com 55 XILINX Chapter 2 Using the System Table 2 15 Right Digilent Expansion Connector Pinout Continued PIN Signal pin HeaderPin 30 EXP IO 72 JA 35 LVTTL 32 EXP IO 74 W7 JA 39 LVTTL 34 EXP IO 74 AB3 4 43 36 JIAG EXP SEL LVTTL 38 G7 40 TDO F5 LVTTL Table 2 16 High Speed Digilent Expansion Connector Pinout d Signal jos 01 VCC3V3 A02 VCC3V3 A03 FPGA TMS 04 HS EXP SEL 05 HS EXP 06 HS IO 1 AF6 31P 3 LVTTL A07 HS IO 2 AE5 31N_3 LVTTL 08 HS IO 3 AB8 32P_3 LVTTL 09 HS IO 4 AB7 32N 3 LVTTL A10 HS IO 5 AE4 33P_3 LVTTL All HS_IO_6 AE3 33N_3 LVTTL A12 HS IO 7 3 LVTTL A13 HS IO 8 3 LVTTL A14 HS IO 9 35P 3 LVTTL A15 HS IO 10 5 35 3 LVTTL A16 HS IO 11 AF2 36P 3 LVTTL A17 HS IO 12 AF1 36N 3 LVTTL A18 HS IO 13 AD4 37P 3 LVTTL A19 HS IO 14 AD3 37 _3 LVTTL A20 HS IO 15 8 38P 3 LVTTL A21 HS IO 16 7 38N 3 LVTTL A22 HS
69. 8 Sound video and game controllers System devices Universal Serial Bus controllers Figure 1 Device Manager Cable Entry H a a a a amp EH EH EH EH There is no difference between the embedded Platform Cable USB implementation and the standalone Platform Cable USB hardware The host computer operating system and iMPACT reports the attached cable as the standalone version The embedded Platform Cable USB can be designated as the active configuration cable by selecting Output Cable Setup from the iMPACT tool bar as shown in Figure A 2 8 Untitled Configuration Mode iMPACT Edit View Mode Operations Output Help 11 08 amp 3 Cable Auto Connect Cable Setup Cable Reset Gable Disconnect Disconnect All Cables SVF File 4 STAPL File a Kove File Figure A 2 Cable Selection Drop Down Menu 72 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 XILINX When the Cable Communications Setup dialog box is displayed the Communications Mode radio button must be set to Platform Cable USB as shown in Figure A 3 If no USB host is available then select Parallel IV attach a cable to J27 Cable Communication Setup mE 2 m Communication Mode C Pa
70. C A8 NET VGA COMP SYNCH LOC G12 NET VGA OUT PIXEL CLOCK LOC H12 NET VGA OUT RED 7 LOC H10 NET VGA OUT RED 6 LOC C7 NET VGA OUT RED 5 LOC D7 NET VGA OUT RED 4 LOC 10 NET VGA OUT RED 3 LOC F9 NET VGA OUT RED 2 LOC G9 NET VGA OUT RED 1 LOC H9 NET VGA OUT RED 0 LOC G8 NET VGA OUT GREEN 7 LOC 11 NET VGA OUT GREEN 6 LOC G11 NET VGA OUT GREEN 5 LOC 11 NET VGA OUT GREEN 4 LOC C8 NET VGA OUT GREEN 3 LOC D8 NET VGA OUT GREEN 2 LOC D10 NET OUT GREEN 1 LOC E10 NET VGA OUT GREEN O LOC G10 NET VGA OUT BLUE 7 LOC E14 NET VGA OUT BLUE 6 LOC D14 NET VGA OUT BLUE 5 LOC D13 NET VGA OUT BLUE 4 LOC C13 NET VGA OUT BLUE 3 LOC 715 NET VGA OUT BLUE 2 LOC H15 NET VGA OUT BLUE 1 LOC E15 NET VGA OUT BLUE O LOC D15 NET VGA OUT BLUE IOSTANDARD LVTTL NET VGA OUT GREEN IOSTANDARD LVTTL NET VGA OUT RED IOSTANDARD LVTTL NET VGA OUT BLUE SLEW SLOW NET VGA OUT GREEN SLEW SLOW NET VGA OUT RED SLEW SLOW NET VGA OUT BLUE DRIVE 8 NET VGA OUT GREEN DRIVE 8 NET VGA OUT RED DRIVE 8 NET VGA VSYNCH IOSTANDARD LVTTL NET VGA OUT PIXEL CLOCK IOSTANDARD LVTTL NET VGA HSYNCH IOSTANDARD LVTTL NET VGA OUT BLANK Z IOSTANDARD LVTTL NET VGA CO
71. C AH9 NET CF MPD 10 LOC 10 NET CF MPD 11 LOC NET CF MPD 12 LOC AD12 NET CF MPD 13 LOC 12 NET CF MPD 14 LOC AG10 NET CF MPD 15 LOC AF10 NET CF MPD IOSTANDARD LVCMOS25 NET CF MPD DRIVE 8 NET CF MPD SLEW SLOW NET CF MP CE 2 LOC 16 NET CF MP OE 7 LOC AD17 NET CF MP WE Z LOC 16 NET CF MPIRQ LOC AD16 NET MPBRDY LOC 16 NET CF MP CE Z IOSTANDARD LVCMOS25 NET CF MP OE Z IOSTANDARD LVCMOS25 NET CF MP WE Z IOSTANDARD LVCMOS25 NET CF MPIRQ IOSTANDARD LVCMOS25 NET CF MPBRDY IOSTANDARD LVCMOS25 NET CF MP CE Z DRIVE 8 NET CF MP OE Z DRIVE 8 NET CF MP WE Z DRIVE 8 NET CF MP CE Z SLEW SLOW NET CF MP OE Z SLEW SLOW NET CF MP WE Z SLEW SLOW EMACI Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 133 7 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE XSGA VIDEO OUTPUT OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET VGA VSYNCH LOC Dil NET VGA HSYNCH LOC NET VGA OUT BLANK Z LO
72. EM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 moun CPU TDO LOC 16 moun CPU TDI LOC AF15 moun CPU TMS LOC 716 CPU TCK LOC AGIS CPU TRST LOC AC21 El el EE pu Ud p pg B 3 T CPU HALT Z LOC AJ23 T PROC_RESET_Z LOC AH5 NET CPU TDO IOSTANDARD LVCMOS25 NET CPU TDI IOSTANDARD LVCMOS25 NET CPU TMS IOSTANDARD LVCMOS25 NET CPU TCK IOSTANDARD LVCMOS25 NET CPU TRST IOSTANDARD LVCMOS25 NET CPU HALT Z IOSTANDARD LVCMOS25 NE 5 d PROC RESET 2 IOSTANDARD LVTTL NET CPU TDO DRIVE 12 NET CPU TDO SLEW SLOW Virtex ll Pro Development System www xilinx com 117 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix E User Constraint Files PINOUT AND IO DRIVE CHARACTERIST OF THE XUP V2PRO DEVELOPMENT SYS n I ED 0 n I ED 1 n I ED 2 z 2 e I ED 3 I ED 0 I ED 1 5 I ED 2 222424 I ED 3 n I ED 0 n I ED 1 I ED 2 n REVISION C PRINTED CIRCUIT BOARD LOC ACA LOC AC3 LOC AA6 LOC 5 IOSTANDARD LVTTL IOSTANDARD LVTTL IOSTANDARD LVTTL IOSTANDARD
73. EW SLOW DE D 3 2 d SSN DATA IOSTANDARD LVTTL SSN DATA DRIVE 8 SSN DATA SLEW SLOW B4 DEP pM 3 d 5 120 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 XILINX PINOUT AND IO DRIVE REVISION C PRINTED CIRCUIT BOARD NET PB ENTER LOC AG5 NET PB UP LOC AH4 NET PB DOWN LOC AG3 NET PB LEFT LOC 1 NET PB RIGHT LOC AH2 NET PB ENTER IOSTANDARD LVTTL NET PB UP IOSTANDARD LVTTL NET PB DOWN IOSTANDARD LVTTL NET PB LEFT IOSTANDARD LVTTL NET PB RIGHT IOSTANDARD LVTTL CHARACTERISTICS FOR OF THE XUP V2PRO DEVELOPMENT SYST Er EM DEC 8 2004 US ER PUSH BUTTONS Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 121 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE UPPER EXPANSION HEADER OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET EXP IO 0 LOC K2 NET EXP IO 1 LOC I2 NET EXP IO 2 LOC N8 NET EXP IO 3 LOC N7 NET EXP IO 4 LOC K4 NET EXP IO 5 LOC K3 NET EXP IO 6 LOC L1 NET EXP IO 7 LOC 1 NET EXP IO 8 LOC N6 NET EXP
74. Erase p 1 override PROGRESS_START Starting Operation Validating chain Boundary scan chain validated successfully Validating chain Boundary scan chain validated successfully 71 Putting device m ISP mode done 1 Erasing device done 1 Erasure completed successfully PROGRESS END End Operation Elapsedtime 30 sec Figure C 6 Transcript Window for the Erase Command 10 Right mouse click on the icon for the XCF32P PROM and select Program from the drop down menu as shown in Figure C7 92 www xilinx com Xilinx University Program Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 5 XILINX 8 untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D S X telg oe s CE E 80 Boundary Scan Slave Serial SelectMAP Deskto Program xc Verify xup v Erase Blank Check Get Device ID Get Device Checksum mf 54 644 Assign New Configuration File Figure C 7 Selecting the Program Command 1 TheiMPACT software responds with a form that allows the user to specify which design revisions are to be programmed and the programming options for the various revisions Select Design Revision Rev 0 and set the Write Protect WP bit to prevent the user from overwriting the Golden configuration Verify that the Operating Mode is set to Slave and the I O Configuration is set to Parallel Mode as shown in Figure C
75. FPGA without the need for expensive external instrumentation Using the JTAG test access port a debug tool can single step the processor and examine the internal processor state to facilitate software debugging This capability complies with standard JTAG hardware for boundary scan system testing External debug mode can be used to alter normal program execution It provides the ability to debug system hardware as well as software The mode supports multiple functions starting and stopping the processor single stepping instruction execution setting breakpoints as well as monitoring processor status Access to processor resources is provided through the CPU Debug Port The 405 JTAG Debug Port supports the four required JTAG signals CPU CPU TMS CPU TDO and CPU TDI It also implements the optional CPU TRST signal The frequency of the JTAG clock signal CPU TCK can range from 0 MHz up to one half of the processor clock frequency The JTAG debug port logic is reset at the same time the system is reset using the CPU TRST signal When CPU TRST is asserted the JTAG TAP controller returns to the test logic reset state 58 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the CPU Debug Port and CPU Reset XILINX Figure 2 15 shows the pinout of the header used to debug the operation of software in the CPU This is accomplished using debug tools such as the Xilinx Parallel Cable IV
76. File PROMFile C Boundary Scan File Figure 2 Selecting PROM File 3 Clickon Next and then select Xilinx PROM with Design Revisioning Enabled using the MCS PROM File Format 4 Givethe PROM File a name of your choice in the location of your choice as shown in Figure B 3 Note Do NOT select Compress Data because the Virtex Il Pro Development System hardware does not support this option www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 5 XILINX untitled Configuration Mode iMPACT File Edit View Mode Operations Output Help 0 x 2 86 22 1401 255 CO P Boundary Scan Slave Serial Desktop Configuration Prepare PROM Files I wantto targeta Xilinx Serial PROM Parallel PROM 8 Xilinx PROM with Design Revisioning Enabled Compress Data PROM File Format MCS UFP C format C EXO CHEX CBN 7 Swan Bits Memory Fill Value 2 Hex Digit PROM File MY DESIGN PROM Location leXPROJECTSWMY DESIGN Back Next Cancel Help Figure B 3 Selecting a PROM with Design Revisioning Enabled 5 Click on Next to bring up the option screen where the type of PROM is specified 6 Select the XCF32P PROM from the drop down men Click on the Add button and specify 2 from the Number of Revisions drop down menu as shown in Figure B 4
77. INX Chapter 2 Using the System Configuring the Power Supplies The XUP Virtex lI Pro Development System supports the independent creation of the power supplies for the core voltage of 1 5V FPGA VINT 2 5V general purpose power I O and or VCCAUX supplies VCC2V5 and 3 3V I O and general purpose power VCC3V3 These voltages are created by synchronous buck switching regulators derived from the 4 5V 5 5V power input provided at the center positive barrel jack power input J26 or the terminal block pair J34 J35 Each of these supplies be disabled through the insertion of jumpers JP2 JP4 and JP6 and the external application of power from the terminal blocks J28 J33 If external power is supplied the associated internal power supply must be disabled through the insertion of JP6 JP2 or JP4 and the associated on board power delivery jumpers JP5 JP1 must be removed The power consumption from each of the on board power supplies can be monitored through the removal of JP5 JP1 or JP3 and the insertion of a current monitor If any of the power supplies are outside the recommended tolerance internally or externally provided the system enters a RESET state indicated by the illumination of the RESET PS ERROR LED D6 and the assertion of the RESET Z signal A typical switching power supply is shown in Figure 2 1 46 m m tour 6 1 m 33V OK ew on ake zan
78. L su aN9 oiany A ano olanv ant ans alanv 35 Ssvaxa _ SN 4437 olanv 4437 ino anv 4 9 a H lt anro 59 so Yo olanv osi ant a y vino YNI J 1H9701any AS Olanv gt 1 z NMOG LnHS P lt NMOGLNHS anv olanv Audio Power Amplifier 2 13 UGO69 v1 0 March 8 2005 Virtex ll Pro Development System www xilinx com 42 Using the LEDs and Switches XILINX The FPGA contains the AC97 controller that provides control information and PCM data on the outbound link and receives status information and PCM data in the inbound link The complete AC97 interface consists of four signals the clock AC97 BIT CLOCK a synchronization pulse AC97 SYNCH and the two serial data links AC97 SDATA IN and AC97 SDATA OUT listed in Table 2 8 The CODEC is held in a reset state until the AUDIO RESET Z signal is driven high by the FPGA overriding a pull down resistor R15 Table 2 8 AC97 Audio CODEC Connections Signal Direction FPGA Pin I O Type Drive Slew 97 SDATA OUT E OTIL 8mA SLOW AC97 SDATA IN I E9 LVTTL 97_5 7 LVTTL 8mA SLOW AC97 BIT CLOCK I F8 LVTIL AUDIO RESET Z LVTTL 8mA SLOW BEEP TONE IN 7 LVTTL 8mA SLOW Using the LEDs and Switches The XUP Virtex II Pro Development System includes four LEDs as visual in
79. LVTTL DRIVE 12 DRIVE 12 DRIVE 12 DRIVE 12 222424 I ED 3 pi I ED 0 5 I ED 1 I ED 2 222424 I ED 3 SLEW SLOW SLEW SLEW SLOW SLOW SLEW SLOW ICS FOR THI 8 2004 USER LEDS Er 118 www xilinx com 1 800 255 7778 XUP Virtex ll Pro Development System 06069 v1 0 March 8 2005 XILINX PINOUT AND IO DRIVE CHARACTERISTICS FOR THE 10 100 ETHI SECTION OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 NET TX DATA 0 LOC J7 NET TX DATA 1 LOC 8 NET TX DATA 2 LOC C1 NET TX DATA 3 LOC C2 NET TX ERROR LOC H2 NET TX CLOCK LOC D3 NET TX ENABLE LOC C4 NET TX DATA IOSTANDARD LVTTL NET TX DATA DRIVE 8 NET TX DATA SLEW SLOW NET TX ERROR IOSTANDARD LVTTL NET TX ERROR DRIVE 8 NET TX ERROR SLEW SLOW NET TX CLOCK IOSTANDARD LVTTL NET TX ENABLE IOSTANDARD LVTTL NET TX ENABLE DRIVE 8 NET TX ENABLE SLEW SLOW NET RX DATA 0 LOC K6 NET RX DATA 1 LOC K5 NET RX DATA 2 LOC JI NET RX DATA 3 LOC
80. MP SYNCH IOSTANDARD LVTTL NET VGA VSYNCH DRIVE 12 NET VGA OUT PIXEL CLOCK DRIVE 12 NET VGA HSYNCH DRIVE 12 NET VGA OUT BLANK Z DRIVE 12 NET VGA COMP SYNCH DRIVE 12 134 www xilinx com 1 800 255 7778 Virtex ll Pro Development System UGO69 v1 0 March 8 2005 XILINX VGA VSYNCH SLEW SLOW VGA OUT PIXEL CLOCK SLEW SLOW VGA HSYNCH SLEW SLOW VGA OUT BLANK 2 SLEW SLOW VGA COMP SYNCH SLEW SLOW Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 1 800 255 7778 135 7 XILINX E E HE E HE HE HE HE HE HE HE HE HE FE HE FE HE FE HE FE HE FE HE FE HE FE HE HE HE HE HE HE SATA 0 Host HE E HE E HE HE FE HE FE HE FE HE FE HE FE HE FE HE FE HE H EE EHE MGT TX RX pads are not directl Rather the MGT itself is plac connect the appropriate pads INST hierarchical path to mgt In addition constrain locatio Align Module This insures cor enable comma align signal See the RocketIO Transceiver SATA 0 HOST GT X0Y1 NST hierarchical path to align H Appendix E User Constraint Files UCF FE HE HE HE HE HE HE HE FE HE FE HE FE HE HE HE E HE HE HE HE HE HE HE HE HE HE HE H H H FE HE HE HE HE HE HE HE FE HE FE HE FE HE HE HE E HE HE HE HE HE HE FE HE HE H HHH y specified in the UCF file ed and the tools automatical
81. ON DIP switch SW9 with both of the switches up or closed 2 Plug in the external 5V power supply and turn on the board by sliding SW11 up towards the ON label LEDs D14 GOLDEN CONFIG D19 PROM CONFIG and D4 DONE should on 3 Connect the SVGA display to the SVGA output connector J13 The 12 digit board serial number should be displayed in the upper text portion of the display 4 Plug in the PC keyboard into the upper PS 2 jack J12 Type any character on the keyboard The typed character should be seen in the MOUSE PORT ASCII CHARACTER field in the upper text portion of the display 5 Plug in the PC keyboard into the lower PS 2 jack 12 any character on the keyboard The typed character should be seen in the KYBD PORT ASCII CHARACTER field in the upper text portion of the display Processor Based Tests The processor based tests exercise the XUP Virtex II Pro Development System functionality most efficiently controlled via software programming These tests use the RS 232 serial interface as the control input and status reporting interface also exercising its functionality in the process Like the hardware based tests the configuration source DIP switches should be set to the PROM and GOLDEN CONFIG settings and the D14 GOLDEN CONFIG LED should be lit after power is applied to the board The user should note that the hardware based tests are active while the processor based t
82. ON SelectMAP GOLDEN LOADING ON OFF ON OFF Select MAP GOLDEN ON OFF ON ON COMPLETED COMPACT FLASH OFF ON OFF OFF LOADING COMPACT FLASH OFF ON OFF ON COMPLETED 22 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Clock Generation and Distribution Table 2 1 System Configuration Status LEDs Continued 3 XILINX LED Status System Status D19 Green D20 Green D14 Amber D4 Red PROM Config CF Config GOLDEN Config Done JTAG USB or PC4 LOADING OFF ON OFF OFF USB or COMPLETED OFF ON OFF ON Clock Generation and Distribution The XUP Virtex II Pro Development System supports six clock sources e 100 MHz system clock Y2 e A75MHz clock 010 for the MGTs operating the Serial Advanced Technology Virtex ll Pro Development System Attachment SATA ports e A dual footprint through hole user supplied alternate clock Anexternal clock for the MGTs J23 J24 A32 MHz clock Y4 for the System ACE interfaces and Aclock from the Digilent high speed expansion module The 75 MHz SATA clock is obtained from a high stability 20 ppm 3 3V LVDSL differential output oscillator and the external MGT clock is obtained from two user supplied SMA connectors The remaining three oscillators are all 3 3V single ended LVTTL sources Each of the oscillators is equipped with a power supply filter to reduce the noise
83. OW VGA OUT GREEN O 2 G10 LVTTL 8mA SLOW VGA OUT GREEN 1 3 E10 LVTTL 8mA SLOW VGA OUT GREEN 4 D10 LVTTL 8mA SLOW VGA OUT GREEN 3 5 8mA SLOW VGA OUT GREEN 4 6 C8 LVTTL 8mA SLOW 38 www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 Using the AC97 Audio CODEC and Power Amp XILINX Table 2 7 XSGA Output Connections Continued 222 video FPGA Signal Direction DAC or Output Pin Type Drive Slew Connector Pin VGA_OUT_GREENJ5 O 7 H11 LVTTL 8mA SLOW VGA OUT GREEN 6 8 G11 LVTTL 8mA SLOW VGA OUT GREEN 7 9 E11 LVTTL 8mA SLOW VGA OUT BLUE 0O 16 D15 LVTTL 8mA SLOW VGA OUT BLUPF 1 17 15 LVTTL 8mA SLOW VGA BLUE 2 18 15 LVTTL 8mA SLOW VGA OUT BLUE 3 19 J15 LVTTL 8mA SLOW VGA OUT BLUE 4 20 C13 LVTTL 8mA SLOW VGA OUT BLUE 5 21 D13 LVTTL 8mA SLOW VGA OUT BLUE 6 22 D14 LVTTL 8mA SLOW VGA_OUT_BLUE 7 O 23 E14 LVTTL 8mA SLOW VGA_OUT_PIXEL_CLOCK O 26 H12 LVTTL 12mA SLOW VGA_COMP_SYNCH O 11 G12 LVTTL 12mA SLOW VGA OUT BLANK Z 10 8 LVTTL 12mA SLOW VGA HSYNCH 13 14 LVTTL 12mA SLOW VGA VSYNCH 13 13 D11 LVTTL 12mA SLOW Using the AC97 Audio CODEC and Power Amp The audio system on the Virtex II Pro Development System consists of a National Semiconductor LM4550 AC97 audio CODEC paired
84. STANDARD LVDS 25 NET MGT CLK N IOSTANDARD LVDS 25 NET EXTERNAL CLOCK P IOSTANDARD LVDS 25 NET EXTERNAL CLOCK N IOSTANDARD LVDS 25 NET N TIMESPEC TS MGT CLK N PERIOD MGT CLK N 13 33 ns HIGH 50 NET MGT CLK P TNM NET MGT CLK P TIMESPEC TS MGT CLK P PERIOD MGT CLK P 13 33 ns HIGH 50 DEFINE THE SYSTEM CLOCKS NET SYSTEM CLOCK LOC AJ15 NET FPGA SYSTEMACE CLOCK LOC 15 NET ALTERNATE CLOCK LOC 16 NET SYSTEM CLOCK IOSTANDARD LVCMOS25 NET FPGA SYSTEMACE CLOCK IOSTANDARD LVCMOS25 NET ALTERNATE CLOCK IOSTANDARD LVCMOS25 NET SYSTEM CLOCK TNM NET SYSTEM CLOCK TIMESPEC TS SYSTEM CLOCK PERIOD SYSTEM CLOCK 10 00 ns HIGH 50 NET FPGA SYSTEMACE CLOCK TNM NET FPGA SYSTEMACE CLOCK TIMESPEC TS FPGA SYSTEMACE CLOCK 31 25 ns HIGH 50 PERIOD FPGA SYSTEMACE CLOCK SSTL2 II i4 DEFINE THE DDR SDRAM CLOCK FEEDBACK LOOP NET CLK FEEDBACK OUT LOC G23 NET CLK FEEDBACK IN LOC C16 NET CLK FEEDBACK OUT IOSTANDARD NET CLK FEEDBACK IN IOSTANDARD SSTL2 II 116 www xilinx com 1 800 255 7778 Virtex ll Pro Development System UGO69 v1 0 March 8 2005 XILINX PINOUT AND IO DRIVE CHARACTERISTICS FOR THE CPU DEBUG SECTION OF THE XUP V2PRO DEVELOPMENT SYST
85. TL 26 EXP IO 30 R2 2 1 LVTTL 28 EXP IO 32 R6 2 35 LVTTL 30 EXP IO 34 2 39 LVTTL 32 EXP IO 36 U1 J2 43 LVTTL 34 EXP IO 38 T5 J2 47 LVTTL 36 EXP IO 40 T3 J3 11 LVTTL 38 EXP IO 42 U2 J3 13 LVTTL 40 EXP IO 44 U7 J3 19 LVTTL Table 2 15 Right Digilent Expansion Connector Pinout ME INS Expansion 1 GND J1 4 EVEN PINS 3 VCC3V3 5 EXP IO 45 T8 J3 21 LVTTL 54 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the Expansion Headers and Digilent Expansion Connectors Table 2 15 Right Digilent Expansion Connector Pinout Continued XILINX Virtex ll Pro Development System 06069 v1 0 March 8 2005 PIN Signal Pin Header Pin OType 7 EXP_IO_47 U5 18 25 9 EXP IO 49 W2 18 29 1 EXP IO 51 U9 18 33 13 EXP IO 53 V4 J3 37 LVTTL 15 EXP_IO_55 1 18 41 LVTTL 17 EXP IO 57 08 18 45 LVTTL 19 EXP IO 59 V6 18 49 LVTTL 21 EXP IO 61 AA2 J4 13 LVTTL 23 EXP IO 63 V8 4 17 LVTTL 25 EXP IO 65 WA JA 21 LVTTL 27 EXP IO 67 ABI JA 25 LVTTL 29 EXP IO 69 W6 JA 29 LVTTL 31 EXP IO 71 Y5 J4 33 LVTTL 33 EXP IO 73 AAA JA 37 LVTTL 35 EXP IO 75 W8 J4 41 LVTTL 37 FPGA_TMS H8 LVTTL 39 LS EXP TDO LVTTL 2 VCC5V0 4 10 46 04 18 23 6 10 48 V2 J3 27 8 EXP IO 50 T9 J3 31 LVTTL 10 EXP IO 52 V3 18 3
86. TL2 II SDRAM 2 138 28 SSTL2 II SDRAM 1 16 AD29 SSTL2 II SDRAM CK1 Z 17 AD30 SSTL2 II SDRAM CK2 76 23 SSTL2 II SDRAM 2 2 75 24 SSTL2 II CLK FEEDBACK G23 LVCMOS25 CLK FEEDBACK I C16 LVCMOS25 SDRAM CKEO 21 26 SSTL2 II SDRAM_CKE1 O 111 R25 SSTL2 II SDRAM RAS Z 154 N29 SSTL2 II SDRAM CAS Z 65 127 SSTL2 II SDRAM WE Z 63 26 SSTL2 II SDRAM 50 2 157 R24 SSTL2 II SDRAM SI Z 158 23 SSTL2 II SDRAM 0 59 26 SSTL2 II SDRAM BA1 52 26 SSTL2 II SDRAM SDA I O 91 AF23 LVCMOS25 SDRAM SCL 92 AF22 LVCMOS25 SDRAM 5 0 NA 181 NA SDRAM SA1 NA 182 NA SDRAM SA2 NA 183 NA Using the XSGA Output 34 The XSGA output on the XUP Virtex II Pro Development System is made up from a triple 8 bit DAC U29 a high density 15 pin D Sub connector J13 and IP placed in the FPGA fabric 53818 video DAC is a low cost DAC tailored to fit graphics and video applications with a maximum pixel clock of 180 MHz The TTL data inputs and control signals are converted into analog current outputs that can drive 25010 37 5Q loads corresponding to a doubly terminated 500 to 75Qload The VGA OUT BLANK 7 input overrides the RGB inputs and blanks the display output This signal is equipped with a pull down resistor R120 to keep the display blanked when the FPGA is not programmed or XSGA output is not required by the user application The XSGA output circuit is shown in Figure 2 11 w
87. Xilinx University Program Virtex ll Pro Development System Hardware Reference Manual 96069 v1 0 March 8 2005 2 XILINX 5 XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex Il Pro Virtex ll EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx XDTV Xinfo XSI XtremeDSP and ZERO are tradema
88. address for the Ethernet interface because this number has not been registered as a valid Ethernet MAC address The Virtex II Pro Development System printed circuit board includes a label that contains the board serial number obtained from the DS2401P Silicon Serial Number as well as a valid Ethernet MAC address that has been registered with the IEEE Xilinx maintains a cross reference list matching the board serial number with the assigned Ethernet MAC address on the XUP Virtex II Pro Development System support Web page Xilinx provides the IP for the 1 Wire interface and application note XAPP198 Synthesizable FPGA Interface for Retrieving ROM Number from 1 Wire Devices describes this interface Table 2 19 10 100 ETHERNET Connections Signal Direction FPGA Pin Type Drive Slew TX DATA 0 O J7 LVTTL 8 mA SLOW TX DATA 1 O J8 LVTTL 8 mA SLOW TX DATA 2 O C1 LVTTL 8mA SLOW TX DATA 3 O C2 LVTTL 8 mA SLOW TX ERROR H2 LVTTL 8 mA SLOW 64 www Xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using System ACE Controllers for Non Volatile Storage XILINX Table 2 19 10 100 ETHERNET Connections Continued Signal Direction FPGA Pin 10 Type Drive Slew TX CLOCK I D3 LVTTL TX ENABLE 8mA SLOW RX DATA 0 I K6 LVTTL RX_DATA 1 I K5 LVTTL DATA 2 Ji LVTTL
89. and RESET Test 98 Additional Hardware Required 98 Test dtu eee e 98 Clock Push Button DIP Switch LED and Audio Amp Test 99 Additional Hardware Required 1 2 99 Test Procedure 7 99 SVGA Gray Scale 100 Additional Hardware Required 1 100 Test Procedure i s quen aa kus ite doe der dee c 100 SVGA Color Output Test eere eee CREE ea 100 Additional Hardware Required 100 Test Procedure gleba Rh a RH EORR e or Pd E Ra eek 100 Silicon Serial Number and PS 2 Serial Port Test 101 Additional Hardware Required 101 520 4 re ted un _ tthe ee 101 Processor Based 101 Additional Hardware Required 102 MGT Serial ATA Test 102 Additional Hardware Required 102 EMAC Web Server
90. ansition of SDRAM SDA when SDRAM SCL is high indicates a stop bit condition terminating the command placing the SPD device into a low power mode SDRAM wm Z NE Z NIVO START BIT STOP BIT UGO69 07 082604 Figure 2 6 Definition of Start and Stop Conditions commands commence with a start bit followed by eight data bits The transmitting device either the bus master or slave releases the bus after transmitting eight bits During the ninth clock cycle the receiver pulses the SDA data signal low to acknowledge that it received the eight bits of data as shown in Figure 2 7 Virtex ll Pro Development System www xilinx com 25 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System SCL FROM MASTER SDA OUTPUT FROM SDA OUTPUT FROM RECEIVER START BIT ACKNOWLEDGE 06069 08 021405 Figure 2 7 Acknowledge Response from Receiver The SPD device always responds with an acknowledge after recognition of a start condition and its slave address 100 If a read command was issued the SPD device transmits eight bits of data releases the SDRAM SDA data line and monitors the SDRAM SDA data line for an acknowledge If an acknowledge is detected and no stop bit is generated by the master the SPD device continues to transmit data If no acknowledge is detected the SPD device terminates further data transmission and waits for the stop bit condition to retur
91. any baud rate in the range of 622 Mb s to 3 125 Gb s per channel Only four of the available eight channels are used on the XUP Virtex II Pro Development System Three channels are equipped with low costs Serial Advanced Technology Attachment SATA connectors and the fourth channel terminates at user supplied Sub Miniature SMA connectors The SATA channels are split into two interface formats two HOST ports J16 J18 and a TARGET port J17 The TARGET port interchanges the transmit and receive differential pairs to allow two XUP Virtex II Pro Development Systems to be connected as a simple network or multiple Virtex II Pro Development Systems to be connected in a ring The SATA specification requires an out of band signalling state that is to be used when the channel is idle This capability is not directly provided by the MGTs Two resistors an FET transistor and two AC coupling capacitors along with special idle state control signals add the out of band IDLE state signaling capability to the MTGs Additional off board hardware can be required to properly interface to generic SATA disk drives Virtex ll Pro Development System www xilinx com 67 06069 v1 0 March 8 2005 5 XILINX 68 Chapter 2 Using the System The fourth MGT channel pair terminates on user supplied SMA connectors J19 22 and can be driven by a user supplied differential clock input pair EXTERNAL CLOCK P and EXTERNAL CLOCK N provided on SMA conne
92. ata CPU Trace and Debug Port The FPGA is equipped with a CPU debugging interface and a 16 pin header This connector can be used in conjunction with third party tools the Xilinx Parallel Cable IV or the Xilinx Platform Cable USB to debug software as it runs on either PowerPC 405 processor core ChipScope Pro can also be used to perform real time debug and verification of the FPGA design ChipScope Pro inserts logic analyzer bus analyzer and Virtual I O low profile software cores into the FPGA design These cores allow the designer to view all the internal signals and nodes within the FPGA including the Processor Local Bus PLB or On Chip Peripheral Bus OPB supporting the PowerPC 405 cores Signals are captured and brought out through the embedded Platform Cable USB programming interface for analysis using the ChipScope Pro Logic Analyzer tool USB 2 Programming Interface The Virtex II Pro Development System includes an embedded USB 2 0 microcontroller capable of communications with either high speed 480 Mb s or full speed 12 Mb s USB hosts This interface is used for programming or configuring the Virtex II Pro FPGA in Boundary Scan IEEE 1149 1 IEEE 1532 mode Target clock speeds are selectable from 750 kHz to 24 MHz The USB 2 0 microcontroller attaches to a desktop or laptop PC with an off the shelf high speed A B USB cable 18 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 7 XIL
93. atform Flash PROM from the JTAG Platform Cable USB interface or the USB interface following the instructions in Appendix B Programming the Platform FLASH PROM User Area 20 www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 Configuring the FPGA 5 XILINX The Platform Flash is normally disabled after the FPGA is finished configuring and has asserted the DONE signal If additional data is made available to the FPGA after the completion of configuration jumper JP9 must be moved from the NORMAL to the EXTENDED position to permanently enable the PROM and allow the FPGA to clock out the additional data using the CLOCK signal The process of loading additional non configuration data into the FPGA is outlined in application note 694 Reading User Data from Configuration PROMs If the CONFIG SOURCE switch is open off or down a lower speed JTAG based configuration from Compact Flash or external JTAG source is selected as the configuration source This is identified to the user through the illumination of the JTAG CONFIG LED D20 The JTAG based configuration can originate from several sources the Compact Flash card cable connection through J27 and a USB to PC connection through J8 the embedded Platform Cable USB interface If a JTAG based configuration is selected the default source is from the Compact Flash port J7 The System ACE controller checks the associated Com
94. ay from Back to Back Random Column Addresses 16 Supported burst lengths 17 Number of banks on SDRAM component 18 CAS latencies supported 19 CS latency 20 WE latency 21 SDRAM module attributes 22 SDRAM attributes 23 SDRAM cycle time tck CAS LATENCY 2 24 SDRAM access time tac CAS LATENCY 2 25 SDRAM cycle time CAS LATENCY 1 26 SDRAM access time tac CAS LATENCY 1 27 Minimum ROW time trp 28 Minimum ROW ACTIVE to ROW ACTIVE trrd Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 27 XILINX 28 Chapter 2 Using the System Table 2 3 SPD EEPROM Contents Continued Byte Description 29 Minimum RAS to CAS delay trcd 30 Minimum RAS pulse width tras 31 Module rank density 32 Command and address setup time tas tcms 33 Command and address hold time tah tcmh 34 Data setup time tds 35 Data hold time tdh 36 40 Reserved 41 Minimum ACTIVE AUTO REFRESH time 42 Minimum AUTO REFRESH to ACTIVE AUTO REFRESH command period 43 Max cycle time 44 skew 45 Max READ HOLD time 46 Reserved 47 DIMM height 48 61 Reserved 62 SPD revision 63 CHECKSUM for bytes 0 62 64 71 Manufacturer s JEDEC ID code 72 Manufacturing location 73 90 Module part number ASCII 91 92 Module revision code 9
95. ccess Controller MAC implemented in the FPGA Each board is equipped with a Silicon Serial Number that uniquely identifies each board with a 48 bit serial number This serial number is retrieved using 1 Wire protocol This serial number can be used as the system MAC address Serial Ports The Virtex lI Pro Development System provides three serial ports a single 5 232 port and two PS 2 ports The RS 232 port is configured as a DCE with hardware handshake using a standard DB 9 serial connector This connector is typically used for communications with a host computer using a standard 9 pin serial cable connected to a COM port The two PS 2 ports could be used to attach a keyboard and mouse to the XUP Virtex II Pro Development System of the serial ports are equipped with level shifting circuits because the Virtex II Pro FPGAs cannot interface directly to the voltage levels required by RS 232 or 5 2 Virtex ll Pro Development System www xilinx com 17 06069 v1 0 March 8 2005 XILINX Chapter 1 Virtex Il Pro Development System User LEDs Switches and Push Buttons A total of four LEDs are provided for user defined purposes When the FPGA drives a logic 0 the corresponding LED turns on A single four position DIP switch and five push buttons are provided for user input If the DIP switch is up closed or on or the push button is pressed a logic 0 is seen by the FPGA otherwise a logic 1 is indicated Ex
96. ce XILINX The Ethernet network interface is made up of three distinct components the Media Access Controller MAC contained in the FPGA a physical layer transceiver PHY and the Ethernet coupling magnetics The LXT972A U12 is an IEEE 802 3 compliant Fast Ethernet physical layer PHY transceiver that supports both 100BASE TX and 10BASE T operation It provides the standard Media Independent Interface MII for easy attachment to 10 100 MACs The LXT972A supports full duplex operation at 10 Mb s and 100 Mb s The operational mode can be set using auto negotiation parallel detection or manual control The LXT972A performs all functions of the physical coding sublayer PCS the physical media attachment PMA sublayer and the physical media dependent PMD sublayer for 100BASE TX connections The LXT972A reads its three configuration pins on power up to check for forced operation settings If it is not configured for forced operation at 10 Mb s or 100 Mb s the device uses auto negotiation parallel detection to automatically determine line operating conditions If the PHY on the other end of the link supports auto negotiation the LXT972A auto negotiates with it using fast link pulse FLP bursts If the other PHY does not support auto negotiation the LXT972A automatically detects the presence of either link pulses 10BASE T or idle symbols 100BASE TX and sets its operating mode accordingly The LXT972A configuration pins are
97. ce in ISP mode done Programming Revision 0 111 Write Protect Revision 0 1 Write Protect Revision 0 PROGRESS END End Operation Elapsedtime 37 sec 1 Figure C 9 iMPACT Programming Transcript Window 3 XILINX 13 To load the newly programmed PROM configuration file into the Virtex II Pro FPGA verify that the CONFIG SOURCE switch is set to enable high speed SelectMap byte wide configuration from the on board Platform Flash configuration PROM and that the PROM VERSION switch is set to enable the Golden configuration If the switches are set properly the green PROM CONFIG LED D19 and the amber GOLDEN GONFIG LED D14 are illuminated 14 Press the RESET RELOAD push button until the red RELOAD turns on Upon releasing the push button the new Golden configuration is transferred to the FPGA Xilinx University Program Virtex ll Pro Development Systemwww xilinx com 001069 v1 0 March 8 2005 1 800 255 7778 95 XILINX Appendix C Restoring the Golden FPGA Configuration 96 www xilinx com Xilinx University Program Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 7 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test A special design has been placed in the Platform FLASH PROM to provide a Built in Self Test BIST boot configuration that tests critical board features and reports on board health and sta
98. ctors J23 24 This EXTERNAL CLOCK can be used to clock the SATA ports if non standard signaling rates are required The MGT connections are shown in Table 2 20 For the user to take advantage of the fourth MGT channel four SMA connectors must be installed at J19 J22 These SMA connectors be purchased from Digikey under the part number A24691 ND Figure 2 20 identifies the location of the external differential clock inputs m wq e ty twa CIES 75 0 0 EN Oo DE RNI3 ANM EXT 5 TXP MGT RXP hj LI UP LIE ON 6e TXNS MGT RXN ELA A 80800 EXT CLK N VIRTEX II PRO Figure 2 20 SMA based Connections There are eight clock inputs into each RocketIO transceiver instantiation REFCLK and BREFCLK are reference clocks generated from an external source and presented to the FPGA as differential inputs The reference clocks connect to the REFCLK or BREFCLK ports on the MGT While only one of these reference clocks is needed to drive the MGT BREFCLK or BREFCLK2 must be used for serial speeds of 2 5 Gb s or greater At speeds of 2 5 Gb s or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver For these higher speeds BREFCLK configuration is required The BREFCLK configuration uses dedicated rou
99. d Signal 04 _ B05 B45 GND _ _ _ B46 HS_CLKIN B16 GCLK6S No Pair LVCMOS25 47 GND 48 HS CLKIO E3 33P 2 LVTTL B49 VCC5V5 B50 SHIELD Using the CPU Debug Port and CPU Reset The CPU Debug port J36 is a right angle header that provides connections to the debugging resources of the PowerPC 405 CPU core The PowerPC 405 CPU cores include dedicated debug resources that support a variety of debug modes for debugging during hardware and software development These debug resources include e Internal debug mode for use by ROM monitors and software debuggers e External debug mode for use by JTAG debuggers e Debug wait mode which allows the servicing of interrupts while the processor appears to be stopped e Real time trace mode which supports event triggering for real time tracing Debug modes and events are controlled using debug registers in the processor The debug registers are accessed either through software running on the processor or through the port The debug modes events controls and interfaces provide a powerful combination of debug resources for hardware and software development tools The JTAG port interface supports the attachment of external debug tools such as the powerful ChipScope Integrated Logic Analyzer a powerful tool providing logic analyzer capabilities for signals inside an
100. d master are determined by the CONFIG SOURCE switch the most significant switch left side of SW9 If the CONFIG SOURCE switch is closed on or up a high speed SelectMap byte wide configuration from the on board Platform Flash configuration PROM 03 is selected as the configuration source This is identified to the user through the illumination of the PROM CONFIG LED D19 The Platform Flash configuration PROM supports two different FPGA configurations versions selected by the position of the PROM VERSION switch the least significant switch right side of SW9 If the PROM VERSION switch is closed on or up the GOLDEN configuration from the on board Platform Flash configuration PROM is selected as the configuration data This is identified to the user through the illumination of the GOLDEN CONFIG LED 014 This configuration can be a board test utility provided by Xilinx or another safe default configuration It is important to note that the PROM VERSION switch is only sampled on board powerup and after a complete system reset This means that if this switch is changed after board powerup the RESET RELOAD pushbutton SW1 must be pressed for more than 2 seconds for the new state of the switch to be recognized If the PROM VERSION switch is open off or down a User configuration from the on board Platform Flash configuration PROM is selected as the configuration data This configuration must be programmed into the Pl
101. der Pinout Bo FESR MES 1 VCC2V5 3 VCC2V5 5 VCC3V3 J5 3 16 3 7 VCC3V3 15 3 16 3 9 VCC3V3 J5 3 16 3 11 EXP IO 40 T3 5 36 13 EXP IO 41 T4 J5 37 LVTTL 15 EXP IO 42 U2 5 38 LVTTL 17 EXP IO 43 U3 J5 39 LVTTL 19 EXP_IO_44 T7 J5 40 LVTTL 21 EXP_IO_45 T8 J6 5 LVTTL 23 EXP IO 46 U4 J6 4 LVTTL 25 EXP IO 47 U5 J6 7 LVTTL 27 EXP IO 48 V2 J6 6 LVTTL 29 EXP IO 49 W2 J6 9 LVTTL 31 EXP_IO_50 T9 J6 8 LVTTL 33 EXP_IO_51 U9 J6 11 LVTTL 35 EXP_IO_52 V3 J6 10 LVTTL 37 EXP_IO_53 V4 J6 13 LVTTL 39 EXP_IO_54 W1 J6 12 LVTTL Virtex ll Pro Development System www xilinx com 49 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Table 2 12 Lower Middle Expansion Header Pinout Continued Pin Signa OType 41 EXP IO 55 1 6 15 LVTTL 43 EXP IO 56 U7 1614 LVTTL 45 EXP IO 57 08 6 17 LVTTL 47 EXP IO 58 V5 J6 16 LVTTL 49 EXP IO 59 V6 J6 19 LVTTL 51 VCC3V3 J5 3 J6 3 53 VCC3V3 J5 3 J6 3 55 VCC3V3 5 3 J6 3 57 VCC2V5 59 VCC2V5 2 GND 5 1 6 1 4 GND J5 1J6 1 6 GND J5 1J6 1 8 GND J5 1 6 1 10 GND J5 1 6 1 12 GND J5 1J6 1 14 GND J5 1 6 1 16 GND J5 1J6 1 18 GND J5 1J6 1 20 GND J5 1J6 1 22 GND J5 1J6 1 24 GND J5 1J6 1 26 GND J5 1 6 1 28 GND 5 1 6 1 30 GND J5 1J6
102. dicators for the user to define as well as four DIP switches and five pushbuttons for user defined use The pushbuttons are arranged in a diamond shape with the ENTER pushbutton in the center of the diamond This placement can be used for object movement in a game None of the DIP switches or pushbuttons have external de bouncing circuitry because this should be provided in the FPGA application Table 2 9 identifies the connections between the user switches user LEDs and the FPGA Table 2 9 User LED and Switch Connections Signal Direction FPGA Pin Type Drive Slew LED 0 O ACA LVTTL 12 mA SLOW LED 1 LVTTL 12 mA SLOW LED 2 6 LVTTL 12 mA SLOW LED 3 5 LVTTL 12 mA SLOW SW 0 I 11 LVCMOS25 SW 1 I ADI1 LVCMOS25 SW 2 AF8 LVCMOS25 _ _ SW_3 I AF9 LVCMOS25 _ _ PB_ENTER I AG5 LVTTL _ _ PB_UP I AH4 LVTTL _ _ PB_DOWN I AG3 LVTTL _ _ XUP Virtex II Pro Development System www xilinx com 43 06069 v1 0 March 8 2005 Chapter 2 Using the System Table 2 9 User LED and Switch Connections Continued Signal Direction FPGA Pin Type Drive Slew PB LEFT I 1 IVTTL PB RIGHT I AH2 LVTTL Using the Expansion Headers and Digilent Expansion Connectors The Virtex II Pro Development System allows for four user supplied expansion headers that are tailored to accept ribbon cables and two front mounted con
103. e DRAFT Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 Contents Chapter 1 Virtex ll Pro Development System Features ay aka qa aaa a ke E eie pad 13 General DeserIipti n wa ava wa tpe hee Rape aor pao 14 Block Diagram PED 14 Board Components os e Ee ERE HERE VR 14 Pro FPGA reser CAE dees E ACCION saa 15 Power Supplies and FPGA 16 Multi Gigabit 17 oystem RAM essa bested eia A e Rer es e Big a gans 17 System ACE Compact Flash Controller 17 Rast Ethernet Interface sua gaa be eek Re bed rry errans 17 Serial Ports 17 User LEDs Switches and Push 18 Expansion 18 XSGA DDUEDUE dada ode qoare a orco oa lp T d ore Eo eS 18 AC97 Audio CODEC sapaqa d Ka de ae visa era 18 CPU Debug Port icr e Rer Ey xr e ya Ea rr kan 18 USB 2 Programming Interface 18 Chapter
104. e XUP Virtex II Pro Development System has provision for the installation of user supplied JEDEC standard 184 pin dual in line Double Data Rate Synchronous Dynamic RAM memory module The board supports buffered and unbuffered memory modules with a capacity of 2 GB or less in either 64 bit or 72 bit organizations The 72 bit organization should be used if ECC error detection and correction is required System ACE Compact Flash Controller The System Advanced Configuration Environment System Controller manages FPGA configuration data The controller provides an intelligent interface between an FPGA target chain and various supported configuration sources The controller has several ports the Compact Flash port the Configuration JTAG port the Microprocessor MPU port and the Test JTAG port The XUP Virtex II Pro Development System supports a single System ACE Controller The Configuration JTAG ports connect to the FPGA and front expansion connectors The Test JTAG port connects to the JTAG port header and USB2 interface CPLD and the MPU ports connect directly to the FPGA Fast Ethernet Interface The XUP Virtex II Pro Development System provides an IEEE compliant Fast Ethernet transceiver that supports both 100BASE TX and 10BASE T applications It supports full duplex operation at 10 Mb s and 100 Mb s with auto negotiation and parallel detection The PHY provides a Media Independent Interface MII for attachment to the 10 100 Media A
105. ecks if there is a Compact Flash or Microdrive in the System ACE socket If it finds one you will see the response shown in Figure 0 19 Otherwise it will just say Querying formatted memory device FAILURE I Tera Term VT File Edit Setup Control Window Help SYSRCE Self Test Initalizing sysace done Querying device version done Identified SYSACE version 4108 Querying formatted memory device SUCCESS lt Type to return to menu H Figure D 19 System ACE Test Completion Note f a Compact Flash or Microdrive is inserted in the socket make sure that it does not contain an FPGA configuration file otherwise the FPGA will be reconfigured and the BIST will be terminated Virtex ll Pro Development System www xilinx com 111 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX 112 Appendix D Using the Golden FPGA Configuration for System Self Test DDR SDRAM Test This test begins when 5 is selected from the BIST Main Menu It first uses the serial detect lines to determine if a DIMM module is seated in the memory slot If one is identified it proceeds to read the configuration registers to determine if the module is currently supported by the Virtex II Pro Development System The registers of interest include the following Register 2 memory type only DDR memories type 7 are supported Register 3 row address count only devices with 13 row addresses are suppor
106. ed version of the Platform Cable USB for the purpose of configuration and programming the Virtex II Pro FPGA and the Plattorm FLASH PROM using an off the shelf high speed USB A B cable Configuration and programming are supported by iMPACT v6 3 01i or later download software using Boundary Scan IEEE 1149 1 IEEE 1532 mode Target clock speeds are selectable from 750 kHz to 24 MHz The host computer must contain a USB host controller with one or more USB ports The controller can reside on the mother board or can be added using an expansion card or PCMCIA CARDBUS adapter The host operating system must be either Windows 2000 SP4 or later or Windows XP SP1 or later IMPACT 6 3 01 and ChipScope Pro are not supported by earlier versions of Windows The embedded Platform Cable USB interface is designed to take full advantage of the bandwidth of USB 2 0 ports It is also backward compatible with USB 1 1 ports The interface is self powered and consumes no power from the host hub It is enumerated as a high speed device on USB 2 0 hubs or a full speed device on USB 1 1 hubs A proprietary Windows device driver is required to use the embedded Platform Cable USB Foundation ISE software releases and service packs beginning with version 6 3 01i incorporate this device driver Windows does not recognize the embedded Platform Cable USB until the appropriate Foundation ISE or ChipScope Pro installation has been completed The embedded Platfo
107. eo Output e 180 MHz Triple Video D A Converter http www fairchildsemi com ds FM FMS3818 pdi Ethernet Networking e Dual Speed Single Port Fast Ethernet Transceiver http www intel com design network products lan datashts 24918603 pdf Power Supplies e 6 Output Synchronous Buck PWM Switching Power Supply http focus ti com lit ds symlink tps54616 pdf e Precision Triple Supply Monitor http www linear com pc downloadDocument do navId H0 C1 C1003 C1144 C10 43 C1020 P1552 D1625 138 www xilinx com Virtex ll Pro Development System 1 800 255 7778 UGO69 v1 0 March 8 2005
108. er 02h www xilinx com Virtex ll Pro Development System 00069 v1 0 March 8 2005 7 XILINX Using the AC97 Audio CODEC and Power Amp 7081017169091 sro F F uawod AS Olanv gt gt 1 aNd olanv ant ant Jazz daz ero a 2 OWL wo ovo oza 1 ZHIN 9 92 Sto adozz YA LED ano ZA NR B e e ans olanv anro 5 2 m 3 3 Seo 215 POF m 9 8 G F o 2 o e 1no onon NON y 1431 otanv Tino wn E a H ino aN1 Txnv 14311100 3Nrr Olqnv lt ano ann 100 3NIT K H 1nO WIN T oaqlA Fs K NM oaan ene ene m 199 6918 23009 H3XIIN Olanv QN9 jo 93009 460v Y 00 sz _ AN 30070 460v 0019 118 zon 5 ans olanv HONAS 60 LEE HONAS lt N Vlvqs 469v lt Nr vwWOS K 143 NE 3NIT olanv n 1nO viv as 60v gt gt 32 2499 1no vivas E K AHI NIANITOIGNW 9 z1asav olanv gt gt 4338 od GI eye d m AN ans olanv anro anro loni zeo anro igo oso 629 sz
109. ered 2 5 CT6472Z265 9T 512 MB 64M X 72 Single Unbuffered 2 5 CT64647265 8T 512 MB 64M X 64 Single Unbuffered 2 5 CT16642265 4T 128 MB 16M X 64 Single Unbuffered 2 5 Notes The in the Crucial part number represents the revision number of the module which is not required to order the module These memory modules are designed for a maximum clock frequency of at least 133 MHz and have a CAS latency of 2 5 18 8 ns The PLB Double Data Rate Synchronous DRAM Controller supports CAS latencies of two or three clock cycles If the memory system is to operate at 100 MHz then set the CAS latency parameter in the controller design to 2 20 ns If full speed 133MHz memory operation is required then set the CAS latency parameter in the controller design to 3 22 6 ns Table 2 5 provides the details on the FPGA to DDR SDRAM DIMM module connections Table 2 5 DDR SDRAM Connections Signal Direction Mal ki jg Type SDRAM_DQJ 0 I O 2 C27 SSTL2 II SDRAM_DQ 1 I O 4 D28 SSTL2 II SDRAM_DQ 2 I O 6 D29 SSTL2 II SDRAM DQ 3 I O 8 D30 SSTL2 II SDRAM DQL4 I O 94 H25 SSTL2 II SDRAM DQI5 I O 95 H26 SSTL2 II SDRAM DQI6 I O 98 E27 SSTL2 II SDRAM_DQ 7 I O 99 E28 SSTL2 II SDRAM DOS 0 I O 5 E30 SSTL2 II SDRAM DM O0 0 97 U26 SSTL2 II 30 www Xilinx com XUP Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the DIMM Module DDR SDRAM XILINX Table 2 5 DDR SDRAM Connecti
110. erential lines and the TX PREEMPHASIS attribute sets the output driver pre emphasis Xilinx recommends setting the TX attribute to 600 600 mV and the TXPREEMPHASIS attribute to 2 25 when SATA cables of 1 0 or less meters in length are used to connect the MGT host to the MGT target Typical eye diagrams for 1 5 Gb s data Virtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 69 XILINX Chapter 2 Using the System transmission using 0 5 meter and 1 0 meter SATA cables are shown in Figure 2 21 and Figure 2 22 File Control Setup Measure stopped 10 Analyze Utilities Help More 2042 Eye width cg Eye height cg Data TIE 1 Cyc cyc jitr 1 E Delete Current 581 9 ps 309 6 32 29 ps PH All Hean 11 5 307 9 Hin I 306 5 mV Max 309 3 Figure 2 21 1 5 Gb s Serial Data Transmission over 0 5 meter of SATA Cable File Control Setup Measure Acquisition is stopped 2 10 0 kpts Analyze Utilities widthicg Ey Current 1 3 2 9 ps Hean Min 11 4 ps 11 4 ps Figure 2 22 1 5 Gb s Serial Data Transmission over 1 0 meter of SATA Cable www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 XILINX Appendix Configuring the from the Embedded USB Configuration Port The Virtex II Pro Development System contains an embedd
111. ests are being run or accessed The user should also note that the RESETNRELOAD button resets the processor and returns the programming to the Built In Self Test Main Menu On power up or reset the Built In Self Test Main Menu shown in Figure D 2 should be displayed in your PC s terminal window Virtex ll Pro Development System www xilinx com 101 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test Ii Tera Term COM1 VT Ei l File Edit Setup Control Window Help UP U2Pro BuiltIn Self Test Main Menu Rev 1 2 Feb 2885 Test SATA port with Aurora loopback Test Ethernet vith example Test fiC97 audio codec Test System ACE Test DDR SDRAM Test Expansion connectors ua069 01a 021005 Figure D 2 Built In Self Test Main Menu Additional Hardware Required e 09 male to female straight through serial communications RS 232 cable PC running Hyper Terminal or similar terminal program set to 9600 baud 8 bit data no parity 1 stop bit and no flow control For a free PC terminal program see http hp vector co jp authors 002416 teraterm html MGT Serial ATA Test This test verifies proper operation of the three SATA Multi Gigabit Transceivers MGTs This is accomplished using a modified version of the Xilinx Aurora 201 demo design which can be found at http www xilinx co
112. evision 1 as shown in Figure B 8 O untitled File Generation Mode iMPACT File Edit View Mode Operations Output Help DZA Ge Slee 2 22 O E Revision 0 E Lookin DESIGN 7 lt File name imy design bit Filesoftype All Design Files 2 Figure B 8 Adding the Design File to Revision 1 12 Click on Open and answer No when prompted to add another design file to Revision 1 Click on Finish to start the generation of the MCS file as shown in Figure B 9 Virtex ll Pro Development System www xilinx com 81 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix B Programming the Platform FLASH PROM User Area SIAN 5 O tput Help D 5 e 01 G Sj Revision Revision 0 1 1 Starting Address 8 Hex Digits xcf32p E 69 08 Full xc2vp30 7 1 my design bit Now start adding device file s Click Finish to start generating file Click Cancel to go to user screen Finish Cancel Help Figure B 9 Generating the MCS File 13 When prompted to compress the file respond No because the XUP Virtex II Pro Development System hardware does not support this option 14 After iMPACT successfully creates the MCS file select Configuration Mode from the Mode menu as shown in Figure B 10
113. for System Self Test Figure D 1 Virtex II Pro Development System BIST Block Diagram 97 Figure D 2 Built In Self Test Main 102 Figure D 3 Testing the SATA 0 HOST to SATA 1 TARGET Connection 103 Figure D 4 Testing the SATA 2 HOST to SATA 1 TARGET Connection 103 Figure D 5 Selecting the SATA Port Tests 104 Figure D 6 Selecting the Specific SATA Port to Test 104 Figure D 7 Resetting the 104 Figure D 8 No Link Established Error 105 Figure D 9 SATA Test Running 105 Figure D 10 SATA Loopback Test 55 106 Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 Figure D 11 Specifying IP Address for Virtex II Pro Development System 107 Figure D 12 Web Server 107 Figure D 13 Web Server 108 Figure D 14 Web Server Stopped 108 Figure D 15 Selecting the Specific AC97 Audio Test 109 Figure D 16 Digital Passthrough Test Completion 1
114. h Speed Expansion Port 2 R 2 Figure 1 1 Virtex Il Pro Development System Block Diagram Board Components 14 This section contains a concise overview of several important components on the XUP Virtex II Pro Development System see Figure 1 2 The most recent documentation for the system can be obtained from the XUP Virtex II Pro Development System support website at http www xilinx com univ xup2vp html www xilinx com Virtex ll Pro Development System 00069 v1 0 March 8 2005 General Description XILINX Three high current power supplies with continuous monitoring Platform Power Flash for connector storing and switch bios config urations XSGA Video 4 0582 port Port for FPGA config urations Compact SATA A flash card connectors port for for Gigabit FPGA serial config and D removable for Compact storage Flash E 10400 Ethernet MAC PHY PS mouse and keyboard port Stereo gt a w n n audio j 5 ia four 60 AC97 P 7 gom x 355 headers RS 232 codec Y serial port High speed expansion connector Buttons switches Low speed expansion connector compatible with Digilent boards and LEDs compatible with Digilent boards Figure 1 2 Virtex ll Pro Development System Board Photo Virtex ll Pro FPGA U1 is a Virtex II Pro FPGA device packaged in a flip chip fine pitch FF896 BGA package Two
115. he various revisions De select Design Revision Rev 0 and all of the options for Design Revision Rev 0 to minimize the programming time Any options that you set for Design Revision Rev 0 are ignored because Design Revision Rev 0 has been previously Erase Write protected 21 Select Design Revision Rev 1 and set the Erase ER bit to erase any previous User design Make sure that the Write Protect WP bit is not set 22 Verify that the Operating Mode is set to Slave and the I O Configuration is set to Parallel Mode as shown in Figure B 14 84 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Advanced PROM Programming Options x Design Revision and Customer Code Select Design Revision and Enter Customer Code Max 54 Hex Digits Design Read Write Erase Verify Customer Revision Protect Protect Code Revo PP IEEE Rei RP we we FER C Rev3 PP Default Revision m Operating Mode WO Configuration 8 Slave clocked by external clock Parallel Mode Master select clock source External Clack Enter 8 Hex Digits Usercode Internal Clack Clock Frequency Load FPGA Figure 14 PROM Programming Options 23 Click o
116. hown in Figure A 5 74 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 5 XILINX 8 Untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D Bj X eee 01 ss ss Boundary Scan Slave Serial SelectMAP Deskt Right click device to select operations xcf32p 2 30 xcf32p 1648 File File Figure A 5 Properly Identified JTAG Configuration Chain Right click on each of the devices in the chain and select Assign New Configuration File from the drop down menu see Figure A 6 The Platform FLASH PROM and the System ACE controller should be set to BYPASS and the desired configuration file for the should be specified as shown in Figure A 7 9 untitled Configuration Mode iMPACT View Mode Operations Output Help D S amp telg ak as G J z Boundary Scan Slave Serial SelectMAP Dest m LAA A Blank Check xcf32p_ Readback Assign New Configuration File Figure A 6 Assigning Configuration Files to Devices in the JTAG Chain Virtex ll Pro Development System www xilinx com 75 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix A Configuring the FPGA from the Embedded USB Configuration Port G Untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D S M amp Be 68
117. igital power supplies as well as application of external power if the capacity of the on board switching power supplies is exceeded The XUP Virtex II Pro Development System provides several methods for the configuration of the Virtex II Pro FPGA The configuration data can originate from the internal Platform Flash PROM two potential configurations the internal CompactFlash storage media eight potential configurations and external configurations delivered from the embedded Platform Cable USB or parallel port interface www xilinx com Virtex ll Pro Development System 00069 v1 0 March 8 2005 General Description XILINX Multi Gigabit Transceivers Four of the eight Multi Gigabit Transceivers MGTs that are present in the Virtex II Pro FPGA are brought out to connectors and can be utilized by the user Three of the bidirectional MGT channels are terminated at Serial Advanced Technology Attachment SATA connectors and the fourth channel terminates at user supplied Sub Miniature A SMA connectors The transceivers are equipped with a 75 MHz clock source that is independent for the system clock to support standard SATA communication An additional MGT clock source is available through a differential user supplied SMA connector pair Two of the ports with SATA connectors are configured as Host ports and the third SATA port is configured as a Target port to allow for simple board to board networking System RAM Th
118. ion xcf32p 2 30 File File Lookin DESIGN gt lt ck XUP V2Pro BIST mcs File name XUP V2Pro BIST mcs Open Files of type mcs Files mcs Cancel All Bypass 4 Figure 4 Assigning New PROM Configuration File 8 Select BYPASS as the configuration files for the System ACE controller and the Virtex II Pro FPGA 9 Right mouse click on the icon for the XCF32P PROM and select Erase from the drop down menu as shown in Figure C 5 When the erase options screen appears select AII Revisions and then click OK Xilinx University Program Virtex ll Pro Development Systemwww xilinx com 91 001069 v1 0 March 8 2005 1 800 255 7778 Appendix C Restoring the Golden FPGA Configuration G untitled Configuration Mode iMPACT Edit View Mode Operations Output Help D H telg Boundary Scan Slave Serial SelectMAP Deskto m e e Program xc Verify vc Blank Check Readback Get Device ID Get Device Checksum N Get Device Signature Usercode IDCODE Looping Assign New Configuration File Figure C 5 Erasing the Existing PROM Contents The iMPACT software then erases the complete contents of the PROM including old versions of the Golden and User designs The transcript window should look similar to Figure C 6 BATCH CMD
119. irtex ll Pro Development System 06069 v1 0 March 8 2005 www xilinx com 1 800 255 7778 123 XILINX Appendix E User Constraint Files UCF PINOUT AND IO DRIVE CHARACTERISTICS FOR THE LOWER MIDDLE EXPANSION HEADER OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004 5 d EXP IO 40 LOC T3 EXP IO 41 LOC T4 EXP IO 42 LOC U2 EXP IO 43 LOC U3 EXP IO 44 LOC 7 EXP IO 45 LOC T8 EXP IO 46 LOC U4 EXP IO 47 LOC U5 EXP IO 48 LOC V2 EXP IO 49 LOC W2 EXP IO 50 LOC T9 EXP IO 51 LOC U9 EXP IO 52 LOC V3 EXP IO 53 LOC V4 EXP IO 54 LOC 1 EXP IO 55 LOC Y1 EXP IO 56 LOC U7 EXP IO 57 LOC U8 EXP IO 58 LOC V5 EXP IO 59 LOC V6 5 d 5 3 5 3 E zl m d E d m d 2 d 3 d 5 3 3 3 5 d 5 3 5 d m d 4 LE n LE HE DB Dg Dg BJ DE REP 14 BA DE E BR DU E z 158 5 d EXP IO IOSTANDARD LVTTL 124 www xilinx com Virtex ll Pro Development System 1 800 255 7778 UGO69 v1 0 March 8 2005 XILINX PINOUT AND IO DRIVE EXPANSION HEA REVISION C PRINTED z z z z zz zz z z z z 24224222224 Ej td Ed Ed b bd Ed bd m Hd mi Bd bd bd Dd m E 5 5 5 E
120. is not required Figure 2 17 shows the implementation of the serial port used on the XUP Virtex II Pro Development System is a 2 5 powered device that operates as a transceiver to shift the signaling levels from the voltages supported by the FPGA to those required by the 5 232 specification The MAX3388E has two receivers and three transmitters and is capable of running at data rates up to 460 kb s while maintaining RS 232 compliant output levels There are five signals from the FPGA to the RS 232 serial port 5232 TX DATA RS232 DSR OUT 5232 CTS OUT RS232 RX DATA and RS232 RTS IN The Transmit Data and Receive Data provide bidirectional data transmission while Request To Send Clear To Send and Data Set Ready provide for hardware flow control across the serial link Table 2 17 identifies the RS 232 signal connections to the FPGA IBM developed the PS 2 ports for peripherals as an alternative to serial ports and dedicated keyboard ports These ports have become standard connectors on PCs for connecting both keyboards and mice They use a 6 pin mini DIN connector and a bidirectional synchronous serial interface with a bidirectional data signal and a unidirectional clock The Virtex II Pro Development System provides two PS 2 ports for keyboard and mouse attachment The PC mouse and keyboard use the two wire RS 2 serial bus to communicate with the host FPGA The PS 2 bus includes both clock and data with ide
121. l Cable 4 interface be used instead by connecting a cable 10 J27 It should be noted that if SelectMap byte wide configuration from the on board Platform Flash configuration PROM is enabled the FPGA Start Up Clock should be set to CCLK in the Startup Options section of the Process Options for the generation of the programming file otherwise JTAG Clock should be selected Virtex ll Pro Development System www xilinx com 21 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Figure 2 3 illustrates the configuration data path USB2 Microcontroller JTAG Port Test JTAG Port SystemACE Config JTAG Port amp CPLD PLATFORM FLASH Controller Micro Port GOLDEN VERSION SELECT 8 USER CF Card MicroDrive SMAP Port Micro Port PROM CONFIG SOURCE 9 JTAG 060069 06 122704 Figure 2 3 Configuration Data Path Four status LEDs show the configuration state of the XUP Virtex II Pro Development System at all times The user can see the configuration source configuration version and tell when the configuration has completed from the status LEDs shown in Table 2 1 Table 2 1 System Configuration Status LEDs LED Status System Status D19 Green D20 Green D14 Amber D4 Red PROM Config CF Config GOLDEN Config Done SelectMAP USER LOADING ON OFF OFF OFF SelectMAP USER COMPLETED ON OFF OFF
122. le 2 13 Bottom Expansion Header Pinout Continued Pin Signal OType 39 EXP IO 74 W7 J6 32 LVTTL 41 EXP IO 75 ws J6 35 LVTTL 43 EXP_IO_76 AB3 J6 34 v 45 EXP_IO_77 AB4 47 EXP IO 78 AB2 49 EXP IO 79 AC2 51 VCC3V3 J5 3 16 3 53 VCC3V3 J5 3 16 3 55 VCC3V3 J5 3 16 3 57 VCC5VO J5 2 J6 2 59 VCC5VO J5 2 J6 2 2 GND J5 1J6 1 4 GND J5 1J6 1 6 GND 5 1 J6 1 8 GND 5 1 J6 1 10 GND 5 1 J6 1 12 GND J5 1 J6 1 14 GND 5 1 J6 1 16 GND 5 1 J6 1 18 GND J5 1 J6 1 20 GND 5 1 J6 1 22 GND J5 1 J6 1 24 GND 5 1 J6 1 26 GND J5 1 J6 1 28 GND 5 1 J6 1 30 GND 5 1 J6 1 32 GND J5 1 J6 1 34 GND 5 1 J6 1 36 GND 5 1 J6 1 38 GND 5 1 J6 1 40 GND J5 1 J6 1 52 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the Expansion Headers and Digilent Expansion Connectors Table 2 13 Bottom Expansion Header Pinout Continued XILINX Pin Signal Pin EXPRin OType 42 15 1 16 1 44 J5 1 6 1 46 GND J5 1J6 1 48 a 1 161 5 50 GND J5 1J6 1 52 15 1 16 1 54 GND _ J5 1J6 1 56 GND 2 15 1 16 1 58 GND
123. ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Processor Based Tests XILINX If there is a serious problem or the test was started without a cable connected to either loop path you may see the message shown in Figure D 8 displayed on your terminal window Tera Term COM1 VT File Edit Setup Control Window Help urora Test System Uersion 2 1 esetting MGIs done arning Couldn t establish links on both cores ress any key to continue d Figure D 8 No Link Established Error Message Once you type into the terminal window and the test starts the user can change the default settings for example the internal serial loopback or the parallel loopback and continue as shown in Figure D 9 The user should note that the test will run until 1000 frames are transmitted or until the user types q to end the test Tera Term COMI VT File Edit Setup Control Window Help Frames lt 64 2 Words 64kdi CCs 64k Rate Mbps Frames lt 64 gt Words 64k Dropped Frames Dropped Words Hard Errors Soft Errors Framing Errors Pattern sequential sequential Frame Size 64 64 LoopBack an PowerDoun 11 Toggle Pattern Auroral Pattern 2 Toggle Aurora RndFnSz Auroral RndFmSz 131 Toggle Aurora P LpBk Auroral P LpBk 41 Toggle S LpBk 1 S LpBk 51 Toggle Aurora PurDun Aurorai space Reset Both MGTs i Figu
124. lock must be setup with only 1 reserved sector It is typical of newer operating systems to format CompactFlash devices with more that 1 reserved sector The workaround for these System ACE controller requirements is to format the card with a utility such as mkdosfs found at http www magerorg mkdosfs The following command line produces the correct format on drive X with a volume name of XLXN C gt mkdosfs v F 16 R 1 s 2 n XLNX X fora 16 MB CF card C gt mkdosfs v F 16 R 1 s 8 n XLNX X fora 128 MB card C gt mkdosfs v F 16 R 1 s 16 n XLNX X fora 512 MB CF card C gt mkdosfs v F 16 R 1 s 64 n XLNX X foralGB microdrive For more information on the System ACE MPU interface consult the System ACE CompactFlash Solution DS080 data sheet Table 2 20 outlines the MPU interface connections between the FPGA and the System ACE controller Table 2 20 System ACE Connections Signal Direction died FPGAPin VO Type Drive 01 70 AF21 LVCMOS25 8mA 69 21 LVCMOS25 8mA MPA 68 19 LVCMOS25 8mA MPA 3 67 AD19 LVCMOS25 8mA MPA 4 45 AE22 25 8mA CF MPA 5 44 AE21 LVCMOS25 8mA CF MPA 6 46 AH22 LVCMOS25 8mA 0 I O 66 15 LVCMOS25 8mA 1 65 ADI5
125. lt in the LEDs displaying the clock status again for 5 seconds 6 Connect the headphones to the upper jack of J14 OUT Warning Do not put the headphones on your ears because the tones generated will be LOUD 7 Press each one of the push buttons SW2 6 A different tone will be produced as each push button is pressed SVGA Gray Scale Test This test verifies the operation of the video DAC by creating a gray scale ramp that drives each of the red green and blue channels with the same signal Any color present indicates the failure of one or more channel outputs Any data bus errors will show up as discontinuities in the ramp There should be 1 5 ramps visible on the display Additional Hardware Required e 5Vexternal power supply SVGA display with cable capable of showing 640 x 480 at 60 Hz image Test Procedure 1 Set the CONFIG SOURCE PROM VERSION DIP switch SW9 with both of the switches up or closed 2 Plug in the external 5V power supply and turn on the board by sliding SW11 up towards the ON label LEDs D14 GOLDEN CONFIG D19 PROM CONFIG and D4 DONE should be on 3 Connect the SVGA display to the SVGA output connector J13 A gray scale ramp should be seen on the bottom of display SVGA Color Output Test This test verifies the operation of the video DAC by creating a color bar pattern starting with 100 white followed by 75 color bars Between each of the color bars there
126. ly LOC GT_X0Y1 SATA 0 HOST n of the registers in the MGT Phase rect timing with respect to the MGT s ser Guide for more info logic REA_GROUP PHASE_ALIGN_0_GRP EA GROUP PHASE ALIGN 0 SATA PORTO IDLE LOC B15 SATA PORTO IDLE IOSTANDARD SATA PORTO IDLE SLEW 2 5 pou P gt 155 pp o 5 HEEE HE E HE HE HE E HE E E HHHH SATA Target FEFE E FE E FE HE HE HE HE HE HEHE H HE H HE HE H INST hierarchical path to mat SATA 1 TARGET GT X1Y1 NS Hae HE HE Ht HE HE H HE E H n a lign RANGE SLICE X14Y152 SLICl FAS LOC GT 1 1 P I X15Y153 LVTTL ne 1 HE HE HE He HE HE FE HE FE FE HE FE HE FE FE A HE FE FE EE E HE HE FE HE FE FE FE HE HE FE HE FE HE FE FE E HE FE FE E HE HE HE FE H HE H A H SATA 1 TARGET logic hierarchical path to al REA GROUP PHASE Al EA GROUP PHASE ALIGN 1 GRP SATA PORT1 IDLE LOC SATA PORT1 IDLE SATA 1 LIGN 1 GRP ed 5 AK3 IOSTANDARD SLEW 5 z 2 gt E Dd EJ 5 pou P IHBHRHHER SATA 2 IHBHRHHER INST 87 E E REGE Host FE HE HE HE HE FE HE FE HE FE HE FE HE FE HE HE HE hierarchical_path_to_mgt 2 HOST GT_X2Y1 l hierarchical path to al EET IE IEEE I H H n H
127. m aurora register aurora htm This test version uses the Aurora protocol to exercise the high speed serial interfaces of the XUP Pro board at 1 5 Gb s with 8B 10B encoding For simplicity and cost reduction the test is designed to use a standard 1 5 Gb s serial ATA cable available from most computer supply stores This test was verified using both 1 0 meter and 0 5 meter cables The basic procedure uses a cable to loop back bidirectional data from one of the two host transceivers to the target transceiver of the same board To test the second pair the serial ATA cable must be manually moved to the other host connector and the same test is rerun monitoring the other host which is selected via the test program software Note It is good practice to turn off power to the board before and while switching the SERIAL ATA cable However the MGTs are in a powered down mode while not displaying test status It is important to note that some additional MGT functionality is controllable once the test is started The test operation can be modified and interrupted from the test status report menu Either one or both of the two MGTS being exercised in the test can be switched to a serial or parallel INTERNAL loopback mode The internal serial loopback mode is useful in diagnosing if the MGT is shorted on the PCB With the internal serial loopback enabled a properly terminated is able to transmit to itself and receive correct data Additional Hardwa
128. mpactFlash device and read write sectors from or to a CompactFlash device The MPU interface can also be used to control configuration flow It enables monitoring of the configuration status and error conditions The MPU interface can be used to delay Virtex ll Pro Development System www xilinx com 65 06069 v1 0 March 8 2005 XILINX 66 Chapter 2 Using the System configuration start configuration select the source of configuration control the bitstream revision and reset the device For the System ACE controller to be properly synchronized with the MPU the clocks must be synchronized The clock traces on the XUP Virtex II Pro Development System that drive the System ACE controller and the MPU interface sections of are matched in length to maintain the required timing relationship The System ACE controller has very specific requirements for the way the file system is created on the CompactFlash device The FAT file system processing code cannot handle more than one ROOT directory sector 512 bytes or 16 32 bit file directory entries If the ROOT directory has more than 16 file directory entries including deleted entries the System ACE controller does not function properly In addition the System ACE controller cannot handle CompactFlash devices whose FAT file system is set up with 1 cluster 1 sector 512 bytes The CompactFlash device must be formatted so that 1 cluster gt 512 bytes and the boot parameter b
129. n FPGA Configuration for System Self Test Appendix E User Constraint Files UCF Appendix F Links to the Component Data Sheets Virtex ll Pro Development System www xilinx com 06069 v1 0 March 8 2005 7 XILINX Chapter 1 Virtex II Pro Development System Features VirtexIM II Pro FPGA with PowerPC 405 cores e Up to2GB of Double Data Rate DDR SDRAM System ACE controller and Type CompactFlash connector for FPGA configuration and data storage e Embedded Platform Cable USB configuration port e High speed SelectMAP FPGA configuration from Platform Flash In System Programmable Configuration PROM Support for Golden and User FPGA configuration bitstreams On board 10 100 Ethernet PHY device e Silicon Serial Number for unique board identification e RS 232 DB9 serial port e Two 5 2 serial ports e Four LEDs connected to Virtex II Pro I O pins e Four switches connected to Virtex II Pro I O pins e Five push buttons connected to Virtex II Pro I O pins e Six expansion connectors joined to 80 Virtex II Pro I O pins with over voltage protection e High speed expansion connector joined to 40 Virtex II Pro I O pins that can be used differentially or single ended e AC 97 audio CODEC with audio amplifier and speaker headphone output and line level output e Microphone and line level audio input e On board XSGA output up to 1200 x 1600 at 70 Hz refresh e Three Serial ATA p
130. n OK to begin programming the PROM The iMPACT transcript window shows the sequence of operations that took place and looks similar to Figure B 15 BATCH CMD Program p 1 defaultVersion 0 selectMap8 ver 1 eras PROGRESS START Starting Operation Validating chain Boundary scan chain validated successfully Validating chain Boundary scan chain validated successfully 1 Putting device in ISP mode done 1 Erasing device 1 Erasing Revision 1 done Erasure completed successfully 1 Putting device in ISP mode done Programming Revision 1 done done done done done PROGRESS END End Operation Elapsedtime 52 sec a Figure 15 PROM Programming Transcript Window Virtex ll Pro Development System www xilinx com 85 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix B Programming the Platform FLASH PROM User Area 24 To load the newly programmed PROM configuration file into the Virtex II Pro FPGA verify that the CONFIG SOURCE switch is set to enable high speed SelectMap byte wide configuration from the on board Platform Flash configuration PROM and that the PROM VERSION switch is set to enable the User configuration If the switches are set properly only the green PROM LED D19 is illuminated 25 Press the RESET RELOAD push button until the red RELOAD turns on Release the push button
131. n to low power mode SPD device read and write operations are shown in Figure 2 8 and Figure 2 9 SLAVE ADDRESS READ DATAn DATA n 1 MASTER T 5 FPGA 72 9 2 TIZ lt 5202 SLAVE SPD 9 001069 09 021405 Figure 2 8 EEPROM Sequential Read SLAVE ADDRESS WRITE WORD ADDRESS DATA t a MASTER x 5 FPGA a zg 5 SLAVE SPD EEPROM 9 9 9 00069 10 021405 Figure 2 9 EEPROM Write 26 www xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the DIMM Module DDR SDRAM XILINX The ability to read the SPD EEPROM is important because the module specific timing parameters are included in the EEPROM data and are required by the DDR SDRAM controller to provide the highest memory throughput The definitions of the SPD data bytes are outlined in Table 2 3 Table 2 3 SPD EEPROM Contents Byte Description 0 Number of used bytes in SPD EEPROM 1 Total number of bytes on SPD EEPROM 2 Memory type DDR SDRAM 07h 3 Number of row addresses 4 Number of column addresses 5 Number of ranks 01h 6 7 Module data width 8 Module interface voltage SSTL 2 5V 04h 9 SDRAM cycle time CAS LATENCY 2 5 10 SDRAM access time tac CAS LATENCY 2 5 11 Module configuration type 12 Refresh rate 13 Primary SDRAM component width 14 Error checking SDRAM component width 15 Minimum clock del
132. nals are shorted together Note The low speed Digilent expansion ports J5 J6 are wired in parallel with the header pins 41 44 Sequentially check each of the non power pins on the signal row of the high speed Digilent expansion connector J37 The signal row of this connector is the row farthest from the mating edge of the connector You should see a 20 ns pulse with a 1 6 us period at each signal pin Note The five pins on each end of the signal row are either power pins or JTAG pins and will not have the test pattern applied to them www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 lt XILINX Appendix E User Constraint Files UCF This appendix outlines the User Constraint Files UCF that are required to properly define the signal pinout of the Virtex II Pro FPGA as well as the input output switching levels drive strengths and slew rates The UCF file information is broken down by function and only the sections required for the user design need to be included in the file for the actual design Any updates to this information is available on the XUP Virtex II Pro Development System support Web site at http www xilinx com univ xupv2p html PINOUT AND IO DRIVE CHARACTERISTICS FOR THE AUDIO PROCESSING SECTION OF THE XUP V2PRO DEVELOPMENT SYSTEM REVISION C PRINTED CIRCUIT BOARD DEC 8 2004
133. nectors that are designed to accept Digilent peripheral devices and a single Digilent high speed port A total of 80 low speed signals are provided with most of the signals shared between the headers J1 4 and the front mounted connectors 5 6 All of these signals are equipped with over voltage protection devices J34 41 to protect the Virtex II Pro FPGA The IDT QuickSwitch devices IDTQS32861 provide protection from signal sources up to 7V Table 2 10 through Table 2 16 provide the FPGA connection information and outline the signals that are shared between the two expansion connector types Various power supply voltages are available on the expansion connectors 2 5V 3 3V and 5 0V depending on the connector type The expansion headers are positioned to prevent the installation of a ribbon cable connector across two of the expansion headers Every second signal in the ribbon cable is a ground signal to provide the best signal integrity at the user s target The output of the over voltage protection device follows the input voltage up to a diode drop below the rail at which time the voltage is clamped So with a Vcc of 3 3V the output clamps at 2 5V This gives 500 mV of input switching margin for both LVTTL and LVCMOS83 3 which have a Viy of 2 0V minimum The expansion headers J1 J4 are user installed items These headers can be purchased from Digikey under the part number 52012 30 ND Figure 2 14 identifies the location of the
134. ns 43 Table 2 9 User LED and Switch 43 Table 2 10 Top Expansion Header 45 Table 2 11 Upper Middle Expansion Header 47 Table 2 12 Lower Middle Expansion Header 49 Table 2 13 Bottom Expansion Header 51 Table 2 14 Left Digilent Expansion Connector 53 Table 2 15 Right Digilent Expansion Connector 54 Table 2 16 High Speed Digilent Expansion Connector Pinout 56 Table 2 17 CPU Debug Port Connections and CPU Reset 59 Table 2 18 Keyboard Mouse RS 232 Connections 62 Table 2 19 10 100 ETHERNET Connections 64 Table 2 20 System ACE Connections 66 Table 2 21 SATA and MGT 68 06069 v1 0 March 8 2005 www xilinx com XUP Virtex ll Pro Development System Appendix A Configuring the FPGA from the Embedded USB Configuration Port Appendix B Programming the Platform FLASH PROM User Area Appendix C Restoring the Golden FPGA Configuration Appendix D Using the Golde
135. ntical signal timings and both user 11 bit data words that include a start bit stop www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 Using the Serial Ports 5 XILINX RS232 DSR OUT RS232 TX DATA RS232 CTS OUT RS232 RX DATA RS232 RTS IN bit and odd parity The data packets are organized differently for mouse and keyboard data In addition the keyboard interface supports bidirectional data transfer so the host device can drive the status LEDs on the keyboard lt lt VCC2V5 SHDN VCC 0 1UF 0 1UF C446 2 5V RS 232 1 4 e Transceiver C24 C1 0 1UF C449 T TAIN T2IN R1OUT R2OUT LOUT RS 232 DCE SWOUT MAC3388ECUG UGO69 17 021405 2 17 RS 232 Serial Port Inplementation The PS 2 port operates as a serial interface with a bidirectional data signal and a unidirectional clock signal Both of these signals operate as open drain signals defaulting to a logical 1 at 5V through the use of a week pull up resistor To transmit a logical 0 the signal line is actively pulled to ground In the case of the data line both the host and the attached peripheral are able to drive the signal low In the case of the clock signal only the host is able to drive the signal low giving the host control of the speed of the interface Figure 2 18 shows the implementation of the PS 2 keyboard
136. o K ENEDDA lt as olanv lt NI ANOL 97 Audio CODEC Fiqure 2 12 41 www xilinx com Virtex ll Pro Development System 06069 v1 0 March 8 2005 yov oauals Lnd o Ld lt n vO8L0L el 60090 i 2 22 olanv olanv olanv anto Ezo zzo ant 810 NTON y 00 HL093S080ZH 87 H3MOd gt ou 00 HI093S080ZH 91 olanv Olanv GND olanv olanv 38027 elo ovr oauals lt 1397 1nO lt 1nO Olanv 1J3T1nO anv 00 109380802 1 as r 00 109380802 ant auo oianv QNO Olanv Olanv Olanv 390 7 34027 2 e 19 99 yov oasals u zu 00 H1093S080ZH 21 AOL Ni 00 H1093S080ZH 17 anozz 7 XILINX lt 1nO anv oldnv aN9 a olany SR 340 ely 619 ovr o3uais ant 0 A437 NIANIT OolanvX X 00 8 09380802 1 dHoli NIraNIT olanvX 4 ant 919 MO 00 109350802 51 3022 7 Sio poz 4
137. on the Web page without entering anything in the text box to reload the Web page The background of the Web page will change each time it is reloaded 4 You can change the DIP switches on the board and reload the Web page to see the DIP switch status report at the bottom of the Web page 5 You can type in x or X in the text field and click Submit bottom to terminate the Web server You will see the Web page shown in Figure D 14 indicating that the Web server is stopped Your terminal program will return back to the BIST Main Menu http 128 187 114 140 8080 pl textbox x Microsoft Internet Explorer File Edit View Favorites Tools Help Figure D 14 Web Server Stopped 108 www xilinx com Virtex Il Pro Development System 1 800 255 7778 UGO69 v1 0 March 8 2005 Processor Based Tests XILINX AC97 Audio Test This test begins when 3 15 selected from the BIST Main It verifies the operation of the AC97 CODEC for three different modes as selected by the user from the AC97 Audio Test Menu shown in Figure D 15 Tera Term COM1 VT File Edit Setup Control Window Help 1097 Audio Test Menu Passthrough Test Fifo Loopback Test Game Sounds Test Quit Figure D 15 Selecting the Specific AC97 Audio Test 1 Digital Passthrough the CODEC is configured to pass the data from the input channels line in mic in directly to the output channels line out amp out 2 FIFO
138. on the clock outputs Table 2 2 identifies the various clock connections for the FPGA Table 2 2 Clock Connections Signal FPGA Pin 10 Type SYSTEM CLOCK AJ15 LVCMOS25 ALTERNATE CLOCK 16 LVCMOS25 HS CLKIN from high speed B16 LVCMOS25 expansion port P F16 LVDS 25 MGT CLK N G16 LVDS 25 EXTERNAL CLOCK P G15 LVDS 25 EXTERNAL CLOCK N F15 LVDS 25 SYSTEMACE CLOCK 15 LVCMOS25 For the user to take advantage of the external differential clock inputs two SMA connectors must be installed at J23 and J24 These SMA connectors be purchased from Digi Key under the part number A24691 ND Figure 2 4 identifies the location of the external differential clock inputs 06069 v1 0 March 8 2005 www xilinx com 23 5 XILINX Chapter 2 Using the System Casters SE sC TES ON tennis ME MGT TXP NM o MGT MGT RXN ELA vVIRTEX H xx PRO IJ LITE 21 13 Figure 2 4 External Differential Clock Inputs The alternate clock input is obtained from a user supplied 3 3V oscillator The footprint on the printed circuit board supports either a full size 21mm x 13mm or half size 13mm 13mm through hole oscillator Figure 2 5 identifies the location of the alternate clock input oscillator 1 mise Figure 2 5 Alternate Clock Input Oscillator Using the DIMM Module DDR
139. ons Continued Signal Direction MIC n je Type SDRAM_DQJ 8 I O 12 26 SSTL2 II SDRAM I O 13 G27 SSTL2 II SDRAM DO 10 I O 19 G28 SSTL2 II SDRAM DO 11 I O 20 G30 SSTL2 II SDRAM DQ 12 I O 105 L23 SSTL2 II SDRAM_DQ 13 I O 106 L24 SSTL2 II SDRAM DQ 14 I O 109 H27 SSTL2 II SDRAM DOQ 15 I O 110 H28 SSTL2 II SDRAM DOS 1 I O 14 J29 SSTL2 II SDRAM DM I1 0 107 V29 SSTL2 II SDRAM DO 16 I O 23 27 SSTL2 II SDRAM DQ 17 I O 24 j28 SSTL2 II SDRAM DO 18 I O 28 K29 SSTL2 II SDRAM DO 19 I O 31 L29 SSTL2 II SDRAM DO 20 I O 114 N23 SSTL2 II SDRAM_DQ 21 I O 117 N24 SSTL2 II SDRAM_DQ 22 I O 121 K27 SSTL2 II SDRAM_DQ 23 I O 123 K28 SSTL2 II SDRAM DOS 2 I O 25 M30 SSTL2 II SDRAM DM 2 0 119 W29 SSTL2 II SDRAM DO 24 I O 33 R22 SSTL2 II SDRAM_DQ 25 I O 35 M27 SSTL2 II SDRAM DO 26 I O 39 M28 SSTL2 II SDRAM_DQ 27 I O 40 P30 SSTL2 II SDRAM_DQ 28 I O 126 P23 SSTL2 II SDRAM DO 29 I O 127 P24 SSTL2 II SDRAM DO 30 I O 131 N27 SSTL2 II SDRAM_DQJ 31 I O 133 N28 SSTL2 II SDRAM DOS 3 I O 36 P29 SSTL2 II SDRAM DM 3 0 129 22 SSTL2 II ISDRAM WO 535 VZ 5624 Virtex ll Pro Development System www xilinx com 31 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Table 2 5 DDR SDRAM Connections Continued
140. ons Output Help 0 c X Ge es 88 12 52 131 e 2 O Boundary Scan Slave Serial SelectMAP Desktop Configuration Add Device Add Non Xiinx Device Initialize Chain Cable Auto Connect Cable Setup Right click to Add Device or Initialize JTAG chain 29 For Help press Configuration Mode Boundary Scan Platform Cable USB usb hs 12 2 4 Figure A 4 Initializing the JTAG Chain A status bar on the bottom edge of the iMPACT GUI provides useful information about the operating conditions of the software and the attached cable If the host port is USB 1 1 Platform Cable USB connects at full speed and the status bar shows usb fs If the host port is USB 2 0 Platform Cable USB connects at high speed and the status bar shows usb hs The active JTAG TCK speed is shown in the right hand corner of the status bar Figure 4 shows a Platform Cable USB connected at high speed using a Boundary Scan Configuration Mode with a JTAG TCK of 12 MHz If there are no configurable expansion boards attached to the basic system the Initialize Chain command should identify three devices in the chain the Plattorm FLASH PROM XCF32D followed by the System ACE controller XCCACE and followed by the FPGA XC2VP30 Any programmable devices on expansion boards follow the FPGA in the configuration chain A properly identified JTAG configuration chain for the basic system is s
141. ontrol Window Help XUP U2Pro BuiltIn Self Test Main Menu Rev 1 8 12 13 2004 Test SATA port with Aurora loopback Test Ethernet with WEB example Test 97 audio codec Test System ACE Test DDR SDRAM MAC Address 88 11 22 33 44 55 make sure it is allowed in your network Input your IP address hit ENTER directly for default previous address 192 168 0 3 Figure D 11 Specifying IP Address for Virtex Il Pro Development System Note the following issues a For this test the MAC address of the board is set to 00 11 22 33 44 55 If your LAN needs you to register your MAC address to enable access please contact your LAN manager to register this MAC address However if you use a crossover cable this issue does not apply b Inputa valid IP address for your LAN environment If it is fixed based on the MAC address contact your LAN manager for the IP address If you usea crossover cable use the default IP address c Bypressing ENTER directly after prompted to input the IP address the Web server will use the default IP address as 192 168 0 2 Or you can input your desired IP address in dot decimal format and press ENTER when finished d Backspace is not supported currently So if you typed the wrong IP address do not use backspace Just press ENTER and you can correct it later e After you press ENTER you will be prompted to verify your IP address If you
142. orts two Host ports and one Target port e Off board expansion MGT link with user supplied clock 100 MHz system clock 75 MHz SATA clock e Provision for user supplied clock On board power supplies e Power on reset circuitry PowerPC 405 reset circuitry Virtex ll Pro Development System www xilinx com 13 06069 v1 0 March 8 2005 XILINX Chapter 1 Virtex ll Pro Development System General Description The XUP Virtex II Pro Development System provides an advanced hardware platform that consists of a high performance Virtex II Pro Platform FPGA surrounded by a comprehensive collection of peripheral components that can be used to create a complex system and to demonstrate the capability of the Virtex II Pro Platform FPGA Block Diagram CPU Debug Port lt gt 100 MHz System Clock 75 MHz SATA Clock User Clocks 2 Platform Flash Configurations 2 Compact Flash Configurations 8 USB2 High Speed Configuration Figure 1 1 shows a block diagram of the XUP Virtex II Pro Development System External Power Internal Power Supplies 3 3V 2 5V 1 5V AC97 Audio CODEC amp Stereo Amp XSGA Video Output User LEDs 4 User Switches 4 User Push button Switches 5 Virtex ll Pro 10 100 Ethernet PHY FPGA RS 232 amp PS 2 Ports 2 Serial ATA Ports 3 Multi Gigabit Transceiver Port 2 GB DDR SDRAM DIMM Module 5V Tolerant Expansion Headers Hig
143. pact Flash socket and storage device for the existence of configuration data If configuration data exists on the storage device the storage device becomes the source for the configuration data The file structure on the Compact Flash storage device supports up to eight different configuration data files selected by the triple CF CONFIG SELECT DIP switch SW8 During JTAG configuration the SYSTEMACE STATUS LED D12 flashes until the configuration process is completed and the FPGA asserts the DONE signal and illuminates the DONE LED D4 At any time the RESET RELOAD pushbutton SW1 can be used to load any of the eight different configuration data files by pressing the switch for more than 2 seconds If a JTAG based configuration is selected and a valid configuration file is not found on the Compact Flash card by the System ACE controller U2 the SYSTEMACE ERROR LED D11 flashes and the System ACE controller connects to an external JTAG port for FPGA configuration The default external source for FPGA configuration is the high speed embedded Platform Cable USB configuration port J8 and is enabled when the System ACE controller does not find configuration data on the storage device Detailed instructions on using the high speed Platform Cable USB interface can be found in Appendix A Configuring the FPGA from the Embedded USB Configuration Port If a USB equipped host PC is not available as a configuration source then a Paralle
144. pansion Connectors A total of 80 Virtex II Pro I O pins are brought out to four user supplied 60 pin headers and two 40 pin right angle connectors for user defined use The 60 pin headers are designed to accept ribbon cable connectors with every second signal a ground for signal integrity Some of these signals are shared with the front mounted right angle connectors The front mounted connectors support Digilent expansion modules In addition a high speed connector is provided to support Digilent high speed expansion modules This connector provides 40 single ended or differential I O signals in addition to three clocks Consult the Digilent website at www diglentinc com for a list of expansion boards that are compatible with the XUP Virtex II Pro Development System XSGA Output The Virtex lI Pro Development System includes a video DAC and 15 pin high density D sub connector to support XSGA output The video DAC can operate with a pixel clock of up to 180 MHz This allows for a VESA compatible output of 1280 x 1024 at 75 Hz refresh and a maximum resolution of 1600 x 1200 at 70 Hz refresh AC97 Audio CODEC An audio CODEC and stereo power amplifier are included on the Virtex II Pro Development System to provide a high quality audio path and provide all of the analog functionality in a PC audio system It features a full duplex stereo ADC and DAC with an analog mixer combining the line level inputs microphone input and PCM d
145. r 26 Figure 2 8 EEPROM Sequential Read 26 Figure 2 9 EEPROM Write oiii eR SG pee ROE EES F 26 Figure 2 10 Clock Generation for the 5 29 Figure 2 11 XSGA Output ee ee piepe hehe atake ass e onp ne d 36 Figure 2 12 AC97 Audio CODEC 41 Figure 2 13 Audio Power 42 Figure 2 14 Expansion 44 Figure 2 15 CPU Debug Connector 59 Figure 2 16 RELOAD and CPU RESET Circuit 60 Figure 2 17 RS 232 Serial Port 61 Figure 2 18 PS 2 Serial Port Implementation 62 Figure 2 19 10 100 Ethernet Interface Block 64 Figure 2 20 SMA based MGT Connections 68 Figure 2 21 1 5 Gb s Serial Data Transmission over 0 5 meter of SATA Cable 70 Figure 2 22 1 5 Gb s Serial Data Transmission over 1 0 meter of SATA Cable 70 Appendix A Configuring the FPGA from the Embedded USB Configuration Port Figure 1 Device Manager Cable 72 Figure
146. rallel Ill MultiLINX Serial Parallel Iv MultiLINX USB MultiPRO Platform Cable USB TCK Speed Baud Rate Port Figure A 3 iMPACT Cable Communication Setup Dialog Regardless of the native communications speed of the host USB port target devices can be clocked at any of six different frequencies by making the appropriate selection in the TCK Speed Baud Rate drop down list The default clock rate of 6 MHz is selected by iMPACT because all Xilinx devices are guaranteed to be programmed at that rate The basic XUP Virtex II Pro Development System contains a Platform FLASH PROM and a Virtex II Pro FPGA This combination of devices does not support the maximum JTAG TCK clock frequency This means that the Speed Baud Rate could be set to 12 MHz If expansion circuit boards that contain programmable devices are added to the basic system the user must ensure that the JTAG clock frequency does not exceed the capability of the additional devices Virtex ll Pro Development System www xilinx com 73 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix A Configuring the FPGA from the Embedded USB Configuration Port After the programming cable type and speed has been selected the JTAG chain must be defined Right click in the iMPACT window and select Initialize Chain from the drop down menu shown in Figure A 4 5 untied Configuration Mode 2 Edit View Mode Operati
147. re D 9 SATA Test Running The test automatically terminates once 1000 frames of data have been transmitted The test status is then displayed If both transceiver channels established a link and if there were no dropped frames dropped words hard errors soft errors or framing errors then the display reports the two tested transceivers passed with the message SATA loopback test PASSED as shown in Figure D 10 To test the third serial ATA port reconnect the serial ATA cable between the untested serial ATA host port and the serial ATA target After reconnecting the cable the user can restart the test selecting the other choice from MGT SATA Test Menu and repeat the previous steps Virtex ll Pro Development System www xilinx com 105 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test Tera Term COMI VT File Edit Setup Control Window Help Aurora Status i Aurora 1 TX Frames 64kdi 1038 1038 Words 64k 66455 66455 TR CCs 64kd 1 13 13 RZ Rate Mbps i 1163 1163 Frames 64k 1038 1038 RX Words 64k 66455 66455 Dropped Frames Dropped Words 1 Hard Errors i a a Soft Errors i a a Framing Errors a a Link i 1 1 Pattern i sequential sequential Frame Size i 64 LoopBack i an an PowerDoun i a a 1 Toggle Auroral Pattern 7 Toggle Aurorai Pattern 2 Toggle fiuroraB RndFmSz 81 Toggle A
148. re Required e 9 pin male to female straight through serial communications RS 232 cable 102 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Processor Based Tests XILINX PC running Hyper Terminal or similar terminal program One 1 5 Gb s rated serial ATA cable e One 1 5 Gb s rated serial ATA cable This test begins when the 1 is selected from the Built In Self Test Main Menu displayed on the terminal window The board should already have a serial ATA cable connected in a looped back configuration between serial ATA 0 HOST and serial ATA 1 Target or between serial ATA 2 HOST and serial ATA 1 Target See Figure D 3 and Figure D 4 Figure D 4 Testing the SATA 2 HOST to SATA 1 TARGET Connection Note While either test is running all three of the MGTs connected to the serial ATA connectors are active but the test software is only monitoring one pair at a time If you select the wrong loop pair to test the target can transmit and receive data frames but you would be monitoring the wrong loop pair of transceivers Thus the test will fail Virtex ll Pro Development System www xilinx com 103 UG069 v1 0 March 8 2005 1 800 255 7778 7 XILINX 104 Appendix D Using the Golden FPGA Configuration for System Self Test 6 user is prompted to select which loop to test Figure D 5 Tera Term 1 VT File Edit Setup Control Window Help
149. rks of Xilinx Inc The Programmable Logic Company is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents
150. rm Cable USB is a RAM based product Application code is downloaded each time the cable is detected by the host operating system USB protocol guarantees that the application code is successfully transmitted All necessary firmware files are included with every Foundation ISE software installation CD Revised firmware can be periodically distributed in subsequent software releases The embedded Platform Cable USB can be attached and removed from the host computer without the need to power down or reboot the host computer When the embedded Platform Cable is detected by the operating system a Programming Cables folder is displayed if the System Properties gt Hardware gt Device Manager dialog box is selected A Xilinx Platform Cable USB entry resides in this folder as shown in Figure A 1 Virtex ll Pro Development System www xilinx com 71 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix A Configuring the FPGA from the Embedded USB Configuration Port fl Device Manager Action View Help lt gt XSJ RICKB WA Batteries Computer Disk drives Display adapters gt DVD CD ROM drives IDE ATA ATAPI controllers 8 IEEE 1394 Bus host controllers Imaging devices gt Keyboards 773 Mice and other pointing devices Modems Monitors BI Network adapters PCMCIA adapters Ports COM amp LPT sik Processors Programming cables HA Xilinx Platform Cable USB ue Smart card readers
151. s web sites for the various components used in this system FPGA Related Documentation e Virtex II Pro Complete Data Sheet http direct xilinx com bvdocs datasheets ds083 pdf e Virtex lI Pro Platform FPGA User Guide http direct xilinx com bvdocs userguides ug012 pdf RocketIO Transceiver User Guide http direct xilinx com bvdocs userguides ug024 pdf PowerPC 405 Processor Block Reference Guide http direct xilinx com bvdocs userguides ug018 pdf e PowerPC Processor Reference Guide http direct xilinx com bvdocs userguides ppc ref guide pdf Configuration Sources System ACE CompactFlash Solution http direct xilinx com bvdocs publications ds080 pdf e Platform Flash In System Programmable Configuration PROMs http direct xilinx com bvdocs publications ds123 pdf DDR SDRAM Modules 64 MB x 64 bit Non ECC Dual Rank Unbuffered DIMM http www micron com products modules ddrsdram part aspx part MT16VDDT6464AG 265 e 32MBx8 TSOP DDR SDRAM http download micron com pdf datasheets dram ddr 256MBDDRx4x8x16 pdf Virtex ll Pro Development System www xilinx com 137 UG069 v1 0 March 8 2005 1 800 255 7778 5 XILINX Appendix F Links to the Component Data Sheets Audio Processing 97 Multi Channel Audio Codec http cache national com ds LM LMA550 pdf e 150 mW Stereo Audio Power Amplifier http focus ti com lit ds symlink tpa6111a2 pdf XSGA Vid
152. set to allow for auto negotiation 10 Mb s or 100 Mb s full duplex or half duplex operation These settings can be overridden by setting control bits in the Media Independent Interface MII registers The slew rate of the transmitter outputs is controlled by the two slew control inputs It is recommended that the slowest slew rate be set by driving both of the slew inputs with a logical 1 Three LEDs are available to provide visual status information about the Ethernet link connection If a link has been established the LINK UP LED is turned on If the link is a 100 Mb s link then the SPEED LED also turns on The RX DATA LED blinks indicating that packets are being received Setting control bits in the MII registers can alter the function of the three LEDs The LX972A provides the interface to the physical media the MAC resides in the FPGA and is available as an IP core The 10 100 Ethernet requires transformer coupling between the PHY and the RJ 45 connector to provide electrical protection to the system The magnetics used on the XUP Virtex II Pro Development System are integrated into the RJ45 connector J10 from the FastJack series of connectors from Halo Electronics Inc The HFJ11 2450 provides a significant real estate reduction over non integrated solutions Table 2 18 identifies the connections between the FPGA and the PHY The type of network cable that is used with the XUP Virtex II Pro Development System depends on how the s
153. t strategies a series of processor centric tests and pure hardware non processor centric tests The pure hardware tests are used to verify the most basic functions of the system and to provide a platform on which the processor centric tests can build Hardware Based Tests These tests should be run in the order listed because each test design can require a positive result from a previous test Power Supply and RESET Test 98 This test verifies the correct operation of the on board power supplies and system RESET generation circuitry Additional Hardware Required external power supply e Multimeter e Shorting Jumper Block Test Procedure 1 Verify that three Shorting Jumper Blocks are installed in JP1 JP2 and JP3 2 Plug in the external 5V power supply and turn on the board by sliding SW11 up towards the ON label 3 Connect the negative lead of the multimeter to J31 and the positive lead to J30 The meter should read between 2 375V and 2 625V and LED D17 2 5V OK should be on 4 Connect the negative lead of the multimeter to J33 and the positive lead to J32 The meter should read between 3 135V and 3 465V and LED D18 3 3V OK should be on www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Hardware Based Tests XILINX 5 Connect the negative lead of the multimeter to J35 and the positive lead to J34 The meter should read between 1 425V and
154. ted Register 4 column address count only devices with 10 column addresses are supported Register 5 rank count single and dual rank devices rank count 1 or 2 are supported Once a valid memory device has been detected the memory test begins The complete memory verification consists of the following tests Data bus walking 1 s test Data bus walking 075 test Address bus walking 1 s test Address bus walking 0 s test Device pattern test a counter value is written to each memory location then read back Device inverse pattern test the inverse of the counter value is written to each memory location then read back Additional Hardware Required A 64M x 64 or 64M x 72 dual rank DDR SDRAM module properly seated in the memory slot Test Procedure 1 After the DDR SDRAM test is selected from the BIST Main Menu the test begins immediately with the serial presence detect If a supported module is detected the complete memory verification begins for each available rank The terminal window output for the DDR SDRAM test is shown in Figure D 20 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Processor Based Tests B Tera Term COM1 VT File Edit Setup Control Window Help SDRAM Module Detection Data Walking 1 s Test Data Walking s Test Address Walking 1 s Test Address Walking s Test Device Pattern 1 Test Device Pattern 2 Test
155. ting resources that reduce jitter BREFCLK enters the FPGA through a dedicated clock input buffer BREFCLK can connect to the BREFCLK inputs of the MGT and the CLKIN input of a DCM for creation of user clocks The SATA data rate is less than 2 5 Gb s so the 75 MHz clocks could have been supplied in the REFCLK inputs but for consistency the BREFCLK and BREFCLK2 clock inputs used for the on board and user supplied MGT clocks as shown in Table 2 21 Table 2 21 SATA and MGT Signals Signal MGT Location PAD Name I O Pin Notes SATA PORTO MGIX0Yl TXNPAD4 A27 HOST SATA PORTO TXP X0Y1 4 26 SATA PORTO RXN 0 1 RXNPAD4 A24 SATA PORTO 0 1 RXPPAD4 A25 www xilinx com Virtex ll Pro Development System UG069 v1 0 March 8 2005 Using the Multi Gigabit Transceivers XILINX Table 2 21 SATA and MGT Signals Continued Signal MGT Location PAD Name I O Pin Notes SATA_PORTO_IDLE B15 SATA PORTI MGT X1Y1 TXNPAD6 A20 TARGET SATA PORTI TXP X1Y1 TXPPAD6 A19 SATA PORTI RXN X1Y1 RXNPAD6 A17 SATA PORTI X1Y1 RXPPAD6 A18 SATA PORTI IDLE SATA PORT2 MGT X2Y1 TXNPAD7 A14 HOST SATA PORT2 TXP 2 1 TXPPAD7 A13 SATA PORT2 RXN X2Y1 RXNPAD7 SATA 2 X2Y1
156. tus Figure D 1 shows BIST block diagram Figure D 1 XUP Virtex ll Pro Development System BIST Block Diagram 06069 20 010605 Appendix C Restoring the Golden FPGA Configuration of this document covers the details of restoring the BIST design if it has been erased accidentally This feature puts the board through several tests to verify the board is fully functional in a stand alone environment Other tests to verify system level functionality can be supported via Virtex ll Pro Development System www xilinx com 97 UG069 v1 0 March 8 2005 1 800 255 7778 XILINX Appendix D Using the Golden FPGA Configuration for System Self Test Compact Flash or download but the Golden Boot has been designed to verify that the board is not damaged due to user abuse This mode allows the user to verify that the board itself is not the root cause of a design failing to function properly The BIST is a combination of pure hardware and processor centric tests combined into one FPGA design The Golden Boot design covers the following elements of the system Clock presence Push buttons DIP switches and LEDs Audio CODEC and power amplifier RS 232 serial ports and PS 2 ports SVGA output 10 100 Ethernet and Silicon Serial Number Expansion ports MGTs System ACE processor interface 10 DDR SDRAM module and Serial Presence Detect PROM gt oO The BIST consists of two different tes
157. urorai RndFmSz 131 Toggle fiuroraB P LpBk 9 Toggle Aurorai P LpBk 41 Toggle fiuroraB S LpBk Toggle Auroral S LpBk 51 Toggle fiuroraB PurDun 1 Toggle Auroral PurDun 1 Reset Both MGTs q Quit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Li 1 i 1 1 1 1 ATA loopback test PASSED q to retrun to preuious menu i Figure D 10 SATA Loopback PASSED EMAC Web Server Test This test begins when 2 is selected from the BIST Main Menu It verifies the operation of the EMAC controller the functionality of the EMAC PHY and the connection between the EMAC controller and the PHY by running a simple Web server on the PowerPC Additional Hardware Required An Ethernet cable plugged into the RJA5 connector of the Virtex II Pro Development System which connects to a LAN and a PC that also connects to the same LAN e Or you can use a crossover cable that connects the Virtex II Pro Development System directly to the PC EMAC Web Server Test Procedure 1 After selecting 2 in the BIST Main Menu you will be prompted to enter the IP address for the XUP board as shown in Figure D 11 106 www xilinx com Virtex ll Pro Development System 1 800 255 7778 06069 v1 0 March 8 2005 Processor Based Tests XILINX amp Tera Term COM1 VT File Edit Setup C
158. ww xilinx com Virtex ll Pro Development System UGO69 v1 0 March 8 2005 Using the XSGA Output XILINX Design files supplied by Xilinx generate the required timing signals VGA OUT BLANK Z VGA HSYNCH VSYNCH VGA SYNCH well as memory addressing for bit and character mapped display RAM Character mapped mode allows for the display of extended ASCII characters in an 8 x 8 pixel block without having to draw the character pixel by pixel Compile time parameters are passed to the Verilog code that defines the XSGA controller operation The 100 MHz clock is used as a source for one of the DCMs to create the video clock By setting appropriate M and D values for the DCM various VGA OUT PIXEL CLOCK rates can be created Virtex ll Pro Development System www xilinx com 35 06069 v1 0 March 8 2005 Using the System Chapter 2 7 XILINX 708101 L 690911 AN NIdSL OH 1 9928 lt HONASA INdLNO VOA Yl 8888 lt HONASH Yl 0892 A anto 961 0892 8 6 8970 9 ANAKAKAKA 96 0892 8 8 5 4 8 PV LE 86 92 8 ve ze L s t 0 sr 12 OON
159. ystem is connected to the network If the XUP Virtex II Pro Development System is connected directly to a host computer then a cross over Ethernet cable is required However if the system is connected to the network through a hub or router then a normal straight through Ethernet cable is required Virtex ll Pro Development System www xilinx com 63 06069 v1 0 March 8 2005 XILINX Chapter 2 Using the System Figure 2 19 provides a block diagram of the Ethernet interface TX ERROR LXT972A TX_ENABLE TX DATA 3 0 TX CLOCK RX CLOCK DATA 3 0 Magnetics RJ 45 RX ERROR RX DATA VALID CARRIER SENSE COLLISION MDC 00069 19 012505 Figure 2 19 10 100 Ethernet Interface Block Diagram The Virtex II Pro Development System includes a Dallas Semiconductor DS2401P Silicon Serial Number U13 This device provides a unique identity for each circuit board which can be determined with a minimal electronic interface The DS2401P consists of a factory laser programmed 64 bit ROM that includes a unique 48 bit serial number an 8 bit CRC and an 8 bit family device code Data is transferred serially via the 1 Wire protocol which requires only a single data lead and a ground return Power for reading the device is derived from the data line with no requirement for an additional power supply The unique 48 bit serial number should not be used as the MAC

Download Pdf Manuals

Related Search

Related Contents

- KINZE Manufacturing, Inc.  Di 18 Bruxelles (SeMob)  Handbuch - Austin Canoe and Kayak  Bandelettes de Glycémie Mode d`Emploi  Embajada de la República Argentina en Cuba  City of Lincoln/Lancaster County  OMNUC R88D-RP Series User's Manual  Echo CS-3000 User's Manual  Manuel propriétaire - Chantier Naval JEANNEAU  FEDKIT FEDKIT user`s manual and programer`s manual  

Copyright © All rights reserved. Failed to retrieve file