Hitachi Single-Chip Microcomputer H8/3102 HD6483102 User`s
Contents
1. Y tb Input buffer Input pull up MOS always switched on Voc Falling edge detector DR read Sleep mode MN Sleep mode DDR6 Q CK DDR write DR6 Vo 2 __Vss F 4 IRQ Output buffer Q PR Input buffer DR read Figure D 1 I O Port Block Diagram 81 External interrupt request to CPU Appendix E External Dimensions Figure E 1 shows the external dimensions of the H8 3102 microcomputer COB standard pattern Figure E 1 External Dimensions 822. 9 2 9 Data 10 2 3 1 Data Formats in General REGS ers 11 23 2 Memory Data Formats ere se PO rtu qa aS 12 242 cie ut Ragam di 13 241 Addressing sso nire n REEL tarea ROUES de to Ecc Re 13 Effective Address Calculation do Gus invades de ede dea hne dubbed a aa DN 15 2 3 Instruction 2 Ste oa Sed 18 Zoe Data Trans ter Instructions S sistat SIR UIS MOT ipto E E RN a eit taie aq nes 20 2 5 2 Operations ies a 22 dx pve oe Ld a one 23 2 344 Shift Operations 23 29 cheeses ideo te 25 2 040 Branching 20 225 System Control UE UNT 31 2 3 8 EEPROM Write 32 206 APE AUIS sale Sostieni pecu 33 2 0 SQVERVIEW E 33 20 Program BXECUUON pepe dodi diutina npe boa den qu 34 210 3 gt Bxeeption Processing S le cioe eo bt tape e a acria aa tuts 34 20 Power Se erede 34 2 7 JBxcepuon Processmg uoa ee DIU EO IIR UIS D Hie 35 2 7
3. When a low to high transition of RES is detected the CPU begins reset exception processing which in the H8 3102 consists of the following steps 1 The low to high transition of the RES input is detected 2 The internal status of the CPU and the registers of the on chip supporting modules are initialized In the CCR the I bit is set to 1 but other bits are left unchanged 3 The reset vector is read from addresses H 0000 to H 0001 in the vector table and loaded into the program counter Program execution then starts from the loaded address start address Figure 2 13 shows the timing of the reset sequence 35 95 External clock Voc Internal address bus Internal read signal Internal write signal Internal data size signal Internal data bus ELITE TST II e N Tee WAV uu WAY A 1 Address of reset vector 2 Reset start address contents of reset vector 3 First instruction of reset routine Figure 2 13 Reset Start Timing 2 7 3 Interrupts In sleep mode only the pin functions as an interrupt pin and is capable of input The IRQ interrupt uses falling edge detection and an interrupt request is accepted if the I bit in CCR is cleared to 0 The interrupt sequence consists of the following steps It When the interrupt request is accepted a transition takes place from the sleep mode to the exception proc
4. es eas 63 9 2 1 DE Characteristics 63 92 2 AC Characteristics 5 M sia tee eres 64 9 2 3 DC Characteristics 3 V ied tetto eine eie 66 924 AC Characteristics 3 deett eres Pane ET I e e EVE EUN ed 67 Appendices Appendix Instruction 69 Appendix Operation Code Map ia ea asit 76 Appendix C Register Field ade o e 78 CST Register 78 52 Resister 2 Me cel Meis ident S 79 Appendix D Port Block 81 Appendix E External DIMENSIONS oec DH dne ad de 82 Section 1 Overview 1 1 Overview The H8 3102 is a single chip microcomputer built around a high speed H8 300 CPU core An 8 kbyte EEPROM 16 kbyte ROM 512 byte RAM and 2 bit I O port are integrated onto the H8 3102 chip Operating at a maximum 5 clock rate at 5 V the H8 300 CPU rapidly executes bit manipulation instructions arithmetic and logic instructions and data transfer instructions Security functions protect the data in the ROM and EEPROM Table 1 1 lists the features of the H8 3102 Table 1 1 Features Item Specification CPU H8 300 CPU Two way general register configuration e Sixteen 8 bit registers or Eight 16 bit registers High speed operation Maximum clock rate 5 MHz with 10 MHz external clock input at 5 V Add subtract 0 4 us e Multiply divide 2 8 us Streamlined concise inst
5. mE I O port H FFFF DDR DDR7 DDR6 78 C 2 Register Field 2 ECR EEPROM Control Register EEPROM Bit 7 6 5 4 3 2 1 0 E PWR oct Initial value 1 1 1 R W R W R W 0 Rewrite 1 Overwrite 0 Page erase 1 Write erase disabled Power Bit Set to 1 when a drop in the internal supply voltage is detected EPR EEPROM Protect Register EEPROM Bit 7 6 5 4 3 2 1 0 PBM Initial value R W 2 Protect Bit Mode 0 Protection area 1 Data area 79 DR Data Register Bit 7 6 0 DR7 DR6 Initial value R W RW RW Data Register Bit 6 Data Register Bit 7 Output data latch Output data latch DDR Data Direction Register y o Bit 7 6 0 DDR7 DDR6 Initial value 0 0 R W WwW WwW Data Direction Register Bit 6 Selects the input output direction of 2 o Tiru 1 Output Data Direction Register Bit 7 Selects the input output direction of 1 o Timur 1 80 Appendix D I O Port Block Diagram Input pull up MOS always switched on Voc Vss Sleep mode Internal data bus DDR write DR7 Output buffer Qe D DR write
6. Write erase protected pages Figure 6 10 Example of Write Erase Protection 6 5 2 Protection Procedure To protect a page software must set the EPR and ECR registers then write the protection code H 78 in the protect bits The protection procedure is given next Figure 6 11 shows a flowchart 1 Clear the PBM bit in the EPR to 0 to select the protection area The and bits in the ECR will then be automatically set to 1 disabling EEPROM writing and erasing 2 Clear the OCI bit in the ECR to 0 The OCO bit may be set to either 1 or 0 3 Execute the EEPMOV instruction to write the protection code H 78 in the protect bits The address of the protect bits is the same as the top byte address on the page to be protected After the protection code has been written the EPR automatically reverts to select the data area and the ECR is set to the write erase disabled state OC1 1 53 Steps 1 to 3 must be carried out for each page protected Protect bits H 78 Figure 6 11 Protection Flowchart 6 5 3 Reading the Protect Bits When the PBM bit in the EPR is cleared to 0 the protect bits can be read The protect bits for a protected page are read as H FC The protect bits for an unprotected page are read as H FF 6 6 Notes When using the EEPROM note the following points 1 Write Erase Abort The reset signal input to circuits other than the EEPROM including the CPU is synchronized with
7. 6 3 EEPROM Read eec eto team UO 48 6 4 EEPROM Write and Erase Operations ot p te e es PAM oa 49 OL Wrte Erdse 49 Q2 T 51 scisco e ET 51 6 4 4 COVER WHE A ode Me 52 6 5 Write Erase PrOtectIOnzz ier Idee EE ND EE S 52 6 3 NI ee do det 52 622 22 Protection Procedure en UO tr eden dde seo tds eo reheat 53 6 5 5 Reudme he Protect Oi Maserati unte anaemia 54 6 6 54 gt MO 56 d AG eua venues tM Stc EL M 56 ERnEEBUV ddr 57 Pell Config UA ON nieto eiii des een 58 Js Register Description a e bu d 58 58 7 222 Data Direction Register DDR esee es lees tetuer 59 159 SPI yc st autetn 60 T4 VO Pir MNS 61 Section 8 Clock Pulse Generator soins ee P Rd E ERR tas den 62 62 Section 9 Electrical Characteristics 63 91 Absolute Maximum Ratings 63 92 PSCC A
8. Size operand size B Byte W Word 20 Figure 2 5 shows the object code formats of the data transfer instructions MOV Hn lt gt d 16 Rm lt Rn Rm Rn Rn gt aa 8 lt Rn aa 16 gt Rn 16 gt Rn POP PUS Notation Operation field Register field Displacement Absolute address Immediate data Figure 2 5 Data Transfer Instruction Object Code Formats 21 2 5 2 Arithmetic Operations Table 2 5 describes the arithmetic instructions Table 2 5 Arithmetic Instructions Instruction Size Function ADD B W Rs gt Rd Rd SUB Performs addition or subtraction on data in two general registers or addition on immediate data and data in a general register Immediate data cannot be subtracted from data in a general register Word data can be added or subtracted only when both words are in general registers ADDX B Rs Rd SUBX Performs addition or subtraction with carry or borrow on byte data in two general registers or on immediate data and data in a general register INC B Rd 1 Rd DEC Increments or decrements a general register ADDS W 1 Rd 2 gt Rd SUBS Adds or subtracts immediate data to or from data in a general register The immediate data must be 1 or 2 DAA B Rd decimal adjust DAS Decimal adjusts 4 bit BCD data
9. 0 3 port 2 0 Voc 0 3 Input low level RES Vib 0 3 0 6 V CLK 0 3 0 5 port 0 3 0 8 Output high level 100 pA 2 4 Voc V lou 20 uA 3 8 Vcc Output low level VoL logi 1 mA 0 0 4 V Input leakage RES Vin 0 5 V 10 SUE CLK Vi 0 510 0 5 V 40 Input pull down RES ld Vin Voc 150 MOS current normal operation Input pull up port lp 150 MOS current 3 Current Normal lcc 10 MHz 20 mA consumption operation 5 MHz 10 Sleep port 100 mode Vec 0 5 V to Voc 3 63 Measurement Parameter Symbol Conditions Min Typ Max Unit Pin capacitance Die Cp Vin 0 V 15 pF fci 1 MHZ 5 COB 25 Notes 1 Input pull down MOS is cut off during sleep mode 2 3 4 5 Normal operation means states except for sleep mode Input pull up MOS in I O port is always switched on even during sleep mode To decrease the input pull up MOS current high level should be input to the I O port during sleep mode if the port is being used If the I O port is not being used leave the port pin open Current consumption assumes that 0 5 V 0 5 V and all output lines unloaded is the external clock frequency 9 2 2 AC Characteristics 5 V Conditions Vec 4 5 to
10. 5 5 V Vss 0 V T4 20 to 75 C regular specifications 40 to 85 C wide range specifications unless otherwise specified Parameter Symbol Conditions Min Typ Max Unit Clock cycle time Figure 9 1 0 1 1 0 us Clock high width tou Figure 9 1 0 4 0 6 Clock low width Figure 9 1 0 4 m 0 6 Clock fall time let Figure 9 1 10 ns Clock rise time ler Figure 9 1 m 10 ns port fall time ti Figure 9 2 1 0 us port rise time Figure 9 2 1 0 us RES pulse width tRwL Figure 9 3 20 love EEPROM write time tepw 10 15 ms Clock hold time teLKH Figure 9 4 20 toye Clock setup time tcLks Figure 9 4 20 Interrupt pulse width IRQ Figure 9 4 200 ns Figure 9 1 CLK Input Waveform 4 5 V to 5 5 V 64 port input Figure 9 2 I O Port Input Waveform Vcc 4 5 V to 5 5 V 0 6 V ii tRWL tRWL a Power on reset Reset input at opening state Figure 9 3 RESET Input Timing 4 5 V to 5 5 V CLK 0 to 10 MHz 4 l O 1 IRQ
11. In addition the final values left in the registers after instruction execution may not be the values indicated in table 6 2 Figure 6 6 shows the sequence to be performed by software for writing or erasing the EEPROM 50 Store write data in RAM Set parameters in CPU registers R4L R5 R6 Set Execute EEPROM write erase instruction EEPMOV Figure 6 6 EEPROM Write Erase Sequence After an EEPMOV instruction the CPU does not execute the next instruction until the writing or erasing of EEPROM data has ended EEPROM data cannot be written or erased by instructions other than EEPMOV 6 4 2 Rewrite A single rewrite operation can modify the values of 1 to 32 contiguous bytes located in the same EEPROM page A rewrite operation is restricted to a single page The byte counter RAL and EEPROM address register R6 should be set so that the operation does not cross a page boundary To perform a rewrite operation clear both OC1 and OCO to 0 6 4 3 Erase When the instruction is executed with OC1 1 and 0 the relevant EEPROM page is erased The entire page containing the byte addressed by the EEPROM address register R6 is erased All data in the page are changed to 1 The byte counter R4L and RAM address register R5 can be set to any valid values 51 EEPROM PageN 2 Page N 2 Page N 1 Page N 1 Page N Page N Figure 6 7 EEPROM Eras
12. Operation field Figure 2 10 EEPROM Write Instruction Object Code Format 32 2 6 Operating States 2 6 1 Overview The CPU operates in three states the program execution state exception processing state and power down state Figure 2 11 summarizes these states Figure 2 12 shows the state transitions Chip state Program execution state CPU executes program Exception processing state Transitory state that changes CPU execution flow at a reset or interrupt Power down state Sleep mode CPU halts to conserve power Figure 2 11 Operating States C Program execution state End of exception processing RES 0 SLEEP instruction E Exception processing state Reset state Figure 2 12 State Transitions 33 2 6 2 Program Execution State In this state the CPU executes program instructions in normal sequence 2 6 3 Exception Processing State This is a transitory state entered in response to a reset or interrupt In interrupt exception processing the stack pointer is referenced and the program counter and condition code register are saved 2 6 4 Power Down State The power down state consists of a sleep mode Sleep mode is entered from program execution state when the SLEEP instruction is executed Operation of the CPU clocks and all other on chip supporting modules is halted The on chip supporting modules enter the reset state but the contents of CPU registers and on ch
13. a specified bit in a general register or memory to 0 The bit number is specified by 3 bit immediate data or the lower three bits of a general register BNOT B lt bit No gt of lt EAd gt lt bit No gt of lt EAd gt Inverts a specified bit in a general register or memory The bit number is specified by 3 bit immediate data or the lower three bits of a general register BTST B bit No of lt EAd gt 2 Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of lt EAd gt gt C ANDs the C flag with a specified bit in a general register or memory and stores the result in the C flag BIAND B C bit No of lt EAd gt gt C ANDs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag The bit number is specified by 3 bit immediate data BOR B C v bit No of lt EAd gt gt C ORs the C flag with a specified bit in a general register or memory and stores the result in the C flag BIOR B C v bit No of lt EAd gt gt C Note Size operand size B Byte ORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag The bit number is specified by 3 bit immediate data 25 Table 2 8 Bit Manipulation Instruction
14. input is at high impedance The input pull down MOS therefore consumes current when high level is input to the RES pin while the chip is operating During sleep mode the input pull down MOS is in off state Input buffer Internal RES signal Sleep mode gt o 1 Input pull down MOS v Vss Figure 1 4 Block Diagram of RES Pin 3 O 1 IRQ and 2 pins can be used as an I O port and l O 1 IRQ pin can be used as interrupt input pin When these pins are not used they should be left open without connecting anything Input pull up MOS s are connected to these pins See section 7 I O Port for details on the 1 and 2 pins Section 2 CPU 2 1 Overview The H8 3102 has the generic H8 300 CPU an 8 bit central processing unit with a speed oriented architecture featuring sixteen general registers This section describes the CPU features and functions including a concise description of the addressing modes and instruction set For further details on the instructions see the H8 300 Series Programming Manual 2 1 1 Features The main features of the H8 300 CPU are listed below e Two way register configuration Sixteen 8 bit general registers or Eight 16 bit general registers Instruction set with 55 basic instructions including Multiply and divide instructions Powerful bit manipulation instructions EEPROM write instruction Eight addressing mo
15. instructions use register direct addressing The ADD B ADDX SUBX AND OR and XOR instructions can also use immediate addressing Data transfer instructions can use all addressing modes except program counter relative 2 and memory indirect Bit manipulation instructions use register direct register indirect 2 or absolute addressing to specify a byte operand and 3 bit immediate addressing to specify a bit position in that byte The BSET BCLR BNOT and BTST instructions can also use register direct addressing to specify the bit position 15 Table 2 2 Effective Address Calculation Addressing Mode Effective Address Effective No Instruction Format Calculation Address 1 Register direct Rn 3 0 87 43 0 Operands are contained in registers m and n Register indirect Rn 15 0 gt 16 bit register contents 15 76 43 3 Register indirect with displacement d 16 Rn 15 0 4 Register indirect with post increment Rn 15 0 15 16 Bit register contents Register indirect with pre decrement 15 0 16 Bit register contents 1 for a byte operand 2 for a word operand 16 Table 2 2 Effective Address Calculation cont Addressing Mode Effective Address Effective No Instruction Format Calculation Address 5 Absolute address aa 8 15 87 0 15 87 0 o Absolute address aa 16 15 0 abs 6 Immedi
16. odd address in RAM the word at the preceding even address is accessed An even address should normally be specified for word data 4 1 1 Block Diagram Figure 4 1 shows a block diagram of the RAM Internal data bus upper 8 bits Internal data bus lower 8 bits H FDCO 2 On chip RAM 512 bytes H FFBE H FFBF Even address Odd address Figure 4 1 RAM Block Diagram 43 Section 5 ROM 5 1 Overview The H8 3102 has 16 kbytes of on chip user ROM The ROM is connected to the CPU by a 16 bit data bus Both byte and word data are accessed in two states enabling rapid data transfer If word access is performed at an odd address in ROM the word at the preceding even address is accessed An even address should normally be specified for word data 5 1 1 Block Diagram Figure 5 1 shows a block diagram of the ROM Internal data bus upper 8 bits Internal data bus lower 8 bits 16 kbytes Even address Odd address Figure 5 1 ROM Block Diagram 5 1 2 Security ROM data are security protected and cannot be read from outside the chip 44 Section 6 EEPROM 6 1 Overview The H8 3102 has 8 kbytes of electrically writable and erasable EEPROM on chip Both data and program code can be stored in the EEPROM 6 1 1 Features The features of the EEPROM are listed below Capacity 8 kbytes Organization 32 bytes x 256 pages Allocated on the CP
17. operation means all states except for sleep mode 3 Input pull up MOS in I O port is always switched on even during sleep mode To decrease the input pull up MOS current high level should be input to the I O port during sleep mode if the I O port is being used If the I O port is not being used leave the port pin open 4 Current consumption assumes that Vinmin 0 5 V Vitmax 0 5 V and all output lines unloaded 5 the external clock frequency 66 9 2 4 AC Characteristics 3 V Conditions Vec 4 5 to 5 5 V Vss 0 V T4 20 to 75 regular specifications 40 to 85 C wide range specifications unless otherwise specified Parameter Symbol Conditions Min Typ Max Unit Clock cycle time Figure 9 5 0 2 1 0 us Clock high width lcu Figure 9 5 0 4 0 6 toye Clock low width Figure 9 5 0 4 0 6 Clock fall time ter Figure 9 5 10 ns Clock rise time tor Figure 9 5 10 ns port fall time ti Figure 9 6 1 0 us port rise time t Figure 9 6 1 0 us RES pulse width tewL Figure 9 7 20 EEPROM write time tepw 20 15 ms Clock hold time Figure 9 8 20 toye Clock setup time lciks Figure 9 8 20 toye Interrupt pulse width IRQ tiraw Figure 9 8 400 ns Figure 9 5 CLK Input Waveform 3 0 V to 3 3 V port input Vc
18. the value 1 or 2 as immediate data Some bit manipulation instructions contain 3 bit immediate data in the second or fourth byte of the instruction specifying a bit number Program Counter Relative d 8 PC This mode is used in the Bcc and BSR instructions An 8 bit displacement in byte 2 of the instruction code is sign extended to 16 bits and added to the program counter contents to generate a branch destination address The possible branching range is 126 to 128 bytes 63 to 64 words from the current address The displacement should be an even number Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The second byte of the instruction code specifies an 8 bit absolute address The word located at this address contains the branch destination address The upper 8 bits of the absolute address are assumed to be 0 H 00 so the address range is from H 0000 to H OOFF 0 to 255 Note that addresses H 0000 to H 0007 0 to 7 are located in the vector table If an odd address is specified as a branch destination or as the operand address of a MOV W instruction the least significant bit is regarded as 0 causing word access to be performed at the address preceding the specified address See section 2 3 2 Memory Data Formats for further information 14 2 4 2 Effective Address Calculation Table 2 2 shows how effective addresses are calculated in each of the addressing modes Arithmetic and logic
19. x 8 bit organization and is further organized into 32 byte pages There are 256 pages as shown in figure 6 2 Page 255 High address bits A12 to A5 Page 1 Page 0 X Decoder Low address bits Ao Figure 6 2 EEPROM Memory Organization 6 1 4 Register Configuration Writing and erasing of the EEPROM are controlled by the registers listed in table 6 1 Table 6 1 EEPROM Registers Register Abbr R W Initial Value Address EEPROM control register ECR R W H FF H FFF8 EEPROM protection register EPR R W H FF H FFF9 46 6 2 Register Descriptions 6 2 1 EEPROM Control Register ECR The ECR is an 8 bit register that indicates power status and controls the type of write or erase operation performed on the EEPROM Bit 7 6 5 4 3 2 1 0 PWR OC1 OCO Initial value 1 1 1 R W R R W R W Bits 7 6 and 5 Reserved These bits cannot be written and are always read as 1 Although not used at present reserved bits may be used in the future Bit 4 Power PWR This bit is set to 1 when an internal voltage drop is detected The voltage drop detection function operates at all times regardless of the operating state of the EEPROM The PWR bit can be read but not written It is cleared to 0 when bit OC1 or OCO is written Bits 3 and 2 Reserved These bits cannot be written and are always read as 1 Although not used at present reserved bits may
20. 0 1 bit data demcae r e s 4 s a 1 0 don t care _ don t care Word data 3 0 4 bit BCD data don t care 7 4 3 0 4 bit BCD data dont care Notation RnH General register high byte RnL General register low byte MSB Most significant bit LSB Least significant bit Figure 2 3 Register Data Formats 11 2 3 2 Memory Data Formats Figure 2 4 indicates the data formats in memory Word data stored in memory must always begin at an even address In word access the least significant bit of the address is regarded as 0 If an odd address is specified no address error occurs but the access is performed at the preceding even address This rule affects the MOV W instruction and also applies to instruction fetching Data type Address Data format 1 Bit data Address n Byte data Address n Even address Word data Odd address Even address Byte data onstack address Even address Word data on stack Odd address Note Ignored on return Notation CCR Condition code register Figure 2 4 Memory Data Formats When the stack is accessed using R7 as an address register word access should always be performed When the CCR is pushed on the stack two identical copies of the CCR are pushed to make a complete word When they are restored the lower byte is ignored 12 2 4 Addressing Modes 2 4 1 Addressing Modes The H8 300 CPU supports the eight addres
21. 1 OVeErVIe Waist NAR MO SD 35 ciate fo MU 35 2 9 37 28 E 38 281 OVE VIEW 38 282 Transition 1o Sleep ea Be den due 38 2 33 BxibTromi Sleep Mode qe 38 2 9 EHE Cc e obs eed eut e rM 40 29 On Chip Memory RAM ROM 40 2 9 2 Register Field 1 0 40 2 0 3 Non bxistentNddresses tU 41 Sections adt ie tei ia REN 42 Igea RAM m 43 CONGPVCN AG erba e aed fte i d in 43 411 Block Diagram 43 SECOND ROM UR NES 44 Dales mdp E 44 5 51 Block Diagram eee eat 44 PP UNE NES ENS 44 SecHOm o BEPRONL aee RU M E pO MeL 45 6 1 45 Dd cab eise 45 6 1 2 Block 45 6 1 3 Memory 46 6 14 A Register Configuration eese ten osa 46 0 24 abusi ores een dea t d oie 47 621 EEPROM Control Register ECR FH eue 47 6 2 27 EEPROM Protection Register 55 48
22. 2 Program Power down state Interrupt exception execution state Sleep mode processing state SLEEP Instruction Figure 9 4 Interrupt Timing in Sleep Mode 4 5 V to 5 5 V 65 9 2 3 DC Characteristics 3 V Conditions Vec 4 5 to 5 5 V Vss 0 V T4 20 to 75 C regular specifications 40 to 85 C wide range specifications unless otherwise specified Measurement Parameter Symbol Conditions Min Typ Max Unit Input high level RES 08 0 3 V CLK Voc 0 7 Voc 0 3 port Voc 0 7 Voc 0 3 Input low level RES ViL 0 3 E Voc x0 15 V CLK 0 3 Voc x 0 15 port 0 3 Vcc x 0 15 Output high level 7100 pA 1 0 Voc V 20 Voc 0 8 Voc Output low level VoL lo 1 mA 0 0 4 V Input leakage RES Vin 0 5 V 10 current CLK Vin 0 5 to Vcg 0 5 V 10 Input pull down RES lg Vin Voc 150 MOS current 1 normal operation 2 Input pull up port lp Vin 150 MOS Current Normal lcc 5 MHz 7 mA consumption 4 operation Sleep 100 mode Voc 0 5 V to Voc 3 Pin capacitance Die Cp Vin 0 V 15 pF fci 1 MHz COB T 25 TBD Notes 1 Input pull down MOS is cut off during sleep mode 2 Normal
23. Code Map Table B is a map of the operation codes contained in the first byte of the instruction code bits 15 to 8 of the first instruction word Some pairs of instructions have identical first bytes These instructions are differentiated by the first bit of the second byte bit 7 of the first instruction word Instruction when first bit of byte 2 bit 7 of first instruction word is 0 pam Instruction when first bit of byte 2 bit 7 of first instruction word is 1 76 ZL Table B Operation Code Map SLEEP STC LDC ANDC LDC INC ADDS SHLL SHLR SHAR ROTXL ROTL ROTXR ROTR AND NOT NEG DEC SUBS MOV 52 BSR x BIST MOV 1 BXOR dE BLD BIXO BIAND BILD EEPMOV Bit manipulation instruction ADD ADDX CMP SUBX OR m gt Notes 1 The PUSH and POP instructions are identical to MOV instructions 2 The BT BF BHS and BLO instructions are identical to BRA BRN BCC and BCS respectively Appendix C Register Field C 1 Register Field 1 Register Bit Names Address Name Bit6 Bit5 Bit4 Bit2 Module H FFF8 ECR PWR OC1 OCO EEPROM H FFF9 EPR PBM H FFFE DR DR7 DR6
24. OCT gt scree fl wee ee ADDS W 1 Rd Rd16 1 Rd16 Raa Ra PECL CE TE IET ies EIE BENBEEEEEHGOGOROEEH Se SUBXB C gt HE qub Mnemonic Operand size EXIIT DAET H SUBS W 1 Rd SUBS W 2 Rd B Rd 0 Rd8 gt Rd8 O HHH cr PCE ee eee B Rs Rd 16 DAS B Rd decimal adjust Rd8 RdH remainder RdL quotient e Rivassa 21210012 888 4 ES XOR B E 71 Table A Instruction Set cont Addressing mode instruction length Operation ko Mnemonic Operand size aa 8 16 b7 e SHAR B Rd SHLL B Rd p dek k 0 SHLR B Rd ROTXR B Rd E RM 3 Peele upon BSET ASRA eee aol prc e sees A Em BSET e BSET Rn GRd B Rn8 of Rd16 lt 1 72 4 8 Dn Maana Q IDA Af _ 1 A Table A Instruction Set cont Add
25. OMC301495272 Hitachi Single Chip Microcomputer H8 3102 HD6483102 User s Manual Preface The H8 3102 is a single chip microcomputer built around a high speed H8 300 CPU core On chip facilities include 8 kbyte EEPROM 16 kbyte ROM 512 byte RAM and two I O ports On chip EEPROM makes the H8 3102 ideal for applications requiring nonvolatile data storage including smart cards and portable data banks Security functions protect data in the on chip ROM and EEPROM against external reading and writing This manual describes the H8 3102 hardware For details of the instruction set refer to the H8 300 Series Programming Manual Contents Secon lo OVERVIEW NA 1 DINERO Tu M KC 1 WD BlogkDIGStanmi s e eae fe cae 2 1 3 Pin Arrangement and Functions tet ehdedata cughadivavedcndasaesan IR da seas 3 131 3 1 3 2 Pin s iine beata Pos tU Vb prone 5 Seco Laudo tA tcr 6 he ee Cfr 6 PX TEES T o 6 M M TD M 7 2 2 Register DeSCHpLODS OS NOU 8 General DELL OLI I T 8 2 2 2 Control RebISIQES edad AH Un deu dU 8 2 32 25 eade ebat bd
26. P PC lt Rnl6 74 ee Table A Instruction Set cont Mnemonic JSR aa 16 SP 2 SP GSP PC lt aa 16 JSR aa 8 SP 2 SP PC GSP PC lt 8 RTS PC GSP SP42 SP aa 8 16 Addressing mode instruction length Operation Operand size RTE CCR lt SP 2 SP lt SP SP 2 SP SLEEP Transit to sleep mode LDC 8 xx 8 CCR EXER E epe STC CCR Rd CCR gt Rd8 ERST ANDCxe amp CCR B CcRAewsoccR 25 XORC xx 8 CCR 8 gt CCR no cece EEE EEE EEPMOV if R4L40 then Repeat 9 R5 R6 R5 1 gt R5 R6 1 gt R6 R4L 1 Until R4L 0 else next Notes The number of states is the number of states required for execution when the instruction and its operands are located in on chip memory e lt Q9 u Set to 1 when there is a carry or borrow from bit 11 otherwise cleared to 0 If the result is zero the previous value of the flag is retained otherwise the flag is cleared to 0 Set to 1 if decimal adjustment produces a carry otherwise cleared to 0 The maximum write time is 15 ms Set to 1 when the divisor is negative otherwise cleared to 0 Set to 1 when the divisor is zero otherwise cleared to 0 75 Appendix B Operation
27. U address space Written by a special block data transfer instruction instruction rewrites overwrites or erases a page 1 to 32 bytes at a time Protection features prevent accidental writing and erasing Wiite erase protection can be designated by protect bits Low voltage detection Control registers prevent inadvertent writing and erasing On chip voltage pumping circuit Generates the high voltages required for writing and erasing Built in oscillator and timer The write erase sequence is controlled using an independent oscillator EEPROM write erase timing does not depend on the external clock Rewrite time 15 ms max Rewrite cycles 104 page rewrite Data retention time 10 years 6 1 2 Block Diagram Figure 6 1 shows a block diagram of the EEPROM The built in timer generates the write erase sequence The clock pulses for this timer are obtained from an on chip oscillator and are independent of the CPU clock Changing the CPU clock rate external clock does not affect the EEPROM write erase timing 45 The voltage pumping circuit generates the high voltages needed for writing and erasing No external high voltage power supply is required Internal data bus upper 8 bits Internal data bus lower 8 bits EPR ECR EEPROM Voltage pumping circuit Timer Oscillator Figure 6 1 EEPROM Block Diagram 6 1 3 Memory Organization The EEPROM has an 8192
28. ate xx 8 15 87 0 Operand is 1 byte op HIMM immediate data Immediate xx 16 18 0 Operand is 2 byte Oo o p f immediate data IMM 7 PC relative d 8 PC 15 0 meee 5 8 Memory indirect aa 8 15 87 0 15 87 0 Ho 15 0 16 bit memory contents O Notation reg regm regn General registers op Operation field disp Displacement IMM Immediate data abs Absolute address 17 2 5 Instruction Set The H8 3102 can use a total of 55 instructions which are grouped by function in table 2 3 Note The H8 300 CPU has 57 basic instructions but the H8 3102 uses only 55 of them The MOVFPE and MOVTPE instructions are not used Table 2 3 Instruction Set Function Instructions Types Data transfer MOV PUSH 1 1 Arithmetic operations ADD SUB ADDX SUBX INC DEC ADDS SUBS 14 DAA DAS MULXU DIVXU CMP NEG Logic operations AND OR XOR NOT 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR 14 BIOR BXOR BIXOR BLD BILD BST BIST Branch Bcc 2 JMP BSR JSR RTS 5 System control SLEEP LDC STC ANDC ORC XORC NOP RTE 8 EEPROM write EEPMOV 1 Total 55 Notes 1 Rn is identical to MOV W SP Rn PUSH Rn is identical to MOV W Rn 2 Bcc is a conditional branch instruction in which cc represents a condition code 18 Tables 2 4 to 2 11 give a concise summary of the instructions in each f
29. be used in the future Bits 1 and 0 Operation Control 1 and 0 and 0 These bits select the type of EEPROM write erase operation Four operations can be selected by OC1 and OCO as follows BitO Description 0 0 Rewrite 0 1 Overwrite 1 0 Page erase 1 1 Write erase disabled Initial value To prevent unintended writing and erasing the OC1 and OCO bits are both set to 1 automatically at a reset and at the end of a write or erase operation They are also set to 1 automatically whenever an internal voltage drop is detected It is accordingly necessary to clear one or both of these bits before every write or erase operation 47 6 2 2 EEPROM Protection Register EPR Bit 7 6 5 4 3 2 1 0 PBM 1 1 Initial value R W R W The EPR is an 8 bit register that enables the writing of EEPROM write erase protect bits Bit 7 Protect Bit Mode PBM This bit selects the EEPROM data area or protection area The protection area is selected when the PBM bit is cleared to 0 The data area is selected when the PBM bit is set to 1 Writing the PBM bit automatically sets both the OC1 and OCO bits in the ECR to 1 disabling writing or erasing of the EEPROM At the end of a write or erase operation in the protection area the PBM bit itself is automatically set to 1 selecting the data area The protect bits are allocated at the same addresses as the fir
30. c x 0 15 Figure 9 6 I O Port Input Waveform 3 0 V to 3 3 V 67 Voc x 0 15 Voc x 0 15 Voc x 0 15 Figure 9 7 RESET Input Timing 3 0 V to 3 3 V CLK 0 to 5 MHz 0 15 Program execution Power down state Interrupt exception state sleep mode processing state SLEEP Instruction Figure 9 8 Interrupt Timing in Sleep Mode 3 0 V to 3 3 V 68 Appendix A Instruction Set Operation Notation Rd8 16 8 or 16 bit general register destination Rs8 16 8 or 16 bit general register source Rn8 16 8 or 16 bit general register CCR Condition code register N N negative flag of CCR Z Z zero flag of CCR V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer 3 8 16 3 8 or 16 bit immediate data d 8 16 8 or 16 bit displacement aa 8 16 8 or 16 bit absolute address Addition Subtraction x Multiplication Division A AND logical OR logical e Exclusive OR logical gt Move m Not Condit
31. control bits in the EPR and ECR then executing the EEPMOV instruction RAM R5 5 R4L 1 Transfer EEPROM EN R6 R4L 1 Figure 6 4 Block Transfer to EEPROM Figure 6 5 indicates the contents of the three parameter registers used by the EEPMOV instruction Table 6 2 describes the parameters and their valid ranges of values 49 7 0 Byte counter R4L 15 0 RAM address register R5 15 0 EEPROM address register R6 Figure 6 5 EEPMOV Parameters Table 6 2 EEPMOV Parameters and Their Valid Ranges Register Name Description Valid Range Final Value R4L Byte counter Byte length of block to 1 to 32 H 00 be written in EEPROM H 01 to H 20 R5 RAM address Starting address of H FDCO to R5 R4L register source block in RAM H FFBF R6 EEPROM address Starting address of desti H 6000 to R6 R4L register nation block in EEPROM H 7FFF Note When an EEPROM write operation ends at the last address on a page the EEPROM address register R6 reverts to the first address on that page Example If R6 6000 and R4L 20 the final value of R6 is H 6000 If R6 H 603F and R4L H O1 the final value of R6 is H 6020 If the parameters are set to values outside the valid ranges in table 6 2 when the EEPMOV instruction is executed or if the byte counter R4L and EEPROM address register R6 are set so as to cross a page boundary the write or erase operation may not be performed as intended
32. ction specifies a 16 bit general register containing the address of the operand After the operand is accessed the register is incremented by for MOV B or 2 for MOV W For MOV W the original contents of the 16 bit general register must be even 13 e Register indirect with pre decrement Rn The Rn mode is used with MOV instructions that store register contents to memory The register field of the instruction specifies a 16 bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory The register retains the decremented value The size of the decrement is 1 for MOV B or 2 for MOV W For MOV W the original contents of the 16 bit general register must be even Absolute Address aa 8 or aa 16 The instruction specifies the absolute address of the operand in memory The absolute address may be 8 bits long aa 8 or 16 bits long aa 16 The MOV B and bit manipulation instructions can use 8 61 absolute addresses The MOV B MOV W JMP and JSR instructions can use 16 bit absolute addresses For an 8 bit absolute address the upper 8 bits are assumed to be 1 H FF The address range is H FF00 to H FFFF 65280 to 65535 Immediate xx 8 or xx 16 The instruction contains an 8 bit operand xx 8 in its second byte or a 16 bit operand xx 16 in its third and fourth bytes Only MOV W instructions can contain 16 bit immediate values The ADDS and SUBS instructions implicitly contain
33. d bits by logic operations The N Z V and C flags are used as branching conditions for conditional branching Bcc instructions Refer to the H8 300 Series Programming Manual for the action of each instruction on the flag bits 2 2 3 Initial Register Values When the CPU is reset the program counter PC is loaded from the vector table and the I bit in the CCR is set to 1 The other CCR bits and the general registers are not initialized In particular the stack pointer R7 is not initialized To prevent program crashes the stack pointer should be initialized by software by the first instruction executed after a reset 2 3 Data Formats The H8 300 CPU can process 1 bit data 4 bit BCD data 8 bit byte data and 16 bit word data Bit manipulation instructions operate on 1 bit data specified as bit n n 0 1 2 7 byte operand All arithmetic instructions except ADDS and SUBS can operate on byte data The MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits x 8 bits and DIVXU 16 bits 8 bits instructions operate on word data The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form Each nibble of the byte is treated as a decimal digit 10 2 3 1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2 3 Data type Register no Data format 7 0 1 bit data RH 7 6 5 4 3 2 110 dontcare 7
34. d data back to the specified address 26 Figure 2 7 shows the object code formats of the bit manipulation instructions Notation p Operation field rm rn Register field Absolute address Immediate data 0000 BSET BCLR BNOT BTST Operand register direct Rn Bit No immediate xx 3 Operand register direct Rn Bit No register direct Rm Operand register indirect Rn Bit No immediate xx 3 Operand register indirect Rin Bit No register direct Rm Operand absolute 2aa 8 Bit No immediate xx 3 Operand absolute 2aa 8 Bit No register direct Rm BAND BOR BXOR BLD BST Operand register direct Rn Bit No immediate xx 3 Operand register indirect Rin Bit No immediate xx 3 Operand absolute 2aa 8 Bit No immediate xx 3 Figure 2 7 Bit Manipulation Instruction Object Code Formats 27 BIAND BIOR BIXOR BILD E Operand register direct Rn Bit No immediate xx 3 Operand register indirect Rn Bit No immediate 3 Operand absolute aa 8 Bit No immediate xx 3 Notation Operation field Register field Absolute address Immediate data Figure 2 7 Bit Manipulation Instruction Object Code Formats cont 28 2 5 6 Branching Instructions Table 2 9 describes the branching instructions Table 2 9 Branching Instructions Instruction Size Function Bcc Branches to a specified address if condition cc is true Th
35. d read by software for its own purposes using the LDC STC ANDC ORC and XORC instructions Bit 5 Half Carry Flag When the ADD B ADDX B SUB B SUBX B or NEG B instruction is executed this flag is set to 1 if there is a carry or borrow at bit 3 and is cleared to 0 otherwise The H flag is used implicitly by the DAA and DAS instructions When the ADD W SUB W or CMP W instruction is executed the flag is set to if there is a carry or borrow at bit 11 and is cleared to 0 otherwise Bit 4 User Bit U Can be written and read by software for its own purposes using the LDC STC ANDC ORC and XORC instructions Bit 3 Negative Flag N Indicates the most significant bit sign bit of data Bit 2 Zero Flag Z Set to 1 to indicate zero data and cleared to 0 to indicate non zero data Bit 1 Overflow Flag V Set to 1 when an arithmetic overflow occurs and cleared to 0 at other times Bit 0 Carry Flag C Set to 1 when a carry occurs and cleared to 0 otherwise Used by e Add instructions to indicate a carry e Subtract instructions to indicate a borrow Shift and rotate instructions to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions Some instructions leave some or all of the flag bits unchanged The LDC STC ANDC ORC and XORC instructions enable the CPU to load and store the CCR and to set or clear selecte
36. d size B Byte 2 5 4 Shift Operations Table 2 7 describes the shift instructions Table 2 7 Shift Instructions Note Size operand size B Byte Instruction Size Function SHAL B Rd shift Rd SHAR Performs an arithmetic shift operation on general register contents SHLL B Rd shift Rd SHLR Performs a logical shift operation on general register contents ROTL B Rd rotate Rd ROTR Rotates general register contents ROTXL B Rd rotate through carry Rd ROTXR Rotates general register contents through the C carry bit 23 Figure 2 6 shows the object code formats of the arithmetic logic and shift instructions Notation p Operation field rm rn Register field MM Immediate data ADD SUB CMP ADDX SUB Rm ADDS SUBS INC DEC DAA DAS NEG NOT MULXU DIVXU ADD ADDX SUBX CMP xx 8 AND OR XORRm AND OR 8 SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Figure 2 6 Arithmetic Logic and Shift Instruction Object Code Formats 24 2 5 5 Bit Manipulations Table 2 8 describes the bit manipulation instructions Table 2 8 Bit Manipulation Instructions Instruction Size Function BSET B 1 bit No of lt EAd gt Sets a specified bit in a general register or memory to 1 The bit number is specified by 3 bit immediate data or the lower three bits of a general register BCLR B 0 lt bit No gt of lt EAd gt Clears
37. de 40 2 9 3 Non Existent Addresses When read non existent addresses always return the data H FF byte access or H FFFF word access Figure 2 18 shows the access timing to on chip memory and the register field Section 3 Memory Map indicates the types of access possible at each address Bus cycle T4 State ai To State Internal address bus Internal read signal Internal data bus Read data read cycle Internal write signal Internal data bus Write data write cycle Figure 2 18 Access Timing to On Chip Memory and Register Field 41 Section 3 Memory Map Figure 3 1 shows a memory map of the H8 3102 Address Address Exception vectors Reset H 0000 H 0001 H 0002 H 0003 ROM H 0004 H 0005 16 kbytes 0006 0007 Switched by EPR EEPROM EEPROM 8 kbytes PBM bit protection Data area area Read only H FFBF 512 bytes EEPROM control registers port control registers Access possible Shaded areas are unavailable to the user X Access impossible User programs must not access these areas User programs must not use 4 bytes Figure 3 1 Memory Map 42 Section 4 RAM 4 1 Overview The H8 3102 has 512 bytes of on chip static RAM The RAM is connected to the CPU by a 16 bit data bus Both byte data and word data are accessed in two states enabling rapid data transfer If word access is performed at an
38. des Register direct Rn Register indirect Rn Register indirect with displacement d 16 Rn Register indirect with post increment or pre decrement Rn or Rn Absolute address aa 8 or aa 16 Immediate 8 or 16 Program counter relative d 8 PC Memory indirect aa 8 e 64 kbyte address space Note The H8 300 CPU has 57 basic instructions but the H8 3102 uses only 55 of them The and MOVTPE instructions are not used e High speed operation All frequently used instructions are executed in two to four states Maximum clock rate is 5 MHz with 10 MHz external clock input at 5 V 8 or 16 bit register register add or subtract 0 4 us 8 x 8 bit multiply 2 8 16 8 bit divide 2 8 US Power down mode SLEEP instruction 2 1 2 CPU Registers Figure 2 1 shows the register structure of the H8 300 CPU There are two groups of registers the general registers and control registers General registers Rn 7 Control registers CR 15 0 7 6 5 4 832 Z V C Notation SP Stack Pointer PC Program Counter Condition Code Register Interrupt mask bit User bit Half carry flag Negative flag Zero flag Overflow flag Carry flag Figure 2 1 CPU Registers 7 2 2 Register Descriptions 2 2 1 General Registers All the general registers can be used as both data registers and address registers When
39. e Operation 6 4 4 Overwrite When the EEPMOV instruction is executed with 0 and 1 the transferred data overwritten on the old data After an overwrite operation the EEPROM contains the logical AND of the old data and the overwritten data Old data 1 001 01 1 0 1 11001 00 Overwriten data 1 0 0 O 1 1 1 1 10100111 Resulting data 1 00001 10 0 1 Figure 6 8 Results of Overwrite Operations examples 6 5 Write Erase Protection 6 5 1 Protect Bits EEPROM data can be protected from accidental writing and erasing Each 32 byte page can be protected individually Each page has its own protect bits Write erase protection is conferred by writing a protection code H 78 in the protect bits Once a page is protected the protection cannot be removed The protect bits for a page have the same address as the first data byte in the page The PBM bit in the EPR selects either the protection or data area The protection area is selected when PBM 0 the data area is selected when PBM 1 Figure 6 9 shows how the protect bits are allocated to pages Figure 6 10 shows an example of write erase protection 52 32 Bytes Page 0 Protect 0 Page 255 Protect 255 PBM 1 0 EEPROM EEPROM Data area Protection area Figure 6 9 Allocation of Protect Bits Data area Protection area Page 0 Page 1 Page 2 Can be written only once Page 255
40. e branching conditions are listed below Mnemonic Description Condition BRA BT Always True Always BRN BF Never False Never BHI High CvZ 0 BLS Low or Same CvZ 1 BCC BHS Carry Clear 0 High or Same BCS BLO Carry Set Low C 1 BNE Not Equal Z 0 BEQ Equal Z 1 BVC Overflow Clear V 0 BVS Overflow Set 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or Equal N V 0 BLT Less Than N V 1 BGT Greater Than Zv N V 0 BLE Less or Equal Zv N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified displacement from the current address JSR Branches to a subroutine at a specified address RTS Returns from a subroutine 29 Figure 2 8 shows the object code formats of the branching instructions Bcc JMP Rm JMP aa 16 JMP 8 BSR JSR QRm JSR aa 16 JSR 8 RTS Notation Operation field Condition field Register field Displacement Absolute address Figure 2 8 Branching Instruction Object Code Formats 30 2 5 7 System Control Instructions Table 2 10 describes the system control instructions Table 2 10 System Control Instructions Instruction Size Function RTE Returns from an exception handling routine SLEEP Causes a transition to the power down state LDC B Rs gt CCR CCR Moves immediate data or general register con
41. em control logic ROM 16 kbytes Clock EEPROM 8 kbytes divider Figure 1 1 Block Diagram 1 3 Pin Arrangement and Functions 1 3 1 Pin Arrangement Figure 1 2 shows the standard COB bonding pad pattern of the H8 3102 chip Unit mm Figure 1 2 Standard COB Pattern Electrode Surface Vss l O 1 IRQ User pad Figure 1 3 Bonding Pad Arrangement 1 3 2 Pin Functions Table 1 2 lists the functions of the H8 3102 pins Table 1 2 Pin Functions Type Symbol Name and Description Power supply Voc Power supply 4 5 V to 5 5 V or 2 7 V to 3 3 Ground 0 V Clock Clock external clock input Reset RES Reset low input resets the chip Ports l O 1 IRQ 3 port 1 One bit data input output port Software can select input or output Interrupt In sleep mode this port receives interrupt input 2 3 port 2 One bit data input output port Software can select input or output Notes 1 Vec Vss and CLK have two bonding pads apiece When the H8 3102 is mounted as a bare chip either or both pads may be used When only one pad is used the other unused pad should be left open without connecting anything When both CLK pins are used the same clock should be input to both pins 2 An input pull down MOS is connected to the RES pin as shown in figure 1 3 to avoid incorrect operation when RES pin
42. essing state The program counter and condition code register are saved on the stack as shown in figure 2 14 The program counter address saved on the stack is the address of the first instruction that will be executed after the return from the interrupt handling routine The I bit in the condition code register is set to 1 The address of the interrupt handling routine is read from the vector table entry corresponding to the interrupt vector and loaded into the program counter and execution of the interrupt handling routine begins Figure 2 18 shows the timing of interrupt sequence SP 4 SP R7 SP 3 SP 1 SP 2 SP 2 SP 1 SP 3 SP R7 gt 5 44 Stack area address Before After Save on stack Notation PCy Upper 8 bits of program counter PC PCL Lower 8 bits of program counter PC CCR Condition code register SP Stack pointer Notes 1 The program counter indicates the address of the first instruction that will be executed after the return 2 Registers must be saved and restored by word access starting at an even address Ignored on return Figure 2 14 Stack before and after Interrupt Exception Handling Sequence 37 2 8 Power Down State 2 8 1 Overview The H8 3102 has a sleep mode a power down state in which CPU functions are halted to conserve power Table 2 14 summarizes the conditions for transition to the sleep mode the state of the CPU and on chip sup
43. g Address Read Data Figure 7 3 I O Line Input Timing 61 Section 8 Clock Pulse Generator 8 1 Overview The H8 3102 includes an on chip divider circuit that generates the system clock 9 from an external clock input The external clock is input at the CLK pin The system clock frequency is one half the external clock frequency Figure 8 2 Relationship of System Clock and External Clock Input 62 Section 9 Electrical Characteristics 9 1 Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply voltage Voc 0 3 to 7 0 V Input voltage Vin 0 3 to 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 Storage temperature 55 to 125 C Note Permanent LSI damage may occur if maximum ratings are exceeded Normal operation should be under recommended operating conditions If these conditions are exceeded it could affect reliability of LSI Without valid data in EEPROM before programming EEPROM 9 2 Electrical Characteristics 9 2 1 DC Characteristics 5 V Conditions Voc 4 5 to 5 5 V Vss 0 V T4 20 to 75 C regular specifications 40 to 85 C wide range specifications unless otherwise specified Measurement Parameter Symbol Conditions Min Typ Max Unit Input high level RES Vin 4 0 Voc O03 V CLK 2 4 Voc
44. general register by referring to the CCR MULXU B Rd x Rs gt Rd Performs 8 bit x 8 bit unsigned multiplication on data in two general registers providing a 16 bit result DIVXU B Rd Rs Performs 16 bit 8 bit unsigned division on data in two general registers providing an 8 bit quotient and 8 bit remainder CMP B W Rd Rs IMM Compares data in a general register with data in another general register or with immediate data and sets the CCR according to the result Word data can be compared only between two general registers NEG B 0 Rd gt Rd Note Size operand size B Byte W Word Obtains the two s complement arithmetic complement of data in a general register 22 2 5 3 Logic Operations Table 2 6 describes the instructions that perform logic operations Table 2 6 Logic Operation Instructions Instruction Size Function AND B Rs gt Rd Rda IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rs Rd Rdv IMM gt Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs gt Rd Rd 6 IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B Rd Obtains the one s complement logical complement of general register contents Note Size operan
45. ion Code Notation Changed according to the execution result Undetermined value 0 Always cleared to 0 Previous value remains unchanged 69 Table A Instruction Set Mnemonic Operand size MOV B Rs 8 MOV B Rs d 16 Rd MOV B Rs Rd MOV B Rs Rd MOV B Rs aa 16 d MOV W xx 16 Rd MOV W Rs Rd MOV W Rs Rd MOV W d 16 Rs Rd 16 Rd MOV W Rs Rd MOV W aa 16 Rd MOV W Rs G Rd MOV W Rs d 16 Rd MOV W Rs Rd MOV W Rs aa 16 POP Rd PUSH Rs B B 5 Addressing mode instruction length Operation 8 Rd8 Rs8 Rd8 Rs16 Rd8 Q d 16 Rs16 Rs16 gt Rd8 Rs16 1 Rs16 aa 8 gt Rd8 aa 16 Rd8 s8 16 38 gt d 16 Rd16 Rd16 1 gt Rd16 Rs8 gt GRdl6 Rs8 8 Rs8 gt 16 xx 16 Rdl6 Rs16 Rd16 Rs16 gt Rd16 d 16 Rs16 gt 16 Rs16 gt Rdl6 Rs1642 2516 aa 16 16 Rs16 gt 16 Rs16 gt d 16 Rd16 16 2 Rdl6 Rs16 gt 16 Rs16 gt 16 SP 16 SP 2 SP SP 2 SP Rs16 gt SP R R pense ps team PS eas NES 70 Table A Instruction Set cont Addressing mode instruction length Operation Condition code 8 n e x Mul INED 3 S
46. ip RAM are retained as long as the specified voltage is supplied The I O port DR and DDR values are also retained Sleep mode is exited by low input at the RES pin or I O 1 IRQ pin 34 2 7 Exception Processing 2 7 1 Overview In the H8 3102 exception processing is performed in response to a reset or interrupt Table 2 12 summarizes the exception processing priority and timing Table 2 13 describes the exception vector table Table 2 12 Exception Processing Priority and Timing Priority Cause Detection Timing Start of Exception Processing Sequence High Reset Synchronized with Instruction execution stops and reset clock processing starts immediately Interrupt Falling edge is Interrupt exception processing starts Low IRQ detected immediately Table 2 13 Exception Vector Table Vector Address Description Vector Number PC high PC low Reset 0 H 0000 H 0001 Reserved for system use 1 H 0002 H 0003 Reserved for system use 2 H 0004 H 0005 Interrupt IRQ 3 H 0006 H 0007 Note Software should not access these addresses 2 7 2 Reset The H8 3102 begins reset exception processing when the RES input changes from low to high At power up RES should be held low for at least 20 external clock cycles after the input clock signal CLK stabilizes Similarly when the chip is reset during operation RES should be held low for at least 20 external clock cycles RES should also be low whenever power is switched on or off
47. not be written and are always read as 1 Although not used at present reserved bits may be used in the future The DR and DDR contents are held in sleep mode as long as the necessary voltage is supplied but the I O ports are placed in the output disabled state with input pull up MOS connected regardless of the value in the I O port direction register DDR 59 7 3 Pin Functions The I O 1 IRQ pin has a dual function as an external interrupt pin This pin functions as an external interrupt input pin during sleep mode The I O 1 IRQ becomes interrupt input pin during sleep mode regardless of the DDR value and the falling edge of the I O 1 IRQ pin becomes an external interrupt request signal to the CPU Input pull up MOS is connected to the I O 1 IRQ pin to avoid an erroneous interrupt request when the input is at high impedance Input pull up MOS is similarly connected to the I O 2 pin The input pull up MOS s are always switched on even during sleep mode To decrease the input pull up MOS current high level should be input to the I O 1 IRQ and I O 2 pins during sleep mode If the pin is not being used either as an I O port or as an external interrupt input it should be left open in this case the pin is pulled high by the input pull up MOS 60 7 4 Pin Timing Figure 7 2 shows the output timing on the I O lines Figure 7 3 shows the input timing Address Write Data Figure 7 2 I O Line Output Timin
48. nterrupt in sleep mode 38 DDR7 0 Sleep mode O 1 IRQ Low Execute SLEEP instruction Execution of interrupt handling routine Sleep mode RTE instruction Figure 2 15 Transition Sequence Figure 2 16 Recovery Sequence from to Sleep Mode example Sleep Mode example Note The RES I O 1 IRQ and I O 2 lines must be held high during sleep mode 2 Exit by reset If the RES input goes low during sleep mode the external clock is supplied to the CPU and on chip supporting modules Next when the RES input goes high the CPU begins reset exception processing The RES input should be held low for at least 20 stable external clock cycles 39 CCR I bit l O 1 IRQ Operating Power down Operating CCR bit cleared to 0 I Sleep mode Interrupt exception processing SLEEP instruction Figure 2 17 Interrupt Timing in Sleep Mode 2 9 Basic Timing The CPU operates on the system clock 9 The interval from one rising edge of the system clock to the next is called a state The memory access cycle or bus cycle consists of two states 2 9 1 On Chip Memory RAM ROM EEPROM The data bus is 16 bits wide Both byte and word access are supported 2 9 2 Register Field I O EEPROM The upper 8 bits of the internal data bus are used to access these registers The data bus is accordingly 8 bits wi
49. porting modules in sleep mode and the conditions for exit from sleep mode Table 2 14 Power Down State States Entering CPU DR Exiting Mode Procedure Clock CPU Reg s RAM DDR Ports EPR Methods Sleep Execute Stop Stop Held Held Held High level Initialized RES mode SLEEP output set e 1 instruction by pull up ARQ MOS data output inhibited 2 8 2 Transition to Sleep Mode Sleep mode is entered by executing the SLEEP instruction In the sleep mode the CPU clock and on chip supporting functions halt so power consumption is reduced to an extremely low level As long as the necessary voltage is supplied however the contents of CPU registers and RAM and the I O port registers DR and DDR are held I O 1 IRQ becomes interrupt input line The and I O 2 lines should be kept high during sleep mode Figure 2 15 shows the transition sequence to sleep mode 2 8 3 Exit from Sleep Mode Exit from the sleep mode takes place by input to the I O 1 IRQ or RES pin Exit by interrupt In sleep mode the I O 1 IRQ pin can receive interrupt signals When high to low transition occurs at input the external clock is supplied to the CPU and on chip supporting modules the sleep mode ends and interrupt exception processing starts The external clock must be stable when the interrupt signal goes low Figure 2 16 shows the transition sequence from the sleep mode to interrupt handling Figure 2 17 shows the timing of an i
50. ressing mode instruction length Operation Rn8 of Rd8 lt Rn8 of Rd8 Rn8 of Rd16 lt Rn8 of GRdl6 Mnemonic Operand size 3 of Rd16 gt C BILD xx 3 Rd BILD xx 3 aa 8 xx 3 of aa 8 gt C C xx 3 of Rd8 BST xx 3 Rd BST xx 3 Rd gt xx 3 of Rd16 BST xx 3 aa 8 2 xx 3 of aa 8 BIST xx 3 Rd 5 3 of Rd8 C 5 xx 3 of Rd16 BIST 3 9 Rd BIST xx 3 aa 8 xx 3 of aa 8 CA fx 3 of GRdl6 gt BIAND xx 3 aa 8 3 of aa 8 gt BILD xx 3 Rd xx 3 of Rd8 gt psa cess pep vs pens popa poeseos we 73 Table A Instruction Set cont Addressing mode instruction length Operation Mnemonic Operand size peerless Ie momen mames ons 111 Deer ree ttt HERRERA BRA d 8 BRAd 8 BTd 8 8 PCePCH8 lt 4 8 BEES I LI d 0 true then use cesse mu E wem id ma E fares Dus se 000 LI TOR JMP IMP aa 16 16 Pceam6 aa 16 eee i BSR 4 8 SP 2 gt SP PC gt SP JSR GRn SP 2 S
51. ruction set e Instruction length 2 or 4 bytes e A Register register arithmetic and logic operations e MOV instruction for data transfer between registers and memory Instruction set features Multiply instruction 8 bits x 8 bits Divide instruction 16 bits 8 bits Bit accumulator instructions e Register indirect specification of bit positions On chip EEPROM memory 8kbytes Written by EEPMOV instruction Page 32 bytes write and erase Protected against accidental writing and erasing On chip voltage pumping circuit ROM 16 kbytes RAM 512 bytes ports Two general purpose input output ports I O 1 IRQ also used for interrupts Table 1 1 Features cont Item Specification Interrupts One external interrupt lines 1 Used for interrupt input in sleep mode Power Single voltage power supply 45Vto5 5V or e 2 7Vt03 3V Clock External clock input frequency e 1 MHz to 10 MHz 4 5 V to 5 5 V range e fei 1 MHz to 5 MHz Voc 2 7 V to 3 3 V Internal clock input 500 kHz to 5 MHz Vcc 4 5 V to 5 5 V 500 kHz to 2 5 MHz Vcc 2 7 V to 3 3 V Power down Sleep mode state Others e Input clock frequency monitor 1 2 Block Diagram Figure 1 1 shows an internal block diagram of the H8 3102 l O 1 IRQ Voc gt 2 2 Data bus Vss gt Address bus RES gt Syst
52. s cont Instruction Size Function BXOR B C lt bit No gt of lt EAd gt gt Exclusive ORs the C flag with a specified bit in a general register or memory and stores the result in the C flag BIXOR B 4 bit No of lt EAd gt gt C Exclusive ORs the C flag with the inverse of a specified bit in a general register or memory and stores the result in the C flag The bit number is specified by 3 bit immediate data BLD B lt bit No gt of lt EAd gt gt C Transfers a specified bit in a general register or memory to the C flag BILD B bit No of lt EAd gt gt Transfers the inverse of a specified bit in a general register or memory to the C flag The bit number is specified by 3 bit immediate data BST B C bit No of lt EAd gt Transfers the C flag value to a specified bit in a general register or memory BIST B C 5 bit No of lt EAd gt Transfers the inverse of the C flag value to a specified bit in a general register or memory The bit number is specified by 3 bit immediate data Note Size operand size B Byte Note on Bit Manipulation Instructions BSET BCLR BNOT BST and BIST are read modify write instructions They read a byte of data modify one bit in the byte then write the modified byte back to the same address Step Operation 1 Read Read data 1 byte at a specified address 2 Modify Modify one specified bit in the read data 3 Write Write the modifie
53. s read The value of DR7 after a reset is undetermined Bit 6 Data Register Bit 6 DR6 Latches the I O ports output data When DDR6 1 selecting output the value of the DR6 bit is output on the 2 line When the DR is read if DDR6 0 input the logic level of the I O 2 line is read directly If DDR6 1 output the value in the DR6 latch is read The value of DR6 after a reset is undetermined Bits 5 to O Reserved These bits cannot be written and are always read as 1 Although not used at present reserved bits may be used in the future 58 7 2 2 Data Direction Register DDR Bit 7 6 5 4 3 2 1 0 DDR7 DDR6 A 2 Initial value 0 0 R W W WwW EM The data direction register specifies the direction input or output of the I O port Bit 7 Data Direction Bit 7 DDR7 Specifies the direction of the I O 1 line 1 selects output 0 selects input This bit can be written but not read If read it always returns the value 1 regardless of its true value A reset clears this bit to 0 making an input port Bit 6 Data Direction Bit 6 DDR6 Specifies the direction of the 2 line 1 selects output 0 selects input This bit can be written but not read If read it always returns the value 1 regardless of its true value A reset clears this bit to 0 making 2 an input port Bits 5 to 0 Reserved These bits can
54. shows an I O port block diagram The DR and DDR can be accessed only by byte access Internal data bus Sleep mode Input pull up MOS Q CK D always switched on Voc DDR write 087 Vss tput buff DR write gt Input buffer Sleep mode External interrupt Falling edge request to CPU detector Sleep mode Input pull up MOS Q D always switched on CK V cc DDR write p DR6 Vss Output buffer gt DR read Input buffer Figure 7 1 I O Port Block Diagram 57 7 1 2 Register Configuration Table 7 1 lists the I O port registers Table 7 1 I O Port Registers Name Abbr R W Address Data register DR R W H FFFE Data direction register DDR W H FFFF 7 2 Register Descriptions 7 2 1 Data Register DR Bit 7 6 5 4 3 2 1 0 DR7 DR6 Initial value E R W R W R W mE TR X 2 4 The data register latches the output data Bit 7 Data Register Bit 7 DR7 Latches the I O ports output data When DDR7 1 selecting output the value of the bit is output on the I O 1 line When the DR is read if DDR7 0 input the logic level of the I O 1 line is read directly If DDR7 1 output the value in the DR7 latch i
55. sing modes listed in table 2 1 Each instruction uses a subset of these addressing modes Table 2 1 Addressing Modes No Addressing Mode Symbol Register direct Rn Register indirect Rn Register indirect with displacement d 16 Rn Register indirect with post increment Rn Register indirect with pre decrement Rn Absolute address aa 8 or aa 16 Immediate xx 8 or xx 16 Program counter relative d 8 PC Memory indirect aa 8 Register Direct Rn The register field of the instruction specifies an 8 or 16 bit general register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits x 8 bits and DIVXU 16 bits 8 bits instructions have 16 bit operands Register Indirect Rn The register field of the instruction specifies a 16 bit general register containing the address of the operand Register Indirect with Displacement 4 16 Rn The instruction has a second word bytes 3 and 4 containing a displacement which is added to the contents of the specified general register to obtain the operand address This mode is used only in MOV instructions For the MOV W instruction the resulting address must be even Register Indirect with Post Increment or Pre Decrement Rn or Rn Register indirect with post increment Rn The Rn mode is used with MOV instructions that load registers from memory The register field of the instru
56. st bytes of pages 0 to 255 of the EEPROM data area Each page of the EEPROM can be protected individually See section 6 5 Write Erase Protection for further information on the protection area and data area Bit 7 PBM Description 0 Protection area is selected 1 Data area is selected Initial value Bits 6 to 0 Reserved These bits cannot be written and are always read as 1 Although not used at present reserved bits may be used in the future ECR and EPR are initialized by the SLEEP instruction After exiting sleep mode software must set up these registers again before writing to EEPROM 6 3 EEPROM Read Operation The EEPROM is read directly by the CPU using the same instructions as for reading ROM or RAM Figure 6 3 shows the read timing The read data are sent to the CPU via a 16 bit bus If word access is performed at an odd address the word at the preceding even address is read 48 bus Internal read signal 4 Fetch timing Figure 6 3 EEPROM Read Timing 6 4 EEPROM Write and Erase Operations 6 4 1 Write Erase Sequence The EEPROM is written or erased using the EEPMOV block data transfer instruction The instruction transfers a block of data stored on RAM to a single page in EEPROM The data transfer from RAM to EEPROM is controlled by parameters set in CPU registers RAL R5 and R6 as shown in figure 6 4 The transfer is made by first setting parameters in registers RAL R5 and R6 and
57. tents to the condition code register STC B CCR gt Rd Copies the condition code register to a specified general register ANDC B CCR IMM gt CCR Logically ANDs the condition code register with immediate data ORC B CCR v IMM gt CCR Logically ORs the condition code register with immediate data XORC B CCR 6 IMM gt CCR Logically exclusive ORs the condition code register with immediate data NOP PC 2 Only increments the program counter Note Size operand size B Byte Figure 2 9 shows the object code formats of the system control instructions RTE SLEEP NOP LDC STC Rn ANDC ORC XORC LDC xx 8 Notation Operation field Register field Immediate data Figure 2 9 System Control Instruction Object Code Formats 31 2 5 8 EEPROM Write Instruction Table 2 11 describes the EEPROM write instruction Table 2 11 EEPROM Write Instruction Instruction Size Function EEPMOV If RAL 0 then repeat R5 R6 41 1 gt R4L until R4L 0 else next Transfers a data block to EEPROM according to parameters set in general registers RAL R5 and R6 R4L size of block bytes R5 starting source address R6 starting destination address Execution of the next instruction begins as soon as the EEPROM write operation is completed The transfer cannot cross an EEPROM page boundary Figure 2 10 shows the object code format of the EEPROM write instruction 15 8 7 0 Notation op
58. the system clock 9 and processed to eliminate short pulses The reset signal input to the EEPROM however is not synchronized with the system clock and is not processed to eliminate short pulses This feature enables the EEPROM to be deactivated by the reset signal alone even when external clock input is stopped to prevent EEPROM data from being destroyed due to chip malfunctions As a result if a reset signal shorter than the minimum pulse width is input only the EEPROM is reset aborting any write or erase operation in progress and initializing the control registers The CPU and other circuits may or may not continue to operate correctly 54 2 EEPMOV Execution with Invalid Register Settings If registers RAL and R6 are set so as to cross a page boundary the EEPROM write or erase operation is performed within the page including the initial address in R6 Example R4L H20 R5 H FF00 R6 H 6010 Then the block data transfer is performed as follows RAM addresses H FF00 to H FFOF EEPROM addresses H 6010 to H 601F RAM addresses H FF10 to H FF1F gt gt EEPROM addresses 6000 to H 600F 55 Section 7 I O Port 7 1 Overview The H8 3102 has a two bit wide I O port Software can select whether to use each I O bit for data input or output The I O port has a data register DR for latching output data and a data direction register DDR for specifying input or output 56 7 1 1 Block Diagram Figure 7 1
59. unctional group The following notation is used in these tables to describe the operations performed Operation Notation Rd General register destination Hs General register source Hn General register EAd Destination operand EAs Source operand CCR Condition code register N N negative bit of CCR Z Z zero bit of CCR V V overflow bit of CCR C C carry bit of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division A AND logical OR logical Exclusive OR logical gt Move a Not 3 8 16 3 8 or 16 bit length 19 2 5 1 Data Transfer Instructions Table 2 4 describes the data transfer instructions Table 2 4 Data Transfer Instructions Instruction Size Function MOV B W EAs gt Rd Rs Moves data between two general registers or between a general register and memory or moves immediate data to a general register Rn Rn d 16 Rn aa 16 xx 16 Rn and Rn addressing modes are available for byte or word data The xx 8 aa 8 addressing mode are available for byte data only Specify word size operands for 7 and R7 POP W SP gt Pops a 16 bit general register from the stack Identical to MOV W SP Rn PUSH W Rn SP Pushes a 16 bit general register onto the stack Identical to MOV W Rn SP Note
60. used as data registers they can be accessed as 16 bit registers RO to R7 or the high bytes ROH to R7H and low bytes ROL to R7L can be accessed separately as 8 bit registers When used as address registers the general registers are accessed as 16 bit registers RO to R7 Registers RAL R5 and R6 have special functions when the EEPMOV EEPROM write instruction 1s executed R7 also functions as the stack pointer used implicitly by hardware in processing exceptions and subroutine calls In assembly language coding R7 can also be denoted by the symbol SP As indicated in figure 2 2 SP R7 points to the top of the stack Free area Stack area Figure 2 2 Stack Pointer 2 2 2 Control Registers The CPU control registers include a 16 bit program counter PC and an 8 bit condition code register CCR 1 Program Counter PC This 16 bit register indicates the address of the next instruction the CPU will execute All instructions are fetched 16 bits 1 word at a time so the least significant bit of the PC is ignored always regarded as 0 2 Condition Code Register CCR This 8 bit register contains internal CPU status information including the interrupt mask bit 1 and half carry negative N zero Z overflow V and carry C flags Bit 7 Interrupt Mask Bit 1 Masks interrupts when set to 1 This bit is set to 1 at the beginning of exception processing Bit 6 User Bit U Can be written an
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