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Z-100 NET100 Ethernet Interface card

1. 443 837 74 5373 0104 0122 3 state 8 bit latch w 0 9 X w 6 00 CONTROL 443 857 74L8367 10138 Hex bus driver Page 11 11 Parts List _ _ _ _ HEATH MAYBE DESCRIPTION LEAD CONFIGURATION PART REPLACED TOP VIEW NUMBER WITH PARALLEL III INPUT Es io L 443 892 7418166 132 I SSES CAN Register CLEAR ud Y CLOCK c o A dock OND W PARALLEL INPUTS 443 896 74802 Quad 2 Input NOR 443 897 74504 U140 U141 HEX inverter 443 900 74574 U120 U129 Dual D flip flop 0 IC IP I 10 GO Page 11 12 Parts List HEATH MAYBE DESCRIPTION LEAD CONFIGURATION PART REPLACED TOP VIEW NUMBER WITH 4 IL 3 3t 5 Ha 443 976 74808 U142 Quad 2 input AND 1 z 2 D on n mn II 7M 10 IM A2 IM AL 443 980 745244 11101 0108 r Noninverting 3 state output octal buffers 54 M s 443 1027 6116 P4 9115 2K x 443 1046 74511 U128 EL Triple 3 input AND d Page 11 13 Parts List HEATH MAYBE DESCRIPTION
2. BT2 RECEIVE RECON TRANSMITTER INHIBIT XXX XXX XXX TIMER xxx AVAILABLE The three maskable status bits are anded with their respec live mask bits and the results along with the POR status bit are or ed to produce the processor interrupt signal INTR This signal returns to its inactive low state when the Inter rupting status bit is reset to a logic 0 or when the corre sponding bit in the MASK register is reset to a logic 0 To clear an interrupt generated as a result of a Power On Reset or Reconfiguration occurance the CLEAR FLAGS com mand should be used To clear an interrupt generated as a result of a completed transmission TA or a completed reception Al the corresponding masks bits should be reset to a logic zero WRITE COM 9026 COMMANDS Execution of the following commands are initiated by performing a processor write with the written data defining the following commands DISABLE THANSMITTER This command will cancel any pending transmit command transmission has not yel started when the COM 9026 next receives the token This com mand will set the TA Transmitter Available status bit when the token is received DISABLE RECEIVER This command will cancel any pending receive command the COM 9026 is nol yet receiving a packet the RI Receiver Inhibited bit will be set the next time the token is received II packet rec
3. REGISTER Ar MI L WE OE Argan AO ano COM 9026 BLOCK DIAGRAM FIGURE 2 TYPICAL COM 9026 INTERFACE Page 12 16 Data Sheets DESCRIPTION OF PIN FUNCTIONS refer to figure 2 PINNO NAME SYMBOL FUNCTION 31 32 35 00865510 A10 9 These three output 5 are the three most significant bits of the RAM buffer address These is are in their high impedance stale except during COM 9026 access cycles to the RAM buffer A10 and 9 will take on the value as specified in the ENABLE RECEIVE or ENABLE TRANSMIT commands to trom page nn and should be viewed as page select bits For packets less than 256 a 1K bulfer can be used with 8 unconnecled For packets greater than 256 bytes a 2K buffer is needed with AB connected 21 22 23 ADDRESS AD7 ADO These 8 bidirectional signals are the lower bits of the RAM buffer address and 24 25 26 DATA 7 0 the 8 bit data path in and out of the COM 9026 ADO is also used for O command 27 28 m decoding of the processor control or status commands to the COM 9026 8 O REQUEST This input signal indicates tha the processor is requesting the use ol the dala bus to receive status information orto issue a command lo 9028 This signal d 15 sampled internally on the falling edge of 9 MEMORY MREG AS REQUEST to translar
4. RER BRE ELE 528 Page A 7 ID Node Number Lookup Table IDNO POSITION DEC HEX 0 1 2 3 4 5 6 7 217 09 OFF OFF ON OFF OFF ON OFF 218 OFF OFF OFF OFF OFF 219 OFF OFF ON OFF OFF ON OFF OFF 20 OFF OFF ON OFF OFF OFF ON 221 DD OFF OFF ON OFF OFF OFF OFF 222 DE OFF OFF ON OFF OFF OFF OFF 223 DF OFF OFF OFF OFF OFF OFF OFF 224 OFF OFF OFF ON ON ON 225 E1 OFF OFF OFF ON ON ON OFF 226 E2 OFF OPF OFF ON ON OFF ON 227 E3 OFF OFF OFF ON ON OFF 228 E4 OFF OFF OFF ON OFF ON 229 5 OFF OFF OFF ON ON OFF ON OFF 230 E6 OFF OFF OFF ON ON OFF OFF ON 231 E7 OFF OFF OFF ON ON OFF OFF OFF 232 E8 OFF OFF OFF OFF ON ON ON 233 E9 OFF OFF OFF ON OFF ON ON OFF 234 EA OFF OFF OFF ON OFF ON OFF ON 235 EB OFF OFF OFF OFF ON OFF OFF 236 EC OFF OFF OFF ON OFF OFF ON ON 237 ED OFF OFF OFF ON OFF OFF ON OFF 238 EE OFF OFF OFF OFF OFF OFF ON 239 EF OFF OFF OFF ON OFF OFF OFF OFF 240 0 OFF OFF OFF OFF ON CM ON ON 241 F1 OFF OFF OFF OFF ON ON OFF 242 F2 OFF OFF OFF OFF ON ON OFF ON 243 F3 OFF OFF OFF OFF ON ON OFF OFF 244 F4 OFF OFF OFF OFF OFF ON ON 245 F5 OFF OFF OFF OFF OFF ON OFF 246 F6 OFF OFF OFF OFF ON OFF OFF ON 247 7 OFF OFF OFF OFF OFF OFF OFF 248 F8 OFF OFF OFF OFF OFF ON ON ON 249 F9 OFF OFF OFF OFF OFF ON OFF Page A 8 ID Node Number Lookup Table IDNO POSITION DEC 0 1 2 3 4 6 7 OF
5. Page 1 7 Introduction Network Reconfiguration At network reconfiguration time all ID numbers up to 255 are polled Each node will remember the next ID number NID the token was passed to In this way the token will be passed only to active ID numbers prevent ing wasted time Every time a node is powered up in the network a network reconfiguration will occur The network reconfiguration consisting of eight marks and one space repeated 765 times will destroy the token and prevent another node from taking control of the network When a node is powered down or disconnected there is no need for a network reconfiguration When the preceding node does not receive a response from its invitaton to transmit it will increment the NID it has stored and send another invitation to transmit The node will continue to increment the NID and retransmit until a response is received from an active node Packet Transfer Transmit When a node receives the token and it has a packet or message it wants to send it looks at the destination ID DID and sends a free buffer inquiry to that ID if the DID is 0 it signifies a broadcast to all nodes the DID responds with an acknowledge ACK the node will send the packet If there is no acknowledgment NAK or ACK is not received after 74 microseconds the node will pass the token to the NID Receive The node receiving a free buffer inquiry checks the receiver inhibited flag If the flag
6. Referring to figure 6 a dipulse appearing an the coax CA is coupled to the receiver via RF transformer T1 and passed through a filter network matched to the 93 character istic impedance of the coax The filter output feeds a 75108 comparator which produces a positive pulse on RCVD for each dipulse received from the coax The RCVD signal feeds the circuitry shown in figure 4 which converts these pulses to data on the AX signal entering the COM 9026 Fig ure illustrates the timing associated with this function The CABLE TRANSCEIVER shown in figures 4 and 6 has been designed to operate in a baseband cable system using a network topology where any 2 nodes are con nected by a single path which is terminated at both ends with the cable s characteristic impedance Figure 9 illus trates a typical free forming tree topology which is used in the implementation By using central HUBs each node connects through a length of cable to a port on a HUB with the cable terminated as previously described No taps are used on the coax The COM 9032 local area network transceiver housed ina 16 package can replace all Ihe logic shown in figures 1 and 4 and simplify the building of ARCNET compatible networks by performing the following functions 1 Generation of CA and CLK clocks for the COM 9026 with high voltage drive MI 2 Creation of PULSE 1 and PULSE 2 wavelorms during transmit 3 Conversion of received d
7. 20 19 18 17 16 ON ON ON ON OFF OFF OFF OFF SW102 This switch in conjunction with SW104 selects the location of the ROM For example to select the address 0F4000 Hex SW104 would have the following configuration POSITION 0 1 2 3 4 5 7 ADDRESSBIT A16 17 18 A19 A20 A21 22 23 ON OFF OFF OFF OFF OFF ON ON ON ON W103 This switch in conjunction with SW107 selects the I O addres S location For example to select 00A0 HEX SW107 would have the following configuration POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT A7 5 4 A2 Ai NC ON OFF OFF ON OFF ON ON ON ON X SW104 This switch in conjunction with SW102 selects the location of the ROM 0F4000 SW104 would have the following configuration POSITION 0 1 2 3 4 8 6 7 ADDRESSBIT 15 14 13 X X X X X ON OFF ON SW105 This switch selects the ID node number There should be a unique node number for every unit in the network When position 7 is set OFF and all other positions ON the ID node number is 1 When posi lion 6 is set OFF and all other positions ON the node number is 2 etc The following settings will select ID node number 114 72H POSITION 0 1 2 4 5 6 7 ON OFF ON OFF OFF OFF ON ON OFF ON Page 4 7 Configuration NOTE This 114 number is different from the typical configuration to pro vide another example of ID number selection NOTE To insure proper setting refer to memo
8. CLOCK GLK A continuous 5 MHz clock input used for timing of the 8026 bus cycles bus arbitration serial ID input and the internal timers 2 CA CA This input signal is a 5 MHz clock used to contro the operation of tha COM 9026 Sequencer This input is periodically halted in the high state by the DSYNC output 4 36 DELAYED DSYNC This output signalis asserted by Ihe COM 9026 to cause Ihe external clock SYNC erator logic to halt the CA clock Refer to figure 9 40 POWER ON POR This signal clears the COM 9026 microcoded sequencer program counter RESET to zero and initializes various internal control flags and status bits The POR tus bit is also sel which causes the INTR output lo be asserted Repeated as tion of this signal will degrade the performance ol the network 39 5 VOLT VI Power Supply SUPPLY 20 GROUND GNO Ground PROTOCOL DESCRIPTION LINE PROTOCOL DESCRIPTION The line protocol can be described s isochronous becausa each byte is preceded by a start interval and ended with a stop interval Unlike asynchronous protocols there is a con stant amount of time separating each data byte Each byte will take up exactly 11 clock intervals with a single clock inter val being 400 nanoseconds in duration As a result 1 byte is transmitted every 4 4 microseconds and the time to transmit a message can be exactly determined The line idles in a spacing logic 0 condition A logic 0 is de
9. During any message transmission each node will receive the source ID SID and destination ID DID and store the SID into RAM buffer location 02 of the current page enabled for receive Il the message is not directed at the particular node the message itself is not deposited into the RAM buffer Every node therefore will store atleast the source of every message sent on the network making it possible to monitor the traffic activity In addition continual loading o a TRANSMIT com mand followed immediately by a DISABLE TRANSMIT command makes it possible to measure the time for one complete token pass Once the DISABLE TRANSMIT command is loaded the command will not actually end un lil the node next receives the token In this case the TA bit in the status register is used to inform the host processor that the token has been passed through the node since only receipt of the token will allow the DISABLE TRANS MIT command to be completed By measuring the time between successive settings 0 the TA status bit an accu rate measure of the time for every round trip token pass can be determined A NETWORK RECONFIGURATION occurs when ever a new network node is first activated onto the system In the normal course of events nodes are always being activated and the system adjusts this by initiating a NET WORK RECONFIGURATION The time to complete a NETWORK RECONFIGURATION and return to a normal operating environment is a function of the
10. RAM Test The following is a test routine to determine if the RAM is operating properly Using a work processor program or EDLIN enter the following under file RAM ASM NET MELADRS 0F000H DGROUP GROUP DSEG STACK GROUP GROUP CSEG ASSUME CS CGROUP DS DGROUP SS DGROUP ES NOTHING DSEG SEGMENT DATA BUFFER O DB 0 0 OFFH DSEG ENDS STSEG SEGMENT STACK DB 25600 7 STSEG ENDS CsEG SEGMENT INITMEMIST PUSH PUSH X PUSH PUSH Dx AX DGROUP DS INIT BUFFFR MOV AX NET MENADRS ES 0 NOV Page 6 2 Initial Tests LOOP MOY JMP POP POP POP POP CSEG ENDS END Type RAM ASM IM RAM Type ES BX AL LOOP DX LED D105 should light while this test is being performed If LED D105 does not light refer to Chapter 10 Service Instructions Test The following is a test routine to determine if the network is operating properly Using a word processor program or EDLIN enter the following under file NET IOADRS DGROUP CGROUP STSEG STSEG CSEG INIT NET 000A0H DSEG STACK CSEG CS CGROUP DS DGROUP SS DGROUP ES NOTHING STACK 256 DUP BRRARE 4 Page 6 3 Initial Tests LOOP TRANSMIT LOOP TA 0 Mov DX NET IO ADRS IN AL DX AND AL 01 AL 0 JE 100 0 MOV DX NET IOADRS 1 MOV AL 003H JMP LOOP TRANSMIT POP DX POP Cx
11. SERVICE MANUAL Zenith Local Area Network Interface Card NET 100 1 Z 100 Series Computers 4 15 40 02 860 42 data ystems The purpose of this page is to make sure that all service bulletins are entered in this manual When a service bulletin is received annotate the manual and list the information in the record below Record of Service Bulletins SERVICE CHANGED PURPOSEOFSERVICE INITIALS PAGE S Contractor is Zenith Data Systems Corporation o St Joseph Michigan 49085 The entire document is subject to Limited Rights data provisions Copyright 1982 1983 Standard Microsystems Corporation Copyright 1984 Zenith Data Systems Corporation all rights reserved Printed in the United States of America Zenith Data Systems Corporation St Joseph Michigan 49085 Contents Abbreviations Specifications Chapter 1 100 1 Card Network Operation Network Reconfigui Packet Transfer Transmit Receive Parts Supplied Tools Required Chapter 2 Introduction 100 Bus Chapter 4 Introduction Typical Configuration Detailed Configuration Data Pls lt TT ET TIT RTT Chapter 5 Installation Introduction 5 1 100 1 Card Installation 5 1 5 2 Chapter 6 Initial Tests Introduction 6 1 6 1 VO Test 6 2 Memory Test 6 3 Chapter 7 Reassembly 71 2 74
12. When node is powered off the previous node will attempt to pass it the token by issuing an INVITATION TO TRANSMIT Since this node will not respond the previous node will time out and transmit another INVITATION TO TRANSMIT to an incre mented ID and eventually a response will be received The time required to do a NETWORK RECONFIGURA TION depends on the number of nodes in the network the propagation delay between nodes and the highest ID number on network but will be in the range of 24 to 61 milliseconds BROADCAST MESSAGES Broadcasting gives a particular node the ability to transmit a data packet to all nodes on the network simultaneously ID zero is reserved for this feature and no node on the net work can be assigned ID zero To broadcast a message the transmitting node s processor simply loads the RAM buffer with the data packet and sets the destination ID DID equal to zero Figure 8 illustrates the position of each in the with the DID residing at address 01 HEX of the current page selected in the TRANSMIT command Each individua node has the ability to ignore broadcast mes sages by setting the most signficant bit of the ENABLE RECEIVE TO PAGE nn command see WRITE COM 9026 COMMANDS to a logic zero gt _ __ COM 9026 OPERATION BUFFER CONFIGURATION During a transmit sequence the 9026 fetches data from the Transmit Buffer a 256 or 512 byte segment of the RAM buffer The ap
13. i27 HE 443 791 Buffer driver tri state Page 11 6 Parts List Network Chassis Adapter Network Chassis Adapter is Part Number 191 3637 1 Refer to Figure 11 2 ITEM NUMBER ITEM NUMBER ITEM NUMBER 5 10 15 20 25 855858 PART NUMBER PART NUMBER PART NUMBER 200 1466 1 250 1434 259 27 344 222 432 866 or 432 1063 432 865 344 220 21 46 259 1 253 746 DESCRIPTION DESCRIPTION DESCRIPTION Chassis with BNC adaptors Screw 6 BT x 375 Solder lug Red wire 1 MOLEX 3F MOLEX Black wire 5000 pf capacitor Solder lug Washer insulated Page 11 7 Parts List 20 25 25 25 Figure 11 2 Network Chassis Adapter Exploded View 22 25 Page 11 8 Parts List Semiconductor Identification This section provides assistance in semiconductor identification by use of a cross reference between Heath part numbers and semiconductor part numbers The Heath part numbers are listed in numerical order with replacement part numbers if available description and lead configuration in adjacent columns The PAL equations also are presented in this chapter Part Number Index HEATH MAY BE DESCRIPTION LEAD CONFIGURATION PART REPLACED TOP VIEW NUMBER WITH _ u m fa 41 18 DL 14CB125 U126 125ns delay line 1 4 IN GND NT MES WM tad CATHODE 150 162 Ava
14. ADIE Address Data Input Enable AS Address Strobe BINP Bus Input BMEMR Bus Memory BOUT Bus Output BSYNC Bus Synchronization CE Chip Enable CLK Clock CR Carriage Return DBIN Data Bus Input DID Destination Identification Number DIP Dual Inline Pack DIS Disable EN Enable EOT End Of Time ESDS Electrostatic Sensitive Devices ET Extended Timeout LED Light Emitting Diode IDDAT ID Data In IDLD ID Load yo Input Output ILE Interface Latch Enable IM Interface Module IOADRS Input Output Address IOREQ Input Output Request ID Identification Number INTR Interrupt LANC Local Area Network Controller LANT Local Area Network Transceiver MASM Macroassembler MEMADRS Memory Address MEMREQ Memory Request MUX Multiplexer NAK No Acknowledgment NID Next Identification Number Output Enable PAL PRSFF PULS RDY REQ ROM ROMSEL SID vii Abbreviations Programmable Array Logic Preset Lines Preset Flip Flop Pulse Random Access Memory Ready Request Read Only Memory ROM Select Receive Source Identification Number Transmit Write Enable Zenith Local Area Network Page Viii Specifications Buffer RAM Size ROM Size Options Maximum Nodes Per Interrupt Operation System Local Area Network Controller Local Area Network Interface RAM VO Access Time ROM Access Time 2K 8 6116 4 4K x 1 2732 2 8K x 8 2764
15. Block Diagram Page 8 2 Theory of Operation The NET 100 1 Card is divided into nine main sections Bus Buffers Multiplexers System Decode and Control Wait Generation Read Only Memory ROM Random Access Memory RAM Network Controller ID Number Active Hub The following paragraphs describe each ot these sections Bus Buffers The bus buffers are receivers and drivers for the S 100 address data and control signals Multiplexers MUX The address data multiplexers pass the 8 bit address onto the internal 1 0 1 7 bus line to the network controller The 8 bit data is then passed lo the controller in the same way System Decode and Control The system decode and control circuits contain all the logic necessary to control memory and I O accesses 8 and 16 bit data transfers interrupts and phantom assertion Wait Generation The wait generation circuitry receives the network control wait signal and transforms it to the S 100 ready signal Page 8 3 Theory of Operation Read Only Memory ROM The ROM allows the capability of booting in a non disk environment The support circuitry provides 24 bit switch selectable location in memory phantom contro optional through a jumper The board does not come equipped with the ROM installed Random Access Memory RAM The 2K x 8 RAM can be accessed by both the network controller and the system processor The RAM location in memory is 24 bit switch sele
16. COMMENTS V Input low voltage 03 08 input high voltage 1 22 Vec excep CAand CLK VS input high voltage 2 v 05 65 V for Aor CLK output low voltage 1 04 V 16ma Va Output low voltage 2 05 20ma Von output high voltage 1 24 v L input leakage current 10 Inputcapacitance 20 Cra dala bus capacitance 50 pf C all other capacitance 30 pt ke power supply current 350 ma apr 220 nu FIGURE 20 TYPICAL CLOCK GENERATOR CIRCUITRY Page 12 26 Data Sheets AC ELECTRICAL CHARACTERISTICS 0710 70 C Voc 5 0V 5 TYP delay trom o wat of DWH setup time ILE delay from CLK processor addr setup trom AD bus Hi to olay rom CLK rising edge delay of IDDAT trom CLK rising edge strobe amp data hold for write addr enable setup to WAIT ADIE to OE delay COM 9026 write data hold time OE to RAM data valid status setup to AS lalling edge status hold from AS failing edge RX setup to CA rising edge RX hold time from rising edge active time oog 8 55 55 8589 588 coco 885808585 8 88 888 2 100 aaaaaaaaaa 22 a 22228 22222222222 after V_ has been stable for time t the minimum active time is 10 of CLK E Lei atico ore The above timing information is valid for a worst case 40 t
17. ID into the COM 9026 The shift ont 1 clocked with Ihe same signal that feeds the COM 9026 on pin 19 Dn liming associated with this signal and IDDAT pin 34 is illustrated in ligure 19 34 ID DATA IN IDDAT This input signal is the serialized output the external ID shift register The ID m is shifted in most significant bit first high level is defined as a logic 1 13 2 The levels on these two input pins specify the timeout durations used by the COM TIMEOUT 9026 m network protocol Refer to the section entitled Extended Timeout 2 Function lor details 37 TRANSMIT Tx This output contains the serial transmit data to the CABLE DATA TRANSCEIVI 38 RECEIVE This input signal contains the serial receive data from the CABLE DATA TRANSCEIVER Page 12 17 Data Sheets DESCRIPTION OF PIN FUNCTIONS Continued PIN NO NAME VM80L FUNCTION 4 5 TESTPIN2 TEST2 These pins are grounded normal chip operation These pins ara used n TEST PIN TEST conjunction with and 611 to enable various internal diagnostic functions when performing chip level testing _ _ 30 ECHO ECHO When this input signal is low the COM 9026 will re transmit all mes ot DIAGNOSTIC length less 254 bytes Tris input should be led high lor normal chip opera ENABLE tion and is only utilized when performing chip level testing 18
18. LEAD CONFIGURATION PART REPLACED TOP VIEW NUMBER WITH Ca 9 0 511 L 443 1112 9602 137 D retriggerable monostable multivibrator 1 gt 443 1128 74503 Open collector 2 input NAND En 443 1133 74532 1136 Quad 2 Input on 443 1159 25152521 U105 0106 0110 10130 0134 0135 8 6 comparator Page 11 14 Parts List HEATH MAYBE DESCRIPTION LEAD CONFIGURATION PART REPLACED TOP VIEW NUMBER WITH 444 222 Available 0107 only from PAL16LB memory Zenith Data Systems timing control or Heath Company 234 425 Available 1 101 from 1 102 Zenith Data Systems IM103 or Heath Company Cable Interface abe 184222556 5 2 47 92772 EF L we le S Page 11 15 Parts List PAL Equations PAL equations are Boolean expressions where equals a negated signal equals an AND function and equals an OR function PAL16L8 444 222 S 100 Bus 9026 Interface MEMADR2 INTR9026 MEMADR1 BSYNC BOUT BINP BMEMR BWO GND PGMGND IOREQ MREQ 5 2 PHANTOM1 NC VCC IF MEMADR2 1 BOUT BWO PHANTOM2 PGMGND INTR9026 INTR INT
19. ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF POSITION 3 4 OFF ON OFF OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF ON OFF OFF ON OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF ON ON OFF ON OFF OFF ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON OFF OFF ON ON OFF OFF ON OFF OFF ON ON OFF OFF ON OFF OFF ON OFF ON OFF ON OFF ON OFF OFF ON OFF ON OFF ON OFF ON OFF OFF ON OFF ON OFF ON OFF OFF OFF ON OFF ON OFF ON OFF ON ID Node Number Lookup Table IDNO Page A 6 bab 555 Sak she 565 555 555 555 565 555 585 555 555 555 bbs 565 555 555 558 555 555 bas 555 SRE sss 558 bbs 555 SEE 588 555 SEE 555 555 5 555 555 ESE bbs sss 555 555 555 EEE 555 sss 555 BEE BEE bbs 555 888 555 555 555 EEE EEE 555 BEE 555 EEE 555 888 555 888 888 888 555 888 888 888 558 555 555 SEE 555 555 555 555 EEE EEE 555 BEE BEE BEE SEE BEE EEE 555 555 EEE EEE 555 0 285 888 888 58 580 588 588 588 885 858 888 858 gas 388 858 838 858
20. POP BX POP AX RET CSEG ENDS END Type MASM 10 Type LIM 10 Type 10 LED 0102 should light while this test is being performed If LED 0102 does not light refer to Chapter 10 Service Instructions Memory Test The purpose of this test is to determine if the RAM and its interface to the system are operating properly If a difficulty is encountered while this testis being performed refer to Chapter 10 Service Instructions 1 Turnonthe computer and monitor 2 After the prompt type 000 0 the monitor will show Examine F000 0 RETURN The following be displayed on the monitor F000 0000 D1 RETURN Page 6 4 Initial Tests Now F000 0001 64 should be displayed or the ID node number set by SW105 in Hex This number will differ depending on the ID number your board is set for RETURN 3 When the memory location is given on the screen type the number listed below After every entry hit a carriage return to advance to the next memory location ONSCREEN TYPE F000 0002 F000 0003 2 F000 0004 s F000 0005 4 F000 0006 F000 0007 F000 0008 i F000 0009 F000 000A F000 0008 F000 000C F000 000D F000 0008 F000 000F F000 0010 Q 4 Hitthe DELETE key to get the prompt back 5 TypeDF000 0 10 RETURN The following should be displayed indicating that the RAM can be written to and read from F000 0000 D1 64 01 02 03 04 05 06 07 08 09 0A OD OE F000 00
21. Page iv Contents Chapter 8 Introduction Bus Buffers 82 Multiplexers MUX 8 2 System Decode and Control 8 2 Wait Generation 8 2 Read Only Memory ROM 83 Random Access Memory RAM 8 3 Network Controller 8 3 ID Number 8 3 Active Hub 8 3 Chapter 9 Circuit Description Introduction 91 Bus Buffers 9 1 Multiplexers 9 1 COM9026 Interface U116 91 System Decode Control 9 2 16 bit Addressing 9 2 B bit Addressing 93 Interrupt 93 Phantom 94 Wait Generation 94 ROM Circuitry 9 6 RAM Interface 9 8 Network Controller 9 9 ID Number 9 9 Active Hub 9 10 Chapter 10 Service Instructions Introduction 10 1 Troubleshooting 10 1 Chapter 11 Parts List Introduction 11 1 Replacement Parts 11 2 NET 100 1 Network i 11 3 Network Chassis Adapter 11 6 Semiconductor Identification 11 8 Part Number Index 11 8 PAL Equations 11 15 Chapter 12 Data Sheets 1241 Data Sheets COM9026 Local Area Network Controller LANC 12 2 C0M9032 Local Area Network Transceiver LANT 12 16 Page V Contents Appendix ID Node Number Lockup Table 14 1 2 13 14 31 32 41 54 52 7 1 72 8 1 91 92 11 1 11 2 Tables 91 ROM Jumper Configuration 2 10 1 9 7 10 1 Page Vi Abbreviations ACK Acknowledgment
22. Redundancy Check characters polynomial used is X X 1 Acknowledgements An ALERT BURST followed by one character an ACK ACKnowledgement ASC I code 06 HEX character This message is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER ENQUIRIES Negative Acknowledgements An ALERT BURST followed by one character Neg ative AcKnowledgement ASCII code 15 HEX This mes sage is used as a negative response to FREE BUFFER ENQUIRIES NETWORK PROTOCOL DESCRIPTION Communication on the network is based on a modified token passing protocol A modified token passing scheme is one in which all token passes are acknowledged by the node receiving the token Establishment of the network config uration and management ol the network protocol are han died entirely by the COM 9026 s internal microcoded sequencer A processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the RAM buffer and issuing a command to enable the transmitter When the COM 9026 next receives the token it verifies that the receiving node is ready by first transmit ting a FREE BUFFER ENQUIRY message II the receiving node transmits an ACKnowledge message the data packet is transmitted followed by a 16 bit CRC If the receiving node cannot accept the packet typically its receiver is inhibited it transmits a Negative AcKnowledge messag
23. STANDARD MICROSYSTEMS CORP 48354 Page 12 14 Data Sheets ANDARD MICROSYSTEMS COM 9026 Local Area Network Controller LANC FEATURES 2 5 M bit data rate ARCNET area network controller C Modified token passing protocol O Self reconfiguring as nodes are added or deleted from network T1 Handles variable length data packets L1 16 bit CRC check and generation System efficiency Increases with network loading 0 Standard microprocessor interface Supports up to 255 nodes per network segment C Ability to interrupt processor at conclusion of commands 1 Interfaces to an external 1K or 2K RAM buffer 0 Arbitrates buffer accesses between processor and COM 9026 Replaces over 100 MSI SSI parts 0 Ability to transmit broadcast messages 0 Compatible with broadband or baseband Systems Compatible with any interconnect media twisted pair coax etc PIN CONFIGURATION RA REG 8 Arbitrary network canfigurations can be used star tree etc Single 5 volt supply GENERAL DESCRIPTION COM 9026 8 a special purpose communications adapter for interconnecting processors and intelligent peripherals using the ARCNET local area network The ARCNET local area network is sell polling modified token passing net work operating at a 2 5 M bit data rale A modified loken passing scheme is one
24. a low ataD input Power up clears 0119 initializing all of the Q outputs low The Q outputs are the D inputs to U120 and U129 and remain low until a data pulse toggles one output high For example assume the onboard port is the first to transmit PULS2 from U123 1 is applied to U129 11 through inverter U140 4 The low at U129 12 is clocked through to U119 13 04 and U128 3 putting a low this will occur if any of the D inputs to U119 are low at U142 3 This causes U125 11 to go high U125 11 feeds four inputs U137 12 U125 5 U128 9 and U128 2 Remember that at this point the Q outputs of U119 are still low causing 0141 pins 8 10 and 12 to be high These three high inputs to the AND gate U128 cause the output to go high and provide U119 the required positive edged clock Q1 Q2 and Q3 of U119 remain high since the flip flops have not toggled The low at D4 is clocked through causing Q4 to go low U137 9 IDLE goes low 4 9 usec after a high is applied to U137 12 U137 is a one shot whose timing is determined by R111 and C151 IDLE enables U127 which turns on the LED whose line is active When no signal is present U137 9 is high and the diodes LED s are unlit In this case Q4 is low therefore D109 will light If one of the other ports is transmitting the corresponding LED will light U137 10 is high at the same time as IDLE and causes U137 7 to go low after a time determined by R112 and C123 when IDLE becomes in
25. is not tied to logic or chassis ground but is AC coupled to chassis ground at the back panel through the chassis adapter box Pins 6 and 3 of the interface modules are connected to 5V and 5V power supplies Pin 7 RX is the incoming signal which is tied to the clock line on the flip flops U120 pins 11 and 3 and 0129 3 Chapter 10 Service Instructions Introduction This chapter contains information to assist in servicing and troubleshoot ing Check the jumpers and switches to be sure the NET 100 1 Card is confi gured properly If these settings are all correct and the trouble is still pre sent refer to Table 10 1 Troubleshooting Table 10 1 lists some problems you may encounter and some possible causes Table 10 1 Troubleshooting PROBLEM System fails to operate Card fails RAMTEST LED 0105 Card fails IOTEST LED D102 Card fails MEMORY TEST Interrupt LED D103 does not light when INTR is asserted POSSIBLE CAUSE Be sure the card is fully seated in the card connector Be sure line cord is plugged in Check all jumpers Check all switches Inspect all packages for proper seating in sockets SPOONS Check SW101 and SW106 for correct selection Check MREQ signal out of U107 If present U108 D105 otherwise U116 U111 U101 U134 U105 U107 Check 5 107 and SW103 for correct settings 2 Check signal out of U107 If present 140 D102 otherwise U
26. is set an NAK is sent to the source ID SID if not an ACK is sent Page 1 8 Introduction When a packet is transmitted the receiving node first writes the SID into its receive buffer Next it will look at the DID If the DID is neither 0 nor its ID number the node will ignore the rest of the packet f the DID corresponds to the receiving node s ID number the node will send an ACK to the SID set the receiver inhibited flag and write the packet into its receiver buffer For a broadcast DID 0 the node will store the packet in its receive buffer if broadcast reception is enabled If not enabled the node will ignore the rest of the packet Parts Supplied The following parts are supplied in this interface card package NET 100 1 Card NET 100 1 Chassis Adapter 2 6 BT x 375 Screws NET 100 1 USER S MANUAL The following accessories are optional 60 25 foot coax cable 61 100 foot coax cable Tools Required The only tools required for the installation of the NET 100 1 Card are a small flat blade screwdriver and a small Phillips screwdriver Chapter 2 Hardware and Host Computer Requirements Introduction The NET 100 1 Card uses the S 100 Bus Interface IEEE Standard 696 Therefore computers used with this card must meet the same standard Listed below are the S 100 Bus pins used signal type and their active level S 100 Bus Pin PINNO SIGNAL TYPE 4 S 5
27. lack of activity for greater than 4 9 When 081 fires 052 produces 150 which resets the octal register resets the signal SET and clears all B 74S74 s This corresponds to the idle state of the HUB and the process repeats when the next packet is received Itis possible to implement a passive HUB as shown in figure 12 This arrangement allows for a maximum of 4 ports For proper operation each port must be terminated in 93 ohms either by connecting il to an active node or attaching a 93 ohm BNC terminator to the unconnected port When the ports are terminated property each port will have an input impedance of 93 ohms Due to the considerable loss expe rienced in this arrangement it is recommended that no more than 4 nodes be connected in this manner FIGURE 9 TYPICAL NETWORK TOPOLOGY Page 12 8 Data Sheets FIGURE 10 ARCNET COMPATIBLE CABLE TRANSCEIVER USING THE COM 9032 Is a registered trademark of the Datapoint Corporation Page 12 9 Data Sheets TIT TOP VIEW MINICIRCUITS LAB PEOR Dren FIGURE 11B INTERFACE MODULE Q i FIGURE 12 4 PORT PASSIVE HUB Page 12 10 Data Sheets PROGRAMMING THE COM 9026 Packet Transmission Transmission of a message begins with the processor selecting a page in the RAM butter and writing the pack
28. noted that the data pattern D1 written into the RAM has been chosen arbitrar ily Only if the D1 pattern appears in the RAM buffer can proper operation be assured CLOCK GENERATOR The COM 9026 uses two separate clock inputs namely CA and CLK The CLK inputis a 5 MHz free running clock and the CA input is a start stop clock periodically stopped and started to allow the COM 9026 to synchronize to the incom ing data that appears on the RX input Figure 9 illustrates the timing of the CA clock generator and its relationship 10 the DSYNC output and the RX input The DSYNC output is used to control the stopping ol the CA clock On the next rising edge of the CA input after DSYNC is asserted CA will remain in the high state The CA clock remains halted in the high state as long as the RX signal remains high When the RX signal goes low the CA clock is restarted and remains running until the next falling edge of DSYNC See ligure 20 for an implementation of this circuit 7 vor KC SR P 33009 CLR ERE UTR OT Pais as EEC puru map o A pa yo 4 No FIGURE 6 PROCESSOR READ COM 9026 aw onto I PS an OD sa 3 ae FIGURE 7 PROCESSOR WRITE COM 9026 Page 12 23 Data Sheets FIG
29. the cycle by removing the WAIT output DWA should only be used if the processor cannot deliver the data to be written in enough time to satisfy the write setup time requirements of the RAM buffer By delaying the acti vation of DWR the period of the write cycle willbe extended until the write data is valid Since the architecture and oper ation of the COM 9026 requires periodic reading and writ ing of the RAM buffer in a timely manner holding the DWA input off for a long period of time or likewise by running the processor at a slow speed can result in a data overflow condition It is therefore recommended that if the processor write data setup time to the RAM buffer is met then the DWR input should be grounded For processor UO write cycles to the COM 9026 ADIE and AIE are used to enable the processor s address onto the interface data bus ILE is used to enable the processor s write data into the COM 9026 Delaying the activation of DWR will hold up the COM 9026 cycle requiring the same precautions as stated for Processor RAM Write cycles Lac sc lac 50 Lac och ve Lar Fe Lae sr Lee Lee Page 12 21 Data Sheets As stated previously processor requests occur at the fall ing edge ol AS if either OREO MREQ are active 9026 requests occur when the transmitter or receiver need to read or write the RAM buffer in the course of executing the command If the COM 9026 reque
30. the long packet enable flag is reset only short packets can be handled Whatever the packet length the COUNT byte will always Point to an address situated in the first 256 bytes of the page Selected Because of this message lengths of 254 through 256 bytes must be padded out to a length of al least 257 bytes in order to be handled Nodes equipped and configured for extended length messages can coexist in the same system as nodes not configured for extended length messages The DEFINE CONFIGURATION command merely informs the COM 9026 of the existence of an external 2K buffer and thus need only be issued at initialization time with standard messages less than 254 bytes proceeds in the normal fashion II an extended length message is sent to a node that does not have its long packet enable flag set the receiver will ignore it The transmitting COM 9026 will set TA bit but not the TMA bit If an attempt is made to have a node transmit an extended length message when the node does not have its long packet enable flag set the packet will not be sent and the TA bit will stay off until a DISABLE TRANS MITTER commandis issued To the host processor this sit uation will exactly as if a transmission were to anode that has its receiver inhibited Page 12 13 Data Sheets APPENDIX 1 DETAILED TIMING INFORMATION The following information is provided for the benefit ol users The lengths of the Ive types of COM 9026 transmi
31. x 375 HE 434 298 Socket HE254 1 Washer 6 lock 132 443 892 Register 252 77 Nut 6 32 x 2507 HE 434 299 Socket una HE 442 702 Voltage regulator u133 HE 443 26 Quad NAND 2 input HE215 675 Heat sink HE 434 298 Socket HE 250 1429 Screw 6 32 x 3757 443 1159 8 04 comparator HE254 1 Washer 6 lock HE 434 311 Socket HE 252 77 Nut6 32 250 0135 443 1159 8 54 comparator uns HE 443 1027 2k x 8 434 311 Socket HE 434 307 Socket I36 443 1133 Quad 2 input OR gate une HE 443 1161 LANG controller HE 434 298 Socket HE 434 253 Socket 443 1112 Dj retrg mon multvbrt Unz Not Supplied HE 434 312 Socket HE 434 299 Socket une HE 443 802 MUX quad 2 input tri state U138 HE 443 857 Buffer hex tristate or HE 434 299 Socket 443 1178 139 443 900 Dual D F F HE 434 299 Socket HE 434 298 Socket ung 443 752 Quad DF F Ut40 HE 443 897 Hex inverter HEN vit hE 443 007 VI20 HE 443 900 Dual D F F HE 434 208 Sosa 434 298 Socket 443 896 Quad NOR 2 input ve QUA ANO Input HE 434 298 Socket 22 HE 443 837 Latch B bit tri state w SV regulator 434 311 Socket U123 443 1162 LANT transciever ITEM PART DESCRIPTION HE 434 298 Socket NUMBER NUMBER 124 150 162 Crystal oscillator 1125 HE 443 26 Quad NAND 2 input 5 85 2940 1 PCboard HE 434 298 Socket 10 266 1203 Circuit board extenders U126 41 18 Delay line HE 434 298 Socket
32. 0 78 DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA BYTE 120 FIGURE 13 TYPICAL SHORT PACKET BUFFER 608 TRANSMIT ADDRESS DATA 00 2F 01 08 02 00 03 D4 200 12C D4 DATA BYTE 1 D5 DATA BYTE 2 D6 DATA BYTE 3 1FF DATA BYTE 300 FIGURE 14 TYPICAL LONG PACKET BUFFER FOR TRANSMIT e Typically the conclusion of a RECEIVE command which is flagged by the RI bit being set to a logic one will generate an interrupt and allow the processor to read or operate on the message as required Figure 15 illustrates the contents of a page in the RAM buffer after a packet is received for a source ID of and a destination ID of 91 with a packet length of 201 bytes C9 HEX Figure 16 illustrates the contents on the RAM bufer after a packet is received from a source ID of C3 and a destination ID of 1F with a packet length of 490 bytes 1EA HEX The COM 9026 will deposit packets in the RAM buffer in a format Identical to the transmit format allowing for a message to be received and then retransmitted without rearranging any bytes in the RAM buffer COM 9026 Interrupts When using the interrupt structure of the COM 9026 to time the issuing of the transmit and receive commands certain procedures should be followed The INT outputof the COM 9026 is generated in a variety of ways For the transmitter the INT output is generated by the logic function TA anded with bit zero in the interrupt mask register Assuming the mask reg
33. 10 0F NOTE F000 0001 should read the ID node number in hex set by SW105 Chapter 7 e Reassembly Introduction This chapter contains the information required to install the top of the Z 100 Computer after NET 100 1 Card installation configuration and tests Reassembly All in One Model Refer to Figure 7 1 Connect cable 134 1264 if using 8 inch disk drive Replace the top case by bringing it straight down into its position Using a small flat blade screwdriver slide the latches all the way to the front I This completes the reassembly of the all in one model Figure 7 1 Reassembly All in One Model Page 7 2 Reassembly Low Profile Model Refer to Figure 7 2 Connect cable 134 1264 if using 8 inch disk drive Replace the top case by bringing it straight downinto its position Push the latches all the way to the front This completes the reassembly of the low profile model PUSH FORWARD 7 2 Reassembly Low Profile Model Chapter 8 Theory of Operation Introduction This chapter provides a brief explanation of the theory of operation of the NET 100 Card If a more detailed theory of operation is desired refer to Chapter 9 Circuit Description Refer to the block diagram Figure 8 1 as you read the following description TE E MULTIPLEXERS Ca SARA CHASSIS ADAPTOR CONNECTOR RG62A COAX CABLE 100 ADDRESS BUS Figure8 1 NET 100 1
34. 135 U110 U107 1 U102 U103 U104 U112 U118 U122 U132 U138 0115 1 0138 0103 Continued Page 10 2 Service Instructions Table 10 1 Troubleshooting continued PROBLEM POSSIBLE CAUSE ROM LED 0104 does not light when ROM is 1 Check for correct settings on SW102 and SW104 being mapped 2 Check ROMSEL signal out of U130 If present U140 U131 D104 otherwise 0106 U130 ROM inoperative U108 U133 U136 U109 U117 RDY signal not generated U133 U139 U121 U136 U140 0142 0131 0116 All ports inoperable U118 U123 0124 U125 0142 U129 U119 0128 0141 0126 Ports 1 2 and 3 inoperable 1 U111 U119 0137 Onboard port inoperable 1 0123 U140 0129 0128 U119 U127 0109 LED 0109 not lit Port3inoperable 1 coax IM103 U141 U120 U128 U119 U127 LED 0108 not lit D108 Port 2 inoperable 1 coax 1 102 U141 0129 0128 U119 0127 LED D107 not lit D107 Port 1 inoperable 1 Bad coax IM101 0141 U119 027 D106 LED D106 not lit emissions 1 Badground between network interface and S 100 Chapter 11 Parts List Introduction This chapter includes a component view of the NET 100 1 Card and an exploded view of the Network Chassis Adapter to assist in the identification for replacement parts Adjacent to the circuit reference designator or exploded view number are the part number and description which must be supplied wh
35. 2 16K x 8 27128 2 Jumper selectable 8 bit or 16 bit addressing Jumper selectable 16 bit or 24 bit addressing 2000 feet 255 Jumper selectable VIO VI7 NMI and SMC COM9026 Zenith Hybrid EGA059102A 880 ns maximum 220 ns maximum RG62A Coax 93 Ohms BNC Connector S 100 IEEE Standard 696 8 11 volts DC Typical 1 6A Maximum 2 0A 12 volts DC at 03A Chapter 1 Introduction This chapter introduces the NET 100 1 Card Zenith Local Area Network ZLAN operation parts supplied and the tools required for installation NET 100 1 Card The NET 100 1 Card is a local area networking card compatible with Data point s ARCNET System It will allow the Z 100 Computer to interface with up to 255 similarly configured computers at a maximum distance of 2000 feet An active 4 port hub is incorporated on the NET 100 1 Card A local area network can be set up by daisy chaining or with the hub using the appropriate software This card is supplied fully populated and may be placed in any vacant card slot in the computer The active hub requires all units in a path or tree to be powered up for the system to communicate properly The card can be configured in many ways with the available switches and jumpers This capability is especially useful for configuring the memory on the card around system memory Yet the card can be used as supplied fully configured except for the ID number The ID number is a switch set to the desir
36. 3M MOLEX right angle HE 434 311 Socket U103 HE 443 791 Buffer driver tri state Resistors HE 434 311 Socket 8101 6 4532 12 45 3 VI04 443 837 Latch 8 bit tri state A102 HE 6 102 12 1 kohm HE 434 311 Socket R103 6 562 5 6 kohm U105 HE 443 1159 8 bit comparator 8104 HE 6 562 5 6 434 311 Socket 8105 HE6 562 5 6 kohm U106 HE 443 1159 B bit comparator R106 HE 6 562 5 6kohm HE 434 311 Socket R107 HE6 102 12 1 U107 HE 444 222 PAL S 100 9026 timing R108 HE 6 562 5 6kohm HE 434 311 Socket R109 HE 6 562 5 6 1108 443 980 Driver A110 Not Used HE 434 311 Socket A111 6 103 12 10 kohm U109 HE 443 791 Buffer driver tri state R112 6 512 12 5 1 kohm HE 434 311 Socket RP101 9 128 10 kohm resistor pack 443 1159 B bit comparator RP102 HE9 128 10 kohm resistor pack HE 434 311 Socket RP103 HE 9 128 10 kohm resistor pack Page 11 5 Parts List CIRCUIT CIRCUIT REFERENCE 205 REFERENCE 205 DESIGNATOR PARTNO DESCRIPTION DESIGNATOR PARTNO DESCRIPTION 443 980 Driver HE434 311 Socket HE 434 311 Socket U128 HE 443 1046 Triple AND 3 input VII2 HE 443 802 quad 2 input tri state HE 434 298 Socket or U129 HE 443 900 Dual D F F HE 443 1178 HE 434 298 Socket HE 434 299 Socket HE 442 702 regulator 130 443 1159 8 bit comparator HE434 311 Socket HE215 675 Heat sink 443 1128 NAND 2 input open collector 250 1429 Screw 6 32
37. 555 888 888 888 93 588 Page A 3 ID Node Number Lookup Table IDNO DEC HEX 0 zi 65 855 888 BEE 888 888 888 75 OFF ON CM OFF OFF ON CM ON OFF OFF ON CM OFF OFF OFF ON OFF ON ON OFF OFF ON ON RRR 555 588 88 88 555 888 555 85 558 555 885 888 888 555 888 885 555 855 11 888 555 888 555 888 885 885 858 885 888 555 888 555 888 885 OFF OFF ON OFF OFF OFF OFF OFF ON OFF OFF OFF ON OFF ON OFF OFF OFF 656 588 OFF OFF OFF OFF OFF OFF OFF CM CM CM 558 555 555 888 858 598 555 555 566 888 888 555 888 64 65 100 101 102 66 585 555 585 855 888 67 103 104 68 105 69 855 biz 555 888 BEE 888 106 6 107 68 108 6C Page 4 ID Node Number Lookup Table IDNO POSITION DEC HEX 0 1 2 3 4 5 6 7 109 6D ON OFF OFF ON OFF OFF ON OFF 110 6E ON OFF OFF ON OFF OFF OFF ON 111 6F ON OFF OFF OFF OFF OFF OFF 112 70 ON OFF OFF OFF CM ON ON ON 113 71 ON OFF OFF OFF ON ON OFF 114 72 ON OFF OFF OFF ON ON OFF 115 73 CM OFF OFF OFF ON ON OFF OFF 116 74 ON OFF OFF OFF OFF ON ON 117 75 ON OFF OFF OFF OFF ON OFF 118 76 ON OFF OFF OFF ON OFF OFF ON 119 7 ON OFF OFF OFF ON OFF OFF OFF 120 78 CM OFF OFF OFF OFF ON CM ON 121 79 ON OFF OFF OFF OFF ON OFF 122 ON OFF OFF OF
38. 9 HE 21 769 01 ceramic C140 Not Used Page 11 4 Parts List CIRCUIT CIRCUIT REFERENCE ZDS REFERENCE ZDS DESIGNATOR PARTNO DESCRIPTION DESIGNATOR PARTNO DESCRIPTION J107 HE 432 1102 Pin 3M MOLEX RP104 9 99 1 kohm resistor pack HE 432 1041 Pin 2F BERG RP105 9 99 1 kohm resistor pack 3108 432 1041 Pin2F BERG RP106 HE 9 128 10 kohm resistor pack HE 432 1102 Pin 3M MOLEX RP107 HE9 128 10 kohm resistor pack J109 HE 432 1041 Pin 2F BERG 108 9 128 10 resistor pack 432 1102 Pin 3M MOLEX RP109 9 128 10 kohm resistor pack J110 HE 432 1102 Pin MOLEX RP110 Not Used HE 432 1041 Pin 2F BERG 111 HE 9 120 150 ohm resistor pack 432 1102 Pin MOLEX 112 9 120 150 ohm resistor pack HE 432 1041 Pin2F BERG Switches J12 HE 432 1102 Pin 3M MOLEX HE 432 1041 Pin 2F BERG Swt01 60 657 SPST J113 HE 432 1102 Pin 3M MOLEX SW102 HE 60 657 DIP SPST HE 432 1041 Pin 2F BERG SW103 HE 60 657 DIP SPST 4114 HE 432 1102 Pin3M MOLEX SW104 HE 60 657 DIP SPST Sw105 HE 60 657 SPST Chokes and Pins SW106 60 657 DIP SPST I SW107 HE 60 657 DIP SPST L101 235 229 35uh RF choke L102 HE 235 229 35uh RF choke Semiconductors L103 HE 235 229 35uh RF choke L104 HE 235 229 35uh RF choke 443 980 Driver P101 HE 432 986 Pin 3M MOLEX right angle HE 434 311 Socket P102 HE 432 986 Pin 3M MOLEX right angle U102 HE 443 791 Buffer driver tri state P103 432 986 Pin
39. AM buffer by the COM 9026 another receive com mand can be issued to allow reception of the next packet while the first packet is read by the processor In general the four pages in the RAM buffer can be used for transmit Or receive in any combination In addition the processor will also use the interface bus 1A10 1AB IAD7 IADO when performing access cycles status reads from the COM 9026 or command writes to the COM 9026 To accomplish this double buffering scheme the RAM buffer must behave as dual memory To allow this RAM to be a standard component arbitration and control on the interface bus IA10 IAB IAD7 IADO is required to permit both the COM 9026 and the processor access to the RAM buffer and at the same time permit all processor O oper ations to or from the COM 9024 Processor access cycle requests begin on the trailing edge of AS if either is asserted These access cycles run completely asynchronous with respect to the COM 9026 Because of this upon processor access cycle requests the COM 9026 immediately puts the processor into a wait state by asserting the WAIT output This gives the COM 9026 the ability to synchronize and control the processor access cycle When the processor access cycle is synchronized by the 9026 the WAIT signal is even tually removed allowing the processor to complete its cycle For processor RAM buffer access cycles AIE and ADIE enable the p
40. EMADRS1 go low MEMADR1 and MEMADR2 outputs in coordination with the other inputs on the U107 PAL cause MREQ to become active The following switches are set to select OFOOOOH as used by the Z 100 SW101 POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT 23 22 21 20 19 18 17 16 ON OFF ON ON ON ON OFF OFF OFF OFF SW106 POSITION 0 1 2 3 4 6 8 7 ADDRESS BIT A15 14 A13 A12 A11 NC NC NC ON OFF ON ON ON ON ON X X X After U116 receives MREQ it generates latch L an active low pulse enabling U122 to transfer the stable address on the internal IADO IAD7 bus to the RAM U115 For a write cycle U116 pulses ILE low enabling data to be multiplexed to the IADO IAD7 bus WE generated by U116 allows the latched data to be stored in U115 For a read cycle the RAM sends data to the system processor or the network controller via the IADO IAD7 bus after U116 generates the pulse to the RAM Page 9 9 Circuit Description Network Controller The network controller circuitry consists of U116 U123 and U124 20 MHz oscillator The network controller circuitry operates at a 2 5M bit data rate and works under a token passing scheme by passing an invitation to transmit to the next active ID number U116 is the Local Area Network Controller LANC and U123 is the Local Area Network Transceiver LANT Together they provide the interface between the system and the network U124 provides the clock signal necessary for U123 to ge
41. ERFACE Figure 2 illustrates a typical COM 9026 to processor inter face The signals on left side of this figure represent typ ica processor signals with a 16 bit address bus and an 8 bit data bus with the data bus multiplexed onto the lower 8 address lines PAD7 PADO The processor sees a nel work node a node consists of a COM 9026 RAM buffer cable transceiver etc as shown in figure 2 as 2K memory locations and 4 1 0 locations within the COM 9026 The RAM buffer is used to hold data packets temporarily prior to transmission on the network and as temporary stor age of all received data packets directed to the particular node The size of the buffer can be as large as 2K byte loca lions providing four pages at a maximum o 512 bytes per page For packet lengths smaller than 256 bytes a 1K RAM buffer can be used to provide four pages of storage In this case address line AB sourced from either the COM 9026 or the processor should be left unconnected Since four pages of RAM buffer are provided both transmit and receive operations can be double buffered with respect to the pro cessor For instance after one data packet has been loaded into a particular page within the RAM buffer and a transmit command for that page has been issued the processor can start loading another page with the next message in a multi message transmission sequence Similarly alter one mes sage is received and completely loaded into one page of the R
42. F OFF ON OFF ON 123 7 ON OFF OFF OFF OFF OFF OFF 124 7c ON OFF OFF OFF OFF OFF ON ON 125 7D ON OFF OFF OFF OFF OFF ON OFF 126 7 CM OFF OFF OFF OFF OFF OFF ON 127 7F ON OFF OFF OFF OFF OFF OFF OFF 128 80 OFF ON CM CM ON CM ON ON 129 81 OFF ON ON ON CM ON OFF 130 82 OFF ON ON ON ON OFF ON 131 83 OFF ON ON ON ON ON OFF OFF 132 84 OFF ON ON ON ON OFF ON ON 133 B5 OFF ON ON ON ON OFF ON OFF 134 86 OFF ON ON ON ON OFF OFF ON 135 87 OFF ON ON ON ON OFF OFF OFF 136 88 OFF ON ON ON OFF ON ON ON 137 89 OFF ON CM ON OFF ON ON OFF 138 OFF ON ON CM OFF ON OFF 139 88 OFF ON CM ON OFF ON OFF OFF 140 OFF CM ON ON OFF OFF ON ON 141 8D OFF ON ON OFF OFF ON OFF 142 BE OFF ON ON ON OFF OFF OFF ON 143 8F OFF ON ON ON OFF OFF OFF OFF 144 90 OFF ON CM OFF CM ON CM ON IDNO 145 91 146 92 147 93 148 94 149 95 150 96 151 9 152 98 153 99 154 155 9B 156 9C 157 80 158 9E 159 9F 160 A0 161 Al 162 2 163 164 4 165 5 166 6 167 168 169 A9 170 AA 171 AB 172 AC 173 AD 174 AE 175 AF 176 B0 17 B1 178 B2 179 B3 180 B4 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Page 5 ID Node Number Lookup Table ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON
43. F ON OFF OFF 250 FA OFF OFF OFF OFF OFF 251 FB OFF OFF OFF OFF OFF 252 FG OFF OFF OFF OFF OFF FD OFF OFF OFF OFF OFF FE OFF OFF OFF OFF OFF FF OFF OFF OFF OFF OFF OFF OFF CM BRB 333 922 lt 9
44. F ceramic C112 HE 21 769 01 ceramic 0101 56 56 144149 HE 21 769 01 pF ceramic D102 HE 412 654 LED red C114 HE 21 769 01 pF ceramic 0103 HE 412 654 LED red cns HE 21 769 101 pF ceramic D104 HE 412 654 LED red D105 HE 412 654 LED red C116 HE21 769 01 pF ceramic D106 412 654 LED red 21 769 01 pF ceramic 0107 412 654 LED red C118 HE 21 769 01 pF ceramic 0108 HE 412 654 LED red cng HE 21 769 01 pF ceramic D109 HE 412 654 LED red C120 Not Used Interfaces and Jumpers C121 HE 21 769 01 ceramic 122 21 769 01 pF ceramic IM101 234 426 Cable interface C123 HE 21 750 56 pF ceramic IM102 HE 234 425 Cable interface 124 21 769 01 pF ceramic 1M103 234 425 Cable Interface C125 21 769 101 pF ceramic J101 HE 432 1073 Pin 10M MOLEX HE 432 1041 Pin 2F BERG C126 HE 21 769 101 ceramic C127 HE25 195 2 2 pF tantalum J102 HE 432 1102 Pin 3M MOLEX C128 HE 21 769 01 ceramic HE 432 1041 Pin 2F BERG C129 HE25 195 2 2 aF tantalum J103 HE 432 1102 Pin 3M MOLEX 130 Not Used HE 432 1041 Pin 2F BERG J104 HE 432 1102 Pin 3M MOLEX C131 HE 21 769 01 uF ceramic C132 HE 21 769 01 pF ceramic HE 432 1041 Pin 2F BERG C133 Not Used J105 HE 432 1102 Pin 3M MOLEX C134 HE 25 962 4 7 uF tantalum HE 432 1041 Pin 2F BERG C135 HE 21 769 101 pF ceramic J106 432 1102 Pin 3M MOLEX HE 432 1041 Pin 2F BERG C136 HE 21 769 01 pF ceramic C137 HE 21 769 01 pF ceramic C138 HE 25 962 4 7 uF tantalum C13
45. PINS JUMPERED 2732 2 J112 12 J113 12 J115 23 2764 2 J112 12 J113 23 J115 no jumper 27128 2 J112 23 J113 2 3 4115 12 The following switch settings of SW102 and SW104 correspond to address 0 4000 using a 2764 ROM SW102 POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT Ai6 17 A18 19 20 A21 A22 23 OFF OFF OFF OFF ON ON ON ON SW104 POSITION 0 1 2 3 4 5 6 7 ADDRESS BIT NC NC NC A15 A14 A13 X X X X X ON OFF ON When a ROM read occurs from this board DBIN and MEMR high U133 3 OE is low OE will enable the outputs 00 07 of U117 to U109 When 0136 pins 9 ROMSEL and 10 OE are low 0109 pins 1 and 19 low allowing data to pass from the ROM to the DIO DI7 of the S 100 Bus A ROM read from this board results in ROMSEL and BMEMR being high and the buffered output of U131 pin 11 being low causing the LED D104 to light U131 an open collector NAND gate is low when ROMSEL and MEMR go high J114 is an optional jumper to allow this signal PHANTOM to be asserted when the ROM is selected allowing the ROM to be mapped over existing memory space When configuring the 2 100 this jumper need not be used Page 9 8 Circuit Description RAM Interface U116 controls the timing for any RAM access whether it is by the network controller or the system processor When the address set by SW101 and SW106 equates with the address on the bus the outputs of U105 MEMADRS2 and U134 M
46. R9026 IF 2 1 BMEMR 1 PGMGND AS BSYNC MREQ MEMADR2 1 MEMR MEMADR2 MEMADR1 BOUT IOREQ IOADRS BINP IOADRS BOUT Chapter 12 Data Sheets Introduction This chapter contains the the necessary technical information to under stand the COM 9026 Local Area Network Controller LANC and the COM 9032 Local Area Network Transceiver LANT The following pages are reprinted with the permission of Standard Microsystems Corporation Page 12 2 Data Sheets TECHNICAL NOTE TN5 2 USING THE COM 9026 LOCAL AREA NETWORK CONTROLLER AND THE COM 9032 LOCAL AREA NETWORK TRANSCEIVER Page 12 3 Data Sheets The purpose of this technical note is to provide the information and schematics needed to implement the CLOCK GENERATOR and the CABLE TRANSCEIVER for the COM 9026 In addition some discussion of the transmission media network topology and network performance is included CLOCK GENERATOR Figures 1 and 2 illustrate the CLOCK GENERATOR and associated timing respectively The purpose ol this circuitry is to generate the CLK and CA signals for the COM 9026 A 20 MHz oscillator is used to allow proper control of the starting and stcpping of the CA signal The CLK signal is generated from a divide by 4 circuit using 2 7491126 The line protocol of the COM 9026 is designed to ensure that a negative transition always occurs 1 bit time before pa
47. S 6 S 7 S 8 VI4 S 9 VI5 S 10 Vi6 S 11 S 12 S 15 18 16 16 17 A17 20 GND B 24 OI B 29 5 30 4 31 A3 M 32 A15 M 33 A12 M 3 4 9 M 35 DATA1 WS 36 DOO M DATAO WS 37 A10 M 38 004 M DATA4 M S 39 005 M DATAS WS 40 006 DATA6 WS 41 DI2 M DATA10 M S ACTIVE LEVEL L O C Low open collector t oc L oc L oc L oc L 0 C OC H H H 0 Volts Line H ZIIZ gt gt gt gt gt Page 2 2 Hardware and Host Computer Requirements PINNO SIGNAUTYPE ACTIVE LEVEL 42 DI3 M DATA11 M S H 43 017 M DATA15 WS H 45 SOUT M H 46 SINP M H 47 SMEMR M H 50 GND B 0 Volts Line 51 8 Volts B 52 16 Volts B 53 GND B 0 Volts Line 59 19 M H 61 A20 H 62 A21 M H 63 A22 M H 64 A23 M H 67 PHANTOM M S Oc 70 GND B 0 Volts Line 72 RDY S H OC 73 INT S L 75 B L 76 pSYNC H 77 M L 78 pDBIN M H 79 H 80 81 A2 M H 82 H 83 A7 M H 84 AB M H 85 A13 M H 86 A14 M H 87 A11 M H 88 DO M DATA2 WS H 89 DO3 M S H 90 007 M DATA7 WS H 91 DI4 S DATA12 WS H 92 DI5 S DATA13 WS H 93 DI6 S DATA14 WS H 94 011 S DATA9 WS H 95 DIO 5 M S H 96 sWO M L 100 GND B Volts Line Ch
48. TR if enabled by the WRITE INTERRUPT MASK command The bit is reset low during a CLEAR FLAGS command BIT 1 Transmit Message Acknowledged TMA This bit 1 set high indicates that the packet transmitted as a result of an ENABLE TRANSMIT FROM PAGE nn command has been posilively acknowledged This bit should only be considered valid after the bit bit 0 is set Broadcast mesages are never acknowledged BIT 0 Transmitter Available TA This bit if set high indicates that the transmitter is available for trans mitting This bit is set at the conclusion of a ENA BLE TRANSMIT FROM PAGE nn command or upon the execution of a DISABLE TRANSMITTER com mand The setting of this bit can cause an interrupt via INTR if enabled by the WRITE INTERRUPT MASK command WRITE INTERRUPT MASK The COM 9026 is capable of generating an interrupt signal when certain status bits become true A write to the MASK register specifies which status bits can generate the inter rupt The bit positions in the MASK register are in the same position as their corresponding status bits in the STATUS register with a logic one in a bit position enabling the cor responding interrupt The setting of the EST1 and EST2 status bits will never cause an Interrupt The POR status bit will cause a non maskable interrupt regardless of the value of the corresponding MASK register bit The MASK register takes on the following bit definition BITS
49. URE 9 CA CLOCK GENERATOR TIMING EXTENDED TIMEOUT FUNCTION There are three timeouts associated with the COM 9026 operation Response Time This timeout is equal to the round trip propagation delay between the 2 furthest nodes on the network plus the max imum turn around lime Ihe time it takes a particular COM 9026 to start sending a message in response to a received message which is known to be 12 microseconds The round trip propagation delay is a function ol Ihe Iransmission media and network topology For a typical system using RG62 coax in a baseband system one way cable propagation delay 0131 microseconds translates to a distance of about 4 miles The flow chart in figure 3 uses a value ol 74 7 microsec onds 31 31 12 margin to determine il any node will respond Idle Time This time is associated with a NETWORK RECONFIGUR ATION Relering to figure 3 during a NETWORK RE CONFIGURATION one node will continually transmit INVI TATIONS TO TRANSMIT until it encounters an active node Every other node on the network must distinguish between this operation and an entirely idle line During NETWORK RECONFIGURATION activity will appear on the line every 78 microseconds This 78 microsecond is equal to the response time of 74 7 microseconds plus the time it takes the COM 9026 to retransmit another message usually another INVITATION TO TRANSMIT The actual timeout is set to 78 2 microseconds to allow for margin Reconfig
50. ac live EOT This signal is named EOT and stands for End of Time It is called this since a low on EOT causes PRSFF to reset the flip flops inthe same manner a power on of the system did Page 9 11 Circuit Description U125 5 starts the pulse generation through the delay line U126 The high on U125 5 is inverted and sent 10 U126 1 U126 12 1 then goes low and is connected to 1 of the interface modules P2 goes low after P1 and is connected to P2 of the interface modules The interface mod ules generate the dipulse to the coax U126 6 goes low after the original input U125 inverts the signal and U126 1 P1 and P2 go high limiting their pulse widths to 100 nsecs Note that P2 is inverted at U140 6 and connected to U123 10 RXIN U123 then generates RXOUT to U116 RXOUT is used for both U116 and the other three port network transmissions The Q outputs either Q1 Q2 or of U119 are inverted by 1141 and tied to the DIS EN lines pin 19 of 1 101 1 103 When the signal is high the interface module is disabled and when low it is enabled Initially all the DIS EN lines are low enabling the interface modules to receive data from the network A high on the DIS EN line prevents the interface modules from retransmitting and disturbing any incoming data The hybrid interface modules provide interface to the coax cable RG62 Pin 11 connects to the shield and 12 to the center of the coax cable The shield
51. alt the CA clock SYNC output This output is a 5 MHz starustop clock that is halted when DSYNC goes active low and restarted by a low signal on the RXOUT output This clock is capable of driving 70 pl plus one LS load with 20 nanoseconds rise and fall times 14 TRANSMIT TX This input which is asserted by the COM 9026 is the serial data transmitted by DATA the node 15 TRANSMIT NAX Thi Tow i bits the TX signal from initiating transmit signals by forc INHIBIT ing PULST ana PULS2 o a high and BL NK a low This signal should be asserted during a power on reset condition SYSTEM CLOCK INTERFACE PINNO NAME SYMBOL J Function 4 CPUCLOCK CPUCLK This output is a4 MHz free running clock capable of driving 130 pf with 30 nano second rise and fall times It is identical to the T TLCLK input when CKSEL is high When CKSEL slow this output becomes the inversion of he signal that is led into the TTLCLK Input 5 CLOCK CKSEL This input selects the clock interface option for the TTLCLK and CPUCLK When SELECT this signal is high both the T TLCLK and CPUCLK are identical 4 MHz free run ning ci which are ted from the 20 MHz input clock OSC via a divide by 5 II divider this input is low the T TLCLK pin an input and the CPUCLK output will produce the inversion of the signal appearing on TTLCLK input 6 TTL CLOCK TILCLK can ba ariar ari it or an output dependin
52. apter 3 Disassembly Introduction This chapter provides the information to remove the top of the 2 100 puter for NET 100 1 Card installation WARNING Dangerous DC voltages are present inside the computer Be sure the line cord is disconnected Disassembly All in One Refer to Figure 3 1 and complete the following steps 1 Unplug the line cord from the AC outlet 2 Using a small flat blade screwdriver move the metal slides all the way to the front and then 1 4 to the back as shown 3 Carefully lift the top case straight up and set it to one side Figure3 1 Disassembly All In One Model Page 3 2 Disassembly Low Profile Model Refer to Figure 3 2 and complete the following steps 1 Unplugthe line cord from the AC outlet 2 Pull the metal slides all the way to the back and then push the metal slides 1 4 to the front as shown 3 Carefuly lift the top case straight up and set it to one side PULL METAL SLIDES ALL THE WAY BACK THEN PUSH FORWARD 174 Figure3 2 Disassembly Low Profile Model Chapter 4 Configuration Introduction This chapter describes the typical factory configuration used with the Z 100 Computer Detailed configuration information is furnished for Z 100 users who desire to modify or customize their configuration and non Zenith Data System microcomputers with S 100 Bus compatiblity Typical Configuration The following is the typical board config
53. ata to NRZ format These functions are performed exactly as the TTL imple mentation shown in figures 1 and 4 Figure 10 illustrates the COM 9032 used with the COM 9026 to implement an ARCNET compatible cable transceiver ARCNET is a registered trademark he Dalapoint Corporation OSYNC TO S163 TO 5163 STOP stop wpe START 2 Rx po o1 62 os 04 es 06 M MII pa 05 06 FIGURE 3 BYTE TO BYTE RECEIVE SYNCHRONIZATION Page 12 5 Data Sheets FIGURE 4 TRANSMIT AND RECEIVE LOGIC Suggested cxcut when using COM9026 without the COM9032 TX 113 01110101 11011 11 FIGURE 5 TYPICAL TX WAVEFORM La FIGURE 6 ARCNET CABLE TRANSCEIVER 4 ARCNET is a registered trademark of the Datapoint Corporation Page 12 6 Data Sheets PULSE2 V V DIPULSE IDEAL ve sas 400 ns FIGURE 7 DIPULSE GENERATION ATA H en i 20MM7 Tuum nnum uv NK ASYNCHRONOUS a os 5026 FIGURE 8 RX WAVEFORM GENERATION Page 12 7 Data Sheets HUB ELECTRONICS Figures 11a and 11b illustrate a typical implementation of active HUB The HUB m
54. ay be thought of as an amplifier and a number ol ideal taps mounted in the same box Each tap is ideal in that it causes no insertion loss no tap loss and provides total suppression ol reflections Each of the ports on the HUB may be connected to a network node to another HUB to an unterminated length of coax or to noth ing at all The reflections caused by connecting an unter minated length of coax is taken into account in the HUB implementation and will not have any negative effects on network operation When no activity appears on the HUB ports the HUB enters the idle state and all receivers are enabled This state corresponds to a clear condition within the octal register which provides disable signals to the transmitters of all ports through the interface modules As soon as any port senses activity portn one of 8 74874 s is clocked low causing the cutput of AND 1 to go low This in turn brings the signal SET to a high which causes the octal register to be clocked through AND 2 The clocking of the octal register causes one output to remain low the one corresponding to the port which sensed activity designated as port n and the other seven outputs to go high This allows port n to transmit repeat its signal to all other ports For each pulse sensed the delay module will generate PULSE T and which is used by all other ports to generate the dipulse as shown in figure 7 The HUB remains in this active state until the transmission it
55. been set by this time ifthe and TMA status bits b00nn100 successful reception of a message 0000c101 lesa than 254 bytes 0001 110 RECON status flag is cleared CLEAR FLAGS I p is a logic 1 the POR status flag is cleared if ris a logic I Ihe All other combinations of written data are not permitted and can result n incorrect chip and or network operation Page 12 25 Data Sheets MAXIMUM GUARANTEED RATINGS Operating Temperature wi 01070 C Storage Tempera 85101506 Lead Temperatur 1 925 C Positive Voltage on any pin 8V Negative Voltage on any pin with respect 10 ground 03V Stresses above those listed may cause permanent damage to the device This is a stress rating only and functional operation of the device al these any other condition above those indicated in the operational sections of this specification is not implied NOTE When powering this device from labaralory or system power supplies it is important thal the Absolute Maximum Ratings not be exceeded or device failure can result Some power supplies exhibit voltage spikes or glitches on their outputs when the AC power is switched on and off In addition voltage transients on the AC power line may appear on the DC II this possibility exists itis Suggested that clamp be used DC ELECTRICAL CHARACTERISTICS 0 to 70 C Vec 5 0V 5 PARAMETER MAX UNITS
56. cription Phantom The other two outputs from U107 PHANTOM1 pin 18 and PHANTOM2 pin 15 are tied together When MEMADRS1 MEMADRS2 and a write cycle occur PHANTOM2 goes low In this way the NET 100 1 board maps over ROM Read Only Memory space in the main system Wait Generation At the beginning of every bus cycle refer to Figure 9 2 the BSYNC pulse is fed to the preset lines PR pins 4 and 10 of flip flop U139 forcing the Q output pin 9 high and the Q output pin 8 low The outputs remain in this state until the clock toggles the low in at U139 2 BSYNC IOADRS OR MEMADRS WAIT ARMWAIT RDY Figure9 2 Timing Diagram Page 9 5 Circuit Description U139 8 ARMWAIT is connected to U121 8 The other input of the NOR gate 0121 9 is IOADRS The output U121 10 is high if this board and have been selected When this occurs and bus status line BINP or BOUT generated by U136 3 is high U131 3 RDY is low causing wait states to be inserted in that bus cycle until ARMWAIT goes high U139 9 ARMWAIT is connected to U142 13 The other input to this gate is MEMADRS When both MEMADRS1 and MEMADRS are low U121 4 goes high causing MEMADRS to be selected and U142 11 to be high U131 6 RDY is low if U142 11 and U131 4 BINP or BOUT or BMEMR are high In effect when or memory accesses occur on the NET 100 1 board RDY is forced low When U116 is ready the WAIT sig
57. ct able on 2K boundaries Network Controller The network controller provides the necessary interface between the S 100 Bus and the network It controls waits interrupts and data to and from the system ID Number The ID number is a unique number from 1 to 255 given to every node unit in the network Physically set by an onboard switch it serves to identify where a message is generated where the message is being sent and the priority that unit has Active Hub The active hub decodes and encodes the incoming and outgoing mes sages The hub allows implementation of a small network without any external hardware through the available three ports The fourth port is dedicated to the network controller no external connection may be made to it Chapter 9 Circuit Description Introduction This chapter provides a detailed circuit description of the NET 100 1 Card Refer to the schematic diagrams for the following discussion Bus Buffers U101 U102 U108 and U111 are the address bus buffers U103 is the buffer for the data out DO0 DO7 bus data received from the S 100 U104 is a buffer for the data in 00 017 bus data going out to the S 100 Bus U104 is enabled by DBIN and REQ U108 and U127 are buffers for the control signals Multiplexers multiplexers U112 and U118 select data transfers between the bus and the RAM or the network controller COM9026 Interface U116 First output data to U116 th
58. data or rom the RAM buffer This signal is sampled Internally on the falling edge o AS 7 READ WRITE RW high level on this the processor s access cycle to the COM 9026 or the A low tevel indicates that write cycle will be performed to either Ihe or the COM 9026 The write will not be completed however until inputis asserted This signal is an internal transparent latch gated with AS 10 ADDRESS 5 sample the stale of the IOREG STROBE and 9026 bus arbitration Is initiated on Ihe falling 4 REQUEST REG ETE or memor cycle has been s sampled The signal 5 REG o REG internal transparent latch gated with AS 12 WAIT WAIT This output signal is asserted by the 9026 at the start of a processor access cycle to indicate that it is not ready to transfer data WAIT returns to its i state when the COM 9026 is ready tor the processor to complete its cycle 5 DELAYED BWA This input signal informs the 9026 that valid data is present on proces WRITE sor s data bus lor write cycles The COM 9026 will remain n the WAIT state until 115 signal is asserted DWA has no effect on read cycles II Ihe processor is able 10 satisty the wnle data setup time it is recommended that this signal be grounded 29 INTERRUPT INTA _ This output signal is a
59. e OFF 1 position and all others to the ON 0 position as shown Refer to appendix A for cross reference to other ID numbers and their respective positions POSITION 0 1 2 3 4 5 6 7 ON OFF ON OFF OFF ON ON OFF ON ON NOTE To insure proper setting refer to memory test in Chapter 6 DipSwitch SW106 all positions to the ON 0 position DipSwitch SW107 all positions to the ON 0 position Page 4 3 Configuration Detailed Configuration Data The following information is furnished to configure the NET 100 1 Card for non Zenith Data System S 100 Bus compatible microcomputers as well as for the Z 100 user who desires to make modifications or effect acustomized configuration CAUTION This product contains ESDS electrostatic sensitive devices Exercise normal caution in handling these devices to prevent static dis charge damage Refer to Figure 4 2 for the locations of the jumpers Figure 4 2 Configuration Jumpers Page 4 4 Configuration Jumpers J101 Selects the interrupt on the S100 Bus Only one of the following should be jumpered NMI INT 4 9105 For 16 bit addressing pins 1 and 2 jumpered for 8 bit addres sing pins 2 and 3 are jumpered J107 T2 Jumper pins 2 and 3 for normal COM9026 operation When pins 1 and 2 are jumpered chip level testing can be performed J108 T1 Jumper pins 2 and 3 for nor
60. e and the transmitter passes the token Onceit has been established that the receiving node can accept the packet and trans mission is complete the receiving node will verity the packet Page 12 18 Data Sheets the packet is received successfully the receiving node transmits an acknowledge message nothing if it is received unsuccessfully allowing the transmitter to set the appropriate status bits to indicating successful or unsu cessful delivery of the packet An interrupt mask permits the COM 9026 to generate an interrupt to the processor when selected status bits become true Figure 3 is a flow chart illustrating the internal operation of the COM 9026 NETWORK RECONFIGURATION A significant advantage of the COM 902615 its ability to adapt to changes on the network Whenever a new node 5 acti vated or deactivated a NETWORK RECONFIGURATION is performed When a new 9026 is turned on creating new active node on the network or if the COM 9026 has not received an INVITATION TO TRANSMIT 840 milli seconds it causes a NETWORK RECONFIGURATION by sending a RECONFIGURE BURST consisting o eight marks and one space repeated 765 times The purpose of this burst is to terminate all activity on the network Since this burst is longer than any other type transmission the burst will interfere with the next INVITATION TO TRANSMIT destroy the token and keep any other node trom assuming control of the line It also
61. ed ID number Refer to appendix A for number selection and conversion All of the information needed to use the features of the NET 100 1 Card is contained within this manual Please read it carefully before attempting to use the NET 100 1 Card Page 1 2 Introduction Network Operation ZLAN consists of a token passing scheme where each node unit passes to the next active higher ID number an invitation to transmit Up to 255 unique node numbers may be assigned to a ZLAN network refer to Figure 1 1 Figure 1 1 ZLAN Topology Page 1 3 Introduction Refer to Figure 1 1 for the following example EXAMPLE Node 4 desires to communicate to node 20 The interconnect ing nodes must be powered on because the board has an active hub Nodes 2 3 4 7 11 12 16 17 18 19 and 20 The network can be configured in two ways Each has advantages and disadvantages which depend on the system to be installed For the highest efficiency network determine which configuration is best for the system Figure 1 2 shows a daisy chain configuration The main advantage of this configuration is that a unit may be easily inserted into the system keeping cable runs at a minimum The disadvantage of this system is that all units must be powered on for communications to occur For example a network system is set in a company where 5 of 20 units are at times inaccessible to the other users Using a daisy chain config uration the ent
62. en ordering a replacement part Page 11 2 Parts List Replacement Parts NET 100 1 Network Card NET 100 1 Card is Part Number 181 4638 1 Refer to Figure 11 1 to identify replacement parts CAUTION This board contains ESDS Electrostatic Sensitive devices Exercise extreme care in handling these devices to prevent damage NOTE Refer to the Semiconductor Identification section of this chapter or Chapter 12 Data Sheets for description of semiconductor devices LPO NE EM ZENITH DATA SYSTEMS 85 2953 1 092683 Figure 11 1 Component View NET 100 1 Card Page 11 3 Parts List CIRCUIT CIRCUIT REFERENCE ZDS REFERENCE ZDS DESIGNATOR PARTNO DESCRIPTION DESIGNATOR PARTNO DESCRIPTION Capacitors C141 HE 25 195 2 2 F tantalum C142 HE 21 769 01 pF ceramic HE 21 769 01 pF ceramic C143 Not Used C102 HE 21 769 01 ceramic 144 Not Used C103 HE21 769 01 pF ceramic C145 HE 21 769 01 uF ceramic C104 HE 21 769 01 pF ceramic C105 HE 21 769 01 pF ceramic C148 HE 21 769 01 ceramic 147 Used C106 HE 21 769 01 pF ceramic C148 HE 21 769 01 pF ceramic C107 HE 21 769 01 pF ceramic C149 21 769 101 pF ceramic HE 21 769 01 pF ceramic C150 Not Used C109 HE 25 195 2 2 pF tantalum C151 HE 21 173 2200 pF ceramic 25 195 2 2 pF tantalum Diodes 6111 21 769 01 p
63. eption is already underway reception ENABLE TRANSMIT FROM PAGE nn This command prepares the COM 9026 to begin a transmit sequence RAM butter page nn the next time it receives the token When this command is loaded the TA and TMA bits are set to a logic 0 The TA bitis set to a logic one upon completion of the transmit sequence Tha TMA bit wil 9026 has received an acknowledgement from the destination COM 9026 This acknowledgement is strictly hardware level which is sent by the receiving COM 9026 before its controlling processor is even aware of message reception It is alsa possible for this acknowledgement to get lost due to line errors etc This implies that the TMA bit is not a guarantee of proper destination reception Refer to figure 3 for details of the transmit sequence and its relation to the ENABLE RECEIVE TO PAGE nn This command allows the COM 9026 to receive data packets into RAM buffer nn and sets the RI status bit to a logic zero II b is a logic 1 the COM 9026 will also receive broadcast transmissions A broadcast transmission is a transmission ta ID zero The RI status bit is set to a logic one upon DEFINE CONFIGURATION II c is a logic 1 the COM 9026 will handle short as well as long packets itc is a logic 0 the COM 9026 will only handle short packets WRITTEN DATA COMMAND 00000000 reserved for luture use 00000001 00000010 will run to its normal conclusion 000 011 have
64. et Figure 13 illustrates the RAM buffer format for a message of length 120 78 HEX from ID 4 HEX to ID B2 Note that address 02 of the selected page contains the 25 complement of the number of data bytes in the message Figure 14 illustrates the RAM buffer format for a message of length 300 12C HEX long packet from ID 2F to ID D8 Note that address 02 must contain all zeros with address 03 equal to the 25 complement of the number of data bytes in the message The 28 complement for long packets is calculated with respect to 512 but only 8 bits are used in RAM buffer address 03 The COM 9026 wil keep track of the 9th bit internally The RAM buffer is arranged such that the last data byte wil always reside in address 255 FF HEX for short packets and address 511 HEX for long packets Broadcast messages will be transmitted if address 01 is set to 00 Once the buffer is loaded the processor must wait for the TA status bit to become a logic one The TA bit informs the processor that a previous transmit command has con cluded and another transmit command can be issued Each time the message is loaded and a transmit command issued itwill take a variable amount of time before the message is transmitted depending on the traffic on the network and the location of the token at the time the transmit command was issued Typically the conclusion of the transmit command which is flagged when TA becomes logic one generates an i
65. fined as line activity and a logic 1 is defined as a pulse of 200 nanoseconds dura tion A transmission starts with an ALERT BURST consisting 018 unit intervals of mark logic 1 Eight bit data characters are then sent with each character preceded by 2 unit intervals of mark and one unit interval of space Five types of transmis sion can be sent as described below Invitations To Transmit An ALERT BURST followed by three characters an EOT end of transmission ASCII code 04 HEX and two repeated DID Destination IDentification characters This message is used to pass the token from one node to another Free Butter Enquiries An ALERT BURST followed by three characters an ENQ ENQuiry ASCII code 05 HEX and two repeated DID Destination IDentification characters This message is used to ask another node if it is able to accept a packet of data Data Packets ALERT BURST followed by the following characters SOH start of header ASCII code 01 HEX SID Source Dentification character repeated DID destination Dentification characters a single COUNT character which is the 23 comple ment of the number of data bytes to follow if a short packet is being sent or 00 HEX followed by a COUNT character which is the 2 s complement o the number ol data bytes to follow II a long packet is being sent N dala bytes where COUNT 256 N 512 N for a long packet two CRG Cyclic
66. for at least 100 milliseconds 2 The CLK input must run for at least 10 clock cycles before the POR input is removed 3 While POR is asserted the CA input may be running or held high If the CA input is running POR may be released asynchronously with respect to CA If he CA input is held high POR may be released before CA begins running During POR the status register will assume the following state BIT 7 RI setto a logic 1 BIT 6 ETS2 not affected BIT 5 ETS not affected BIT 4 POR set to logic 1 BIT 3 TEST set to alogic 0 BIT 2 RECON set to a logic 1 set to logic TA set to a logic In addition the DSYNC output is reset inactive high and the interrupt mask register is reset no maskable interrupts enabled Page 00 Is selected for both the receive and the transmit RAM buffer After the POR signal is removed the COM 9026 will generate an interrupt the nonmaskable Power On Reset interrupt The COM 9026 will start oper ation four CA clock cycles after the POR signal is removed At this time the COM 9026 after reading ID from the external shift register will execute two write cycles to the RAM buffer Address 00 HEX will be written with the data D1 HEX and address 01 HEX will be written with the ID number as previously read from the external shift register The processor may then read RAM buffer address 01 to determine the COM 9026 ID It should be
67. g on the state of the CKSEL input When CKSEL is high a free clock is ouput When CKSEL Is low the becomes an input which drives an inverter that feeds the CPUCLK output 7 OSCILLATOR OSC __ This input requires a 20 MHz clock 9 LOCAL AREA LANCLK This output wil supply the ree running 5 MHz cock 10 ne COM 9026 19 M eroek capable of driving 70 pf plus one LS load with 20 nanoseconds rise and fall times 8 GROUND GND Ground 16 5 VOLT Vex Power Supply SUPPLY FUNCTIONAL DESCRIPTION Transmit logic refer to figures 2 and 4 The COM 9026 when transmitting data on TX will pro duce a negative pulse of 200 nanoseconds in duration to indicate a logic 1 and no pulse to indicate a logic Retering to figure 4 a 200 nanosecond pulse on TX is con verted to two 100 nanosecond nonoverlapping pulses shown as PULS1 and PULS2 The signals PULS1 and PULS are used to create a 200 nanosecond wide dipulse by driving opposite ends of the AF transformer shown in gure 2 Receive logic refer to figures 2 and 5 As each dipulse appears on the cable it is coupled through the RF transformer passes through the matched fitter and feeds the 75108B comparator The 75108B pro duces a positive pulse for each dipulse received from the cable These pulses are captured by the COM 9032 and are converted to NRZ dala with the NRZ data bit boundaries being delayed by 5 OSC clock periods as shown in figure 5 As each by
68. half art PAIS s US ADURXFROCESSORWEWEDAR E RW I COM 5026 Hr ADO 895 Qe Y gt WAIT aM e aa er LER 4i TE FIGURE 5 COM 9026 WRITE RAM FOLLOWED BY PROCESSOR WRITE RAM Page 12 22 Data Sheets CLK interval 5C figure 5 illustrates this situation then the cycle will always start at half CLK interval The uncertainty is introduced when the processor request occurs during half CLK intervals 6C 7C or BC In this case the processor cycle will start between 200 and 500 nanose conds later depending on the particular timing relation between AS and CLK The maximum time between pro cessor request and processor cycle start which occurs when the processor request comes just after COM 9026 request is 1300 nanoseconds It should be noted that all times specified above assume a nominal CLK period of 200 nanoseconds Figures 6 and 7 illustrate timing for Processor Read COM 9026 and Processor Write COM 9026 respectively These cycles are also shown divided into B half clock intervals 1P through 8P and can be inserted within figures 4 and 5 If these processor cycles occur POWER UP AND INITIALIZATION The COM has the following power up requirements 1 The POR input must be active
69. he time it takes the token to make a round trip through the network it will indicate one of three situations 1 The nade is disconnected from the network 2 There are na other active nodes on the network 3 The external receive circuitry has failed These situations can be determined by using another soft ware timeout which is greater than the worst case time for around trip token pass which occurs when all nodes trans mit a maximum length message It should be noted that each node upon packet trans mission ignores the value of the SID in the buffer and instead inserts the ID number as specified by the external switches Packet Reception To enable the receiver for packet reception the processor selects a page in the buffer to use and waits for the Al status bit to become a logic one The Al bit informs the processor that a previous RECEIVE command has concluded and another RECEIVE command can be issued Each time a receive command is issued the reception can take vari able length of time since there is no way ol telling when another node will decide to transmit a message directed at this node The RECEIVE command will reserve a particu lar page memory in the RAM buffer for reception Only the successful reception of a packet or the issuing of a DIS ABLE RECEIVE command wil set the RI bit to a logic one thus freeing up the page in the RAM buffer for processor accesses ADDRESS DATA 00 46 01 B2 02 88 10
70. ic 0 The bit boundaries are spaced at 400 nanosecond intervals establishing the 2 5 M bit data rate The COM 9026 when transmitting data on TX will produce a negative pulse of 200 nanoseconds in duration to indicate a logic 1 and no pulse to indicate a logic 0 Figure 5 illustrates a typical data transmission The CABLE TRANSCEIVER function is first to can vert the 200 nanosecond TX pulses output by the COM 9026 to a format consistant with the transmission media and net work topology and second to convert signals from the cable to the NAZ data required by the COM 9026 s RX input Starting with the TX and RX signals many different cable transceiver implementations can result to allow for broad bandorbasebandnetworks using twisted pair coax or fiber optics as the transmission media Figures 4 and 6 illus trate a typical CABLE TRANSCEIVER used to implement Datapoint s local area network The ARCNET implementation uses a baseband system with RG62 93 ohm coax Referring to figure 4 200 nanosecond negative pulse on TX is converted to two 100 nanosecond negative pulses shown as PULSE 1 and PULSE 2 These two signals are used to create a 200 nanosecond wide dipulse signal by being driven into opposite sides of RF transformer T1 and finally coupled onto the coax as shown in figure 6 re7 shows the timing relationship between 1 and PULSE 2 The waveform of the resultant dipulse is also shown in figure 7
71. ilable U124 1 1 only from 20 MHZ crystal Zenith Data Systems oscillator or Heath Company PIN B V00 OUTPUT DESCRIPTION Page 11 9 Parts List LEAD CONFIGURATION HEATH MAYBE PART REPLACED TOP VIEW NUMBER WITH 412 654 Available D102 through D109 only from Light Emitting Zenith Data Systems Diode LED or Heath Company CATHODE 442 665 79105 9143 5V Voltage regulator iis w 442 702 1 2 U113 U114 5V Voltage regulator 443 26 74500 1126 0133 Quad 2 input NAND 443 752 74L5175 VII9 Quad D type CLEAR 1Q 10 10 20 20 20 GN Page 11 10 Parts List HEATH MAYBE DESCRIPTION LEAD CONFIGURATION PART REPLACED TOP VIEW NUMBER WITH IV 2A4 2 24 1 2 2 IYA LI 19 18 1 16 15 14 n 12 I 443 791 74L8244 V102 U103 H G f 0109 127 Noninverting 3 state output octal buffers c AFEA I LI LI 1 MI 2V4 142 22 1 IM om Vec CONTROL A JY 443 802 7415257 U112 U118 or or Quad 2 input ay EJ 443 1178 74ALS257 state 5 multiplexer enan y 9 wes
72. ime is bounded by the time it lakes the token to make a round trip through each node on the network This time is a function of the number of nodes on the network the traffic activity and the number of bytes transmitted in each message There are also some delay times that are intrinsic to the COM 9026 contributing to this wait time The COM 9026 will perform a simple token pass it receives the token has nothing to transmit and passes the token to the Next ID in approximately 28 microseconds Therefore the best time for a round trip token pass to each node can be expressed as follows Tb 28N microseconds where N equals the number of nodes on the network When a particular node receives the token and has a message to transmit the COM 9026 introduces an additional time of 113 microseconds plus 4 4 microseconds tor each byte trans mitted in the message Therefore the worst case time for a round trip token pass which exists when each node on the network has a message to transmit can be expressed as follows Tw Tb 113 4 4B N microseconds where B equals the average number of bytes sent per mes sage Combining terms the wail time is bounded by the following equation 28N lt Twalt lt 141 4 4B N microseconds In a typical network consisting of 10 nodes with an average message length of 100 bytes will fall between 280 microseconds no messages sent and 5 81 millisec onds when 10 nodes send 100 by
73. in which all token passes are acknowledged by the node accepting the token The token passing network scheme avoids the fluctuating channel access times caused by data collisions in so called CSMA CD schemes such as Ethernet The COM 9026 circuit contains a microprogrammed se quencer and all the logic necessary to control the token passing mechanism on the network and send and receive data packets at the appropriate time A maximum of 255 nodes may ba connected to the network with each node being assigned a unique ID The COM 9026 establishes the network configuration and automatically re configures the network as new nodes are added or deleted from the network The COM 9026 per forms address decode CRC checking and generation and packet acknowledgement as well as other network man agement functions The COM 9026 interfaces directly to the host processor through a standard multiplexed address data bus Anexternal RAM buffer ol up to 2K locations is used to hold up to four data packets with a maximum length of 508 bytes per message The RAM buffer is accessed both by the pro cessor and the COM 9026 The processor can write com mands to the COM 9026 and also read COM 9026 status The COM 9026 will provide all signals necessary to allow smooth arbitration of all RAM buffer operations is a registered trademark of tha Datapoint Corporation Page 12 15 Data Sheets RECONFIGURATION IMER PROGRAM COUNTER
74. ire system will not be able to communicate if any unit is powered down Without access to 5 computers those physical lines must be bypassed if this is even possible for the network to communi cate This is an undesirable situation which can be avoided by using the tree configuration Figure 1 3 shows a basic tree configuration Set up in branches this con figuration does not require all systems to be powered on for communication to occur just the individual branch must be active The main disadvantage is that the tree configuration does require prethought on wiring Possible future sites should be taken into consideration while connecting the sys tem when using the tree configuration In the tree configuration the unaccessible 5 computers can be set in a separate branch allowing the network to communicate without these units powered on Although these configurations may look unique the logical network is the same as shown in Figure 1 4 Do not connect the network in this manner Use only a daisy chain or tree configuration Page 1 4 Introduction SYSTEM OPTIONAL ARCNET SYSTEM ARCNET 4 SYSTEM Figure 1 2 Daisy Chain Configuration Page 1 5 Introduction ARCNET SYSTEM ARCNET ARCNET ARCNET ARCNET ARCNET ARCNET ARCNET SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM SYSTEM Figure 1 3 Tree Configuration Page 1 6 Introduction Figure1 4 Logical Network
75. is repeating is finished Atthis time it returns to the idle stale The determination of when a transmission is finished is based on time There are never more than nine consec utive spacing elements in a transmission the start element and eight zeros Therefore a dipulse is received at least once every ten unit intervals 4 microseconds The COM 9026 has a turnaround time somewhat greater than 12 microseconds so there will be at least a 12 microsecond interval of no activity between the end of the last data ele ment of one transmission and the start of the alert burst of the next transmission Were it not for the potential reflection problem caused by an unterminated or unconnected length of coax the HUB could drop back into the idle state when the receiver has not heard anything for same period of time between 4 and 12 micraseconds In order to provide protection against reflections the HUB should not back into the idle state until any and reflections cease For individual runs of coax not greater than 2000 feet RG62 coax a reflection from shorted unterminated cable will return in less than 4 9 microsec onds Changing the 4 microsecond III to 4 9 microsec onds will allow the HUB and the network to be unaffected by reflections For the duration of the packet retriggerable one shot OS1 will never fire The 5 5 microsecond duration 01051 will determine when a packet transmission has con cluded by sensing a
76. ister bit is set to a logic one allowing transmitter interrupts to occur when the TA bit gets set to a logic one the interrupt is simultaneously generated In order to clear the interrupt and prevent repeated servicing of the same interrupt either another transmit command should be loaded if there is another message ready to be transmitted which will reset the TA bit to a logic zero ar bit zero of the interrupt mask register should be reset to a logic zero During reception the INT output is generated by the logic function RI anded with bit 7 of the interrupt mask reg ister Assuming the mask register bit 7 is set to a logic one allowing receive interrupts to occur when the RI bit gets set to alogic one an interruptis simultaneously generated As for the transmitter the interrupt should be cleared during the interrupt service routine The clearing of the interrupt is accomplished by either issuing another receive command page in the RAM buffer has been freed up to accept a new data packet or by resetting bit 7 of the interrupt mask register to a logic zero Network Performance The most important parameter used to measure perfor mance in local area network is the amount of time a node has to wait before being able to send a message This ADDRESS DATA Page 12 11 Data Sheets parameter actually denotes the number of messages per second leaving each node In the token passing scheme used by the COM 9026 this wait t
77. ll directly feed the RX input of the COM 9026 pin 38 During transmission the COM 9032 converts the transmit data from the 9026 TX pin 37 into the wavelorms necessary to drive opposite ends of the rf transformer used in the ARCNET cable electronics shown in figura 2 FIGURE 1 Pes nA is a registered trademark ol the Datapoint COM 9032 BLOCK DIAGRAM L poration Page 12 31 Data Sheets FIGURE 2 TYPICAL COM 9032 INTERCONNECT Page 12 32 Data Sheets DESCRIPTION OF PIN FUNCTIONS Rafer to figure 2 COM 9026 INTERFACE PINNO NAME SYMBOL FUNCTION 1 2 PULSE 2 PULST are Sv jative pulses which occur ever PULSE 1 PULS1 time tho FA nputis pulsed PULS2 and 1 are led to feed an external 3 driver as shown in figure 2 When used with the circuitry shown in figure 2 this output shouid be left uncon nected The timing of this signal is shown in figure 4 BLANK BLNK 10 MM This inputis the recovered receive dala trom the network For each appear the network comi shown in figure 2 wi luce a 2 ithe pulse which directly feeds this I RXOUT This output is the NAZ data generated as a function of the RXIN pulse waveform u gt OUT which directly feeds the AX input of the COM 9026 pin 38 32 DELAYED DSYNC This active low input which is asserted by the COM 9026 VIII h
78. lustrates the relationship of the DSYNC CA and RX signals before dur ing and after CA synchronization The technique used for synchronization is similar to that 0 standard asynchronous protocols where a sample point within an asynchronous signal Is found and used for each byte transmitted Traditionally a 16X or 64X clock is used to provide the resolution needed to find the proper sample point for low frequency transmission Because of the 2 5 M bit rate provided by Ihe COM 9026 a 2X clock the CA sig nal is used in conjunction with an external 8X clock 20 MHz to allow determination of a reliable sample point It should be noted that the DSYNC output can never become active low during a COM 9026 transmission At the end of a transmission the COM 9026 will wait about 6 microseconds By this time the line should be quiet and the RX input will be sitting in a space low condition At this lime the COM 9026 will wait for the RX input to become high level sensitive not edge sensitive which occurs dur ing the alert burst of the next transmission At this time the COM 9026 starts reception by lowering the DSYNC signal FIGURE 1 CLOCK GENERATION Suggested circuit when using the 9026 without iha COM9032 Page 12 4 Data Sheets CABLE TRANSCEIVER The circuitry of figure 1 andthe COM 9026 assume the data appearing on the RX signal is NRZ with a high level indi cating a logic 1 and a low level indicating a log
79. mal COM9026 operation When pins 1 and 2 are jumpered chip level testing can be performed J109 ECHO Jumper pins 1 and 2 for normal COM9026 operation When pins 2 and 3 are jumpered COM9026 will retransmit all messages less than 254 bytes J110 4111 These two jumpers specify the time out durations as follows ET2 ET1 RESPONSE RECONFIGURATION TIME us TIME ns 1 1 74 7 840 1 0 283 4 1680 0 1 561 8 1680 0 0 1118 6 1680 Page 4 5 Configuration J112 When using a 27128 ROM jumper pins 2 and 3 For other size ROM s jumper pins 1 and 2 J113 When using a 2732 ROM jumper pins 1 and 2 For 2764 27128 jumper pins 2 and 3 J114 When pins 2 and 3 are jumpered the EPROM will not cause PHANTOM to be active When pins 1 and 2 jumpered will be active when the ROM is selected J115 When using a 2732 ROM jumper pins 2 and 3 For a 27128 jumper pins 1 and 2 For a 2764 no jumper is required Switches Refer to Figure 4 3 for the location of the switches In the following config urations OFF equates to a logic 1 and ON to a logic 0 swo E57 ES EI Figure4 3 Configuration Switches Page 4 6 Configuration SW101 This switch in conjunction with SW106 selects the memory address location for the RAM For example to select the address 0F000 HEX SW101 would have the following configuration POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT 23 22 21
80. move the hole plug buttons which cover these holes and discard them 2 Carefully sand or scratch the paint off the back panel from the two outermost screw holes 3 Place chassis adapter over these holes and feed the cables through the holes to the inside of the unit 4 Using two HE 250 1434 6 BT x 375 self tapping screws fasten the chassis adapter to the rear panel 5 Connect the cables fed to the inside of the unit to the NET 100 board connectors P101 P102 and P103 The connector has three pins but only two contacts are used The outer pins contain the same signal and the contact may be installed either way as long as the middle pin makes contact with the middle connector This completes the installation of the network chassis adapter To connect nodes together RG62 coaxial cable can be run through ceilings on floors or along the walls For shorter delays and less cabling keep long runs to a minimum CAUTION Since other installations may use similar cable and connectors be sure the correct connectors and cabling are connected to the Network Chassis Adapter Damage to this board may result if improper connections are made Chapter 6 Initial Tests Introduction This chapter contains three initial tests to make sure the NET 100 1 Card is properly operating and interfaced to the system The three tests are RAM I 0 and Memory NOTE These tests are interrupted by pressing the CTRL and RESET keys simultaneously
81. nal becomes inac live going low WAIT is inverted at U133 11 clocking a low to the D Input pin 12 of 0139 U139 is clocked by synchronizing WAIT to the S 100 Bus timing ARMWAIT goes low forcing RDY high and ending the wait state Page 9 6 Circuit Description ROM Circuitry The ROM circuitry is independent from the network controller circuitry It does not generate any wait states nor does it rely on the wait states from the network controller to operate properly After onboard buffering the ROM circuitry operates as if it were a separate board within the unit U106 U108 U109 U130 U131 U133 U136 U140 SW102 and SW104 comprise the circuitry for the ROM U117 U106 and U130 are com parators which check the address set by SW102 and SW104 When the address at SW102 is the same as that from the address bus the output U106 19 goes low U106 19 is connected to the input of U130 If both addresses check ROMSEL goes low enabling the ROM U117 20 The addresses 0 12 required for 0117 are taken from the buffered address bus Depending on the memory type used A13 may also be connected through J115 pins 1 and 2 Figure 9 3 illustrates the ROM insertion for the memory type used and Table 9 1 lists the jumper config uration for the selected ROM M 2732 2 Figure 9 3 ROM Insertion Page 9 7 Circuit Description Table 9 1 ROM Jumper Contiguration TYPE JUMPER
82. nerate CA and CLK pins 13 and 9 for U116 pins 2 and 19 CLK is also used by U132 to clock the ID number to 0116 U123 also serves as an interface between the incoming outgoing pulses on the interface modules IM101 through IM103 and RX and TX on U116 TX U116 37 is converted by U123 to PULS2 Incoming signals RXIN are converted by U123 to RXOUT which is connected to RX on the U116 38 ID Number When power or a keyboard reset is applied to the system U116 reads the ID number from U132 The hardware is capable of selecting an ID number from 1 to 255 which is physically set by the user by SW105 The ID number is present at the parallel inputs of U132 pins 2 3 4 5 10 11 12 and 14 When U116 sends IDLD ID Load and CLK to U132 the chip outputs the data in serial form to U116 34 IDDAT ID Data In 0116 stores the ID number in RAM location 01H The specific location in the Z 100 is F000 01H The following switch setting designates ID number 100 64H SW105 POSITION 0 1 2 3 4 5 6 7 ON OFF ON OFF OFF ON ON OFF ON ON Page 9 10 Circuit Description Active Hub At initial power up of the system U125 9 is momentarily held low by the network R101 and C134 for 0 22 seconds After being gated through U125 U141 and U142 this signal becomes PRSFF PRSFF initializes the flip flops 0120 and U129 so that the Q outputs are high and remain in that state until data from the network or this board pulses in
83. nterrupt While waiting for the interrupt to occur the pro cessor can load another page in the RAM buffer with the next message to be sent in anticipation of the transmitter becoming available TA becomes a logic one In this way double buffering is accomplished by loading a second mes sage while the first message is being transmitted The interrupt will then allow the software to time the repeated issuing of transmit commands Before a message is transmitted the destination node is asked if it is able to receive the message a FREE BUFFER ENQUIRY transmission This 15 done automati cally by the COM 9026 with no software intervention II the destination node is not servicing its COM 9026 for what ever reason the receiver at the destination node will be inhibited RI set to a logic one and the source node will never be able to deliver the packet and set the TA bit ta a logic one Because of this there should be a soltware timeout on the TA bit When the timer times out the processor should disable the transmitter which forces the COM 9026 to abandon the transmission and causes the bit to set to logic one when the node next receives the token II the source node attempts to transmit a packet to a nonexistent node the packet will never be delivered but the TA bit will always be set to a logic one In this situation the TMA bit will never get set If the disable transmitter command does not cause the TA bit to be set in t
84. o 60 duly cycle on CLK Al times are measured irom the 50 point of the signals FIGURE 10 CLK CA AC CHARACTERISTICS Page 12 27 Data Sheets FIGURE 11 PROCESSOR ACCESS SYNCHRONIZATION H t START OF PROCESSOR ACCESS CYCLE FIGURE 13 PROCESSOR WRITE RAM AC TIMING Page 12 28 Data Sheets VALID 9026 ADDA FIGURE 16 9026 WRITE RAM TIMING Page 12 29 Data Sheets cxf f lt 5 eo w PROCESSOR ADDA 9026 DATA OUT 4 FIGURE 17 PROCESSOR READ COM 9026 AC TIMING 26 A070 PROCESSOR ADDA HE hy is ADIE FIGURE 19 10 INPUT AC TIMING STANDARD MICROSYSTEMS diagrama products eludes as a means ol I semiconductor applica consequenily complete inlormalion sulliciemt for tunstrueton purposes nol necessarily given The CORPORATION intonation has been carelully checked and is believed to be enrely tahanie However responsibilty for inaccuracies Furthermore such inlarmatron nat convey a purchaser ol Ihe semicangue lor devices described any license under he pateni rights SMG ar otners reserves the righi to make changes SS Marcus Hauppauge NY 788 56273 00 21 any lime In order to improve design and supply the best product po
85. propagation delay between nodes the number of nodes on the network and the highest ID number on the network Figure 17 is a graph illustrating the reconfiguration time as a function of the number of nodes on the network and the highest ID number and shows a range of 21 to 61 milliseconds The reconfig uration time shown assumes no cable propagation delay The reconfiguration time has no long lasting effect an the system performance and will only increase the lime of a single token pass by the actual time of reconfiguration 101 ANO eer ESTO Z s p FIGURE 17 NETWORK RECONFIGURATION TIME Similarly when a node is deactivated the node that usually passes the token will have to continually try lo pass the token to the next highest ID The time it takes for a node to pass the token and find the next active node is a function ofthe difference ID numbers of the deactivated node and the next highest active node For example if node 3 passes to node 10 and node 10 passes to node 20 and if node 105 deactivated then node 3 will issue an INVITATION TO TRANSMIT to nodes 10 11 12 elc and finally node 20 where it will detect line activity and complete the token pass In this example node 43 will issue eleven INVITA TION s TO TRANSMIT all but the last one taking 93 6 microseconds see appendix 1 TOKEN PASS with no response before finally finding activity at node 20 In thi
86. propriate buffer size is specified in the DEFINE CONFIGURATION command When tong pack ets are enabled the COM 9026 will interpret the packet as along or short packet depending on whether the contents FIGURE 8 ADORESS FORMAT RAM BUFFER Y CONFIGURATION no COUNT 256 N DATA BYTE Y 2 DATA BYTE DATA BYTE N NOT uien SHORT PACKET 1256 512 BYTE Pace of buffer Jocation 02 is zero or non zero During a receive sequence the COM 9026 stores data in the receive buffer also a 256 or 512 byte segment of the RAM buffer The VO command which enables either the COM 9026 receiver or the COM 9026 transmitter also initializes the respective buffer page register The formats of the buffers both 256 and 512 byte are shown below ADDRESS FORMAT 0 E 2 3 COUNT N Not 0860 DATA BYTE Y N DATA PACKET LENGTH DATA BYTE 2 SI SOURCE ID DIO DESTINATION ID e 10 FOA BROADCASTS DATA BYTE N t DATABYTE N LONG PACKET 1512 BYTE PAGE The ID set by the external switches is continually sampled during COM 9026 operation ID refers to the identification number assigned to this node 2 NID refer to the next identification number receiving tokan from tha ID DID destination identification start of header character proceeds all data packets FIGURE 3 9026 OPERATION Page 12 19 Data Sheets Page 12 20 Data Sheets PROCESSOR INT
87. provides line activity which allows the COM 9026 sending the INVITATION TO TRANSMIT 10 release control of the line When COM 9026 sees an idle line for greater than 78 2 microseconds which will only occur when the token is lost each COM 9026 starts an internal time out equal to 146 microseconds times the 255 minus its own ID lt also sets the internally stored NID next ID representing the next possible ID node equal to its own ID If the timeout expires with no line activity the COM 9026 starts sending INVITATIONS TO TRANSMIT with the DID equal ta the currently stored NID Within a given network one COM 9026 will timeout the one with Ihe highest ID number After sending the INVITATION TO TRANSMIT Ihe COM 9026 waits for activity on the line If there is no activity for 74 7 microseconds the COM 9026 increments the NID value and transmits another INVITATION TO TRANSMIT using the new NID equal to the DID If activity appears before the 74 7 microsecond timeout expires the COM 9026 releases con trol of the line During NETWORK RECONFIGURATION INVITATIONS TO TRANSMIT will be sent to all 256 possi ID s Each COM 9026 on the network will finally have saved a NID value equal to the ID of the COM 9026 that assumed control from it From then until the next NET WORK RECONFIGURATION control is passed directly from one node to the next with no wasted INVITATIONS TRANSMIT sent to ID s not on the network
88. quates to a logic 1 and ON to a logic 0 SW107 POSITION 0 1 2 3 4 5 6 7 ADDRESS BIT AQ 10 11 A12 A13 14 A15 ON OFF ON ON ON ON ON ON ON ON SW103 POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT 7 5 4 A2 Al OFF ON OFF ON ON ON ON ON Page 9 3 Circuit Description 8 Bit Addressing When J105 pins 2 and 3 are jumpered only the address set by SW103 is compared Although SW107 is not compared the 8 bit addressing oper ates similarly to the 16 bit operation U107 is a 16L8 Programmable Array Logic PAL The PAL generates MREQ pin 13 and IOREQ pin 12 from IOADRS MEMADRS1 and 52 as shown by the PAL equations located in Chapter 12 MREQ controls LED D105 through buffer 0108 When active low the LED will light LED D102 operates the same way being controlled by IOREQ The S 100 Bus generates AS Address Strobe through U107 enabling U116 to sample MREQ and IOREQ Interrupt One output from U107 is the INTR line 0107 17 When U116 asserts its interrupt line INTR 9026 U107 will force INTR low causing LED D103 to turn on after being buffered by U138 INTR is connected to 4101 a series of jumpers refer to Figure 9 1 For use in the Z 100 is jumpered although it is possible to jumper and VIO VI7 For the system to operate properly only one jumper at a time can be used J101 Figure9 1 Interrupt Jumpers Page 9 4 Circuit Des
89. ring the readpor tion of the processor s read cycle The COM 9026 status register contents are defined as follows BIT 7 Receiver inhibited RI This bit set high indi cates that a packet has been deposited into the RAM buffer page nn as specified by the last ENABLE RECEIVE TO PAGE nn command The setting of this bit can cause an interrupt via INTR if enabled during a WRITE INTERRUPT MASK command No messages will be received until an ENABLE RECEIVE TO PAGE nn command is issued Alter any message is received the receiver is automat ically inhibited by setting this bit 10 a logic BIT 6 Extended Timeout Status 2 ETS2 This bit re flects the current logic value tied tothe ET2 input pin pin 1 BIT S Extended Timeout Status 1 ETS1 This bit re fects the current logic value tied tothe input pin pin 3 12 24 Data Sheets BIT 4 Power On Reset POR This bit i set high indi cates that the COM 9026 has received an active signal on the POR input pin 40 The setting of this bit will cause nonmaskable interrupt via INTR 3 Test TEST This bitis intended for test and diag nostic purposes It will be a logic zero under any normal operating conditions BIT 2 Reconfiguration RECON This bit i set high indicates that the reconfiguration timer has timed out because the RX input was idle for 78 2 micro seconds The setting of this bit can cause an Inter rupt via IN
90. rmore such information does not convey 10 the purchaser o Me semicanductor devices described any lice the patent ol SMC or others SMC reserves the right ta make changes at any time in order 0 improve design and supply the best product possible Page 12 35 Data Sheets 21903 STANDARD MICROSYSTEMS CORP Appendix A ID Node Number Lookup Table IDNO 555 555 888 888 888 888 888 888 858 885 BEE 888 888 888 888 888 Too 555 555 588 855 888 888 888 888 555 558 885 555 888 888 888 888 10 1 12 555 aks 555 555 888 888 888 888 858 885 888 888 555 888 888 10 11 12 16 17 18 585 555 555 888 555 888 888 13 14 15 19 20 21 555 555 biz 555 888 888 555 885 112 11 135 555 888 888 1 10 1 585 588 588 588 588 855 888 1F 20 21 588 555 biz 885 888 888 888 888 588 Page A 2 ID Node Number Lookup Table IDNO DEC HEX 2 1 555 555 ake 555 BEE 555 555 555 888 888 BEE 555 888 888 888 888 KER 588 855 58 555 555 555 888 555 888 888 888 233 858 555 555 555 885 555 888 888 665 655 888 888 555 555 888 888 588 885 888 555 555 888 888 588 923 585 555 555 555 888 888 558 bb 885 555 BEE 888 888 88 555 55 55 11 11 888 888 555 555 555
91. rocessor address captured during AS time onto the interface address bus A10 IA8 IAD7 IAD0 The sig nal L will capture the 8 least significant bits of this address appearing on IAD7 IAD0 before the dala is multiplexed onto it At the falling edge of L a stable address is pre sented to the RAM buffer For read cycles OE allows the addressed RAM buffer data to source the interface address data bus IAD7 IADO In figure 2 this information is passed into a transparent latch gated with WAIT At the Talig edge ot WAIT the data accessed by the processor is captured PAYS LO ADOR X X 1 meu 5 77 II 2 Le eo ES aba pun FIGURE 4 PROCESSOR READ RAM FOLLOWED BY COM 9026 READ RAM and driven out via the logic function RD anded with REQ For processor I O read cycles from the COM 9026 ADIE and are used to enable the processor address inlo the COM 9026 Data out of the COM 9026 is gated through the transparent latch and appears on the processor s data bus with the same control signals used tor RAM read cycles For processor write cycles after the falling edge of L the 9026 produces WE write enable output to the RAM buffer and the ILE output from the COM 9026 allows the Processor data to source the interface address data bus IAD7 IADO At this time the COM 9026 waits for DWA before concluding
92. rough multiplexers U112 and U118 will be discussed ADIE Address Data Input Enable from U116 pulses low en abling the multiplexers through pin 15 Pin 1 on U112 and U118 are high since ILE Interface Latch Enable is high ILE determines whether data or address bits are enabled onto the IAD0 IAD7 internal bus While high ILE selects the B inputs the address lines of U112 and U118 After the address has been enabled to U116 ILE and ADIE pulse low select ing the inputs of U112 and U118 allowing U116 to latch the data on IAD0 IAD7 Page 9 2 Circuit Description input access for data from 101 16 is very similar address is passed 10 U116 in the same manner as previously discussed At this point U116 outputs its data onto the IADO IAD7 bus U104 then latches the data for output onto the DIO DI7 S 100 Bus System Decode and Control The memory access circuitry consists of U101 U105 U111 U134 SW101 and SW106 U105 and U134 are comparators which check the address on the bus with the address set by SW101 and SW106 If the address checks the outputs of 0105 19 MEMADRS2 and U134 19 1 are low 16 Bit Addressing The V0 access circuitry consists of U110 U135 SW103 and SW107 When J105 pins 1 and 2 are jumpered together the address on the bus is compared with the address set SW107 and SW103 Listed below are the settings for address switches selecting Note that OFF e
93. rticular byte of any transmission A three bit field of 110 which proceeds every byte provides the required negative transition The 0 in this three bit field may be thought of asa Startbit and the 11 may be thought of as two stop bits trom the previous byte When the COM 9026 is waiting tor another byte or the first byte within a message it will resynchronize the CA clock by temporarily halting the CA Clock at the high level It accomplishes this by lowering the signal When the RX line experiences a high to low transition the 0 in the three bit field the CA clock is restarted which in tum causes the DSYNC signal be raised tothe high level The circuitry of figure 1 assumes an RX bit spacing of 400 nanoseconds which must be equal to twice the period of the CA clock The circuitry of figure 1 is set up such that the next low to high transition of the CA clock occurs between 200 and 250 nanoseconds alter the high to low transition on RX This places the point at which the COM 9026 samples the RX input approximately midway into the bit Every other low to high transition on CA thereafter will be used to sample the B bit data byte thal follows Once the byte is received the signal is again activated in preparation for the next high to low transition on the RX line indicating the start of the next data byte The DSYNC out put will return to its high inactive state after each CA syn Chronization is established Figure 3 il
94. ry test in Chapter 6 SW106 This switch in conjunction with SW101 selects the MEMADRS location OF0000H POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT 15 A14 A13 A12 A11 NC NC ON OFF ON ON ON ON ON X X X SW107 This switch in conjunction with SW103 selects the IOADRS location POSITION 0 1 2 3 4 5 6 7 ADDRESSBIT 9 10 All A12 A13 A14 15 ON ON ON ON ON ON ON ON Chapter 5 Installation Introduction This chapter provides the necessary information to install the NET 100 1 Card and Network Interface NET 100 1 Card Installation CAUTION This product contains ESDS electrostatic sensitive devices Exercise extreme care in handling these devices to prevent damage Refer to Figure 5 1 and complete the following steps 1 Selecta vacant slot in the card cage assembly 2 Disconnect8 inch disk drive cable 134 1264 if used 3 Insert the NET 100 1 Card with the components facing forward into the selected card slot Seat the card firmly by pushing straight down Figure 5 1 NET 100 1 Card Installation Page 5 2 Installation Network Chassis Adapter Installation Refer to Figure 5 2 and complete the steps below C 66 CHASSIS ADAPTOR 6 BTx3 4 SELF TAPPING SCREW Figure 5 2 Network Chassis Adapter Installation Page 5 3 Installation 1 Choose of the adjacent unused 25 D pin connectors on the back panel We suggest J5 and J6 connectors Re
95. s example the extra time associated with this system adjust ment will be 10 times 93 6 microseconds plus the response lime of the active node which must be less than 74 micro Seconds assuming a one way cable propagation delay of 31 microseconds Just as with the NETWORK FIGURATION this adjustment has no long lasting effect on the system performance and will only increase the lime of a single token pass by an amount equal to the time taken to find the next active node on the network For a more detailed discussion of the critical perfor mance parameters refer to appendix 1 Extended Length Message Operation The COM 9026 can transmit and receive short packets maximum length of 253 bytes or long packets maximum length of 508 bytes When only short packets are used it is possible to use either a 1K or 2K RAM buffer When both long and short packets are used a 2K RAM buffer must be used Use of the extended length message feature is con trolled via the DEFINE CONFIGURATION command This command allows the user to set the long packet enable flag When this flag is set and the contents of RAM buffer address 02 is zero the packet is treated as a long packet with RAM buffer address 03 pointing to the address containing the first byte in Ihe message In this case the last byte in the mes sage resides in RAM buffer address 511 When the long packet enable flag is set both long and short packets can be handled However when
96. s sions are Shown below INVITATIONS TO TRANSMIT ITT ALERT BURST 24565 EOT DID 1323 33 043 1564s FREE BUFFER ENQUIRIES FBE ALERT BURST 24ys 6bts ENQ DID DID 1323 33 bits 1565 PACKETS ALERT 24 3 6503 SOH SID DID DID COUNT 220 us 55 bits B CHARACTERS 448 ps 558 bits CAC CRC _8 8 ks 22 bits 332 4483 ACKNOWLEDGEMENTS ALERT BURST 243 6545 _44 ps 11 bits 685 NEGATIVE ACKNOWLEDGEMENTS NAK ALERT BURST 24ys 6bits NAK 44 5 11 bits 6 8 3 In addition there are certain delay constants and cable propagation times required for analysis as described below CHIP TURNAROUND TIME Tta 12 6 ps This time is defined as the time from the end of any received transmission until the start of a response TOKEN PROPAGATION DELAY This time is defined as the CABLE propagation time between the node holding the token and the node receiving the token between the node holding the token and the node receiving amessage BROADCAST DELAY TIME Tbd 15 6 This time is defined as the time from the end of a trans mitted broadcast packet until the start of a token pass RESPONSE TIMEOUT Trp This time is the maximum amount of a time a COM 9026 RECOVERY TIME Tre 3 4 us This time is the amount trom the end of the RESPONSE TIMEOUT until the start of a token pass MICROSYSTEMS assumed aces devices any license under Ine pa
97. sserted when an enabled interrupt condition has occured REQUEST INTR returns to its inactive state by resetting Ihe interrupting status condition or the corresponding interrupt mask bit INTERFACE This output signal in conjunction with ADIE gates the processor s address data LATCH bus PAD7 PADO onto interface address dala bus IAD IADO dun ENABLE data valid portion ol a Processor Write RAM or Processor Wnle COM 90 operation 55 ADIE This output signal enables the processor s address dala bus PAD7 PADO cap INPUT tured by AS or ILE onto the interface address data bus 1AD7 lADO 13 ADDRESS This output signal enables me processor s upper 3 address bits PA10 PAB onto INPUT interface address bus IA10 IAB ENABLE 15 LATCH t This output signal latches the interface address dala bus IAD7 IADO into a latch which feeds tho lower 8 address bits ol the RAM butter during address valid time of all RAM butter access cycles 17 WRITE This output signal is used as a write pulse to the external RAM butter Data is ret ENABLE erenced to the trailing edge of WE 18 OUTPUT OE This outpul signal enables the RAM buffer output data onto the interlace ENABLE address data bus IAD7 IAD0 during the data valid portion of all RAM butter read operations 33 IDLOAD 1005 This output signal synchronously loads the value selected by the ID switches into an external shift register in preparation for shifting the
98. ssible 1082 STANDARD MICROSYSTEMS CORP 4 83 2 5M Page 12 30 Data Sheets STANDARD MICROSYSTEMS COM 9032 Local Area Network Transceiver LANT FEATURES PIN CONFIGURATION Reduces chip count for COM 9026 ARCNET implementations by 6 8 TTL chips 0 Performs all clock generation functions for the COM 9026 LI Compatible with the COM 9026 O Provides line drive signals for transmission E Converts incoming serial receive data to NRZ data format LI Generates two 4 MHz general purpose clocks GENERAL DESCRIPTION The COM 9032 local area network transceiver is a com panion chip to the COM 9026 Loca Area Network Control ler LANC and will perform the additional functions necessary to allow simple interface to a transmission media for all ARCNET orequivalent local area networks Using a 20 MHz input clock the COM 9032 will produce two 5 MHz clocks for the COM 9026 The first 5 MHz clock is free run ning and will directly feed the CLK input of the COM 9026 pin 19 The second 5 MHz clock has start stop capability which is controlled by the DSYNC output cf the COM 9026 pin 36 and the received data input as required by the COM 9028 pin 2 Two additional 4 MHz free running clocks are also generated on the COM 9032 to allow operation other logic a microprocessor or an 1 51 controller During data reception the COM 9032 will convertincom ing serial receive data from the transmission media to NAZ form which wi
99. sts a bus cycle at the same time as the processor or shortly after the processor COM 9026 cycle will follow immediately after the pro cessor cycle Figure 4 illustrates the timing relationship of a Processor RAM Read cycle followed by a COM 9026 RAM read cycle Once the AS signal captures the processor address to the RAM buffer and requests a bus cycle it takes 4 CLK periods for the processor cycle to end Figure 4 breaks up these 4 CLK periods into 8 half clock interval labeled 1P through BP A COM 9026 access cycle will take 5 CLK periods lo end Figure 4 breaks up these 5 CLK periods into 10 hall intervals labeled 1C through 10 If a processor cycle request occurs after a 9026 request has already been granted the COM 9026 cycle will occur first as shown in figure 5 Figure 5 illustrates the timing relationship of a COM 9026 RAM Write cycle followed by a Processor RAM Write cycle Due to the asynchronous nature of the bus requests AS and CLK the transition from the end of the COM 9026 cycle to the beginning of the proces sor cycle might have some dead time Retering to figure 5 if AS falling edge occurs after the start of half CLK interval 9C no real contention exists and it will take between 200 and 500 nanoseconds before the processor cycle can start The start of the processor cycle is defined as the time when the COM 9026 produces a leading edge on both ADIE and If the processor request occurs before the end of
100. t Vec 0 5 ka 0 1 mA CA and LANCLK outputs 04 v la 0 4 mA and LANCLK outputs LEAKAGE CURRENT 1 50 TTLCLK input with CKSEL low 10 m all other inputs INPUT CAPACITANCE N 30 pl SUPPLY CURRENT 20 mA at 20 MHz OSC frequency AC CHARACTERISTICS PARAMETER MIN TYP MAX UNIT COMMENTS OSC Input k 50 ns ta 20 ns Lt 20 ns CA LANCLK os 200 ns pe 76 ns pn 75 ns ta 20 ns _ 2 na TTLCLK 250 ns 110 ns MI 110 CPUCLK CKSEL is high 250 ns 110 ns 110 ns tee ns 30 ns 45 ns for CKSEL low TRANSMIT TIMING 10 ns 10 ns 10 ns pus 10 ns 60 ns bio 80 ns 60 ns I 2 ns 52 ns om 2 ns pon 4 ns RECEIVE TIMING ts 10 ns p 10 ns 70 ns to Stovi too ns t 10 ns 20 ns 400 ns Page 12 34 Data Sheets en tas 15 CKSEL HIGH as CPUCLK 05 CX86L HIGH CKSEL Lom p TIN d k CKSEL HIGH FIGURE 3 CLOCK TIMING FIGURE 5 RECEIVE TIMING PARAMETERS 403 5 STANDARD MICROSYSTEMS CORPORATION diagrams utilizing SMC products are Included as means of illustrating typical semiconductor applica front consequently complete infarmation sufficient for construction purposes is not nec ssanly given The informator has been caralully checked and is believed 10 be entirely reliable However no responsibility assumed for maccuracies Furthe
101. te is received by the COM 9026 the CA clock stopped by the COM 9026 via DSYNC unti the first bit of the next byte is received which will automatically re start the CA clock The COM 9026 uses the CA clock to qure data and these sample points are shown in igure 5 Typically RXIN pulses occur at multiples of the transmis sion rate of 2 5 MHz 400 nanoseconds The COM 9032 can tolerate distortion of plus or minus 100 nanoseconds and still correctly capture and convert the RXIN pulses to NAZ format Page 12 33 Data Sheets MAXIMUM GUARANTEED RATINGS Operating Temperature Range 0 to 70 C Storage Temperature Range 55 to 150 C Lead Temperature soldering 10 as Positive Voltage on any Pin Pe Negative Voltage on any Stresses above those ated may cause permanent damage to the device This is a rating only and functional operation ot he device at these or at any other condition above those indicated in the operational sections of this specification is not implied DC ELECTRICAL CHARACTERISTICS T 0 Cto 70 Vos 5V 5 PARAMETER MIN TYP MAX UNIT COMMENTS INPUT VOLTAGES V 20 08 V OUTPUT VOLTAGES Von 40 v PULST PULS2 D Ves 04 v lop 4 0 mA PULST PULS2 AXOUT and TTLCLK outputs Vos Veo 0 5 v lo 0 1 mA CPUCLK output 04 V 1 0 1 CPUCLK outpu
102. te messages If only a single node is sending messages it can send one every 833 microseconds a rate of 1200 messages per second 120 000 bytes per second If all 10 nodes send 100 byte messages each node will be able to send a message every 5 81 milliseconds a rate of 172 messages per second or 17 200 bytes per second In actual practice Datapoint Corporation has installed many ARCNET systems with as many as 200 nodes active at any given time A typical network supports two totally independent operating systems and a wide variety of uses including program loading word processing print spool ing program development electronic mail etc The traffic toad on this type network rarely falls belaw 400 messages ADDRESS F3 91 37 100 C9 DATA BYTE 1 2 3 201 FIGURE 15 TYPICAL SHORT BUFFER AFTER RECEPTION 00 16 200 1 1 2 1FF DATA BYTE 490 FIGURE 16 TYPICAL LONG PACKET BUFFER AFTER RECEPTION Page 12 12 Data Sheets per second yetless than 2 ol the nodes senda message any single token trip The time required lor a token trip therefore stays very close to the traffic value wilh peaks of three times the no value being extremely rare 9026 has some interesting features that allow one to monitor the dynamic performance ol the network from any node
103. tent ai any time order 1o emprove Gen and supply Ine bett product Given the above numbers is possible to calculate time the start of one token pass to the start of the next token pass For cases a Trp of 74 6 ps is assumed SIMPLE TOKEN PASS no message sent 156 126 28253 TOKEN PASS AND MESSAGE 35605 126 156 5 12 6 Tom 685 Ta 126 Tom 3324s 448 12605 68 5 _12 6us 1410 5 448 4Tpm TOKEN PASS AND MESSAGE recever inhibited 156 Tta Tpm 2Tpm ae Tod 15645 12 6 3324s 4 4 15 6 270 6 4 48 ns Tip TOKEN PASS AND MESSAGE gets lost 156 12 Tol 15645 Ta 12 63 Tpm 685 12695 Tom 3323 44 Tp 7 Tc 34 5 1870 44 2Tpm TOKEN PASS AND MESSAGE destination node HT 1563 nore Ta 126 15655 7 _34 1218 us TOKEN PASS no response T Tc 156 8 746 8 34 8 836 Crea Gagrams ise SMC products are cluded as a ot Bustratng typical semiconductor ows nol convey to me purckamer o semiconductor of SMC or others reserves the ngat to make changes possible 1983
104. uration Time II any node does not receive the token within this lime the node will initiate a NETWORK RECONFIGURATION The ET2 and ET1 inputs allow the network to operate over longer distances than the 4 miles stated earlier DC levels on these inputs control the maximum distances over which the COM 9026 can operate by controlling the 3 timeout val ues described above Table 1 illustrates the response time and reconfiguration time as a function of the ET2 and ET1 inputs The idle time will always be equal to the response time plus 3 5 microseconds It should be noted that for proper network operation all COM 9026 s connected to the same network must have the same response lime idle time and reconfiguration time 10 RESPONSE RECONFIGURATION ET2 _ TIME us TIME ms 1 1 747 840 1 0 2834 1680 0 T 5618 1680 0 11186 1680 TABLE1 COM 9026 INTERNAL PROGRAMMABLE TIMER VALUES VO COMMANDS VO commands are executed by activating the input The COM 9026 will interrogate the ADO and the R W inputs al the AS time to execule commands according to the fol lowing table IOREQ ADO RW FUNCTION low low low write interrupt mask low low high read status register low high low write COM 9026 command low high high reserved for future use READ STATUS REGISTER Execution of this command places the contents of Ihe sta tus registeron the data bus AD7 ADO du
105. uration which is preset at the fac tory Refer to Figure 4 1 while reading this section CAUTION This product contains ESDS electrostatic sensitive devices Exercise normal caution in handling these devices to prevent static dis charge damage Figure4 1 Typical Configuration Page 4 2 Configuration Programming jumper across J101 pin 5 VI2 interrupt Programming jumper J105 pins 2 and right 8 bit VO addres sing Programming jumper on J107 and J108 pins 2 and 3 right and J109 J110 and J111 pins 1 and 2 left test points on COM9026 chip Programming jumper on J112 pins 1 and 2 left and J113 pins 2 and 3 right 2764 2 ROM DIP Dual Inline Pack Switch SW101 positions 0 3 to the ON 0 position and all others to the OFF 1 position to select for the RAM address DIP Switch SW102 positions 0 1 2 and 3 to the OFF 1 position and all others to the ON 0 position to select 0 4000 for the ROM address DIP Switch SW103 positions 0 and 2 to the OFF 1 position and all others to the ON 0 position to select for the address Dip Switch SW104 position 6 to the OFF 1 position and all other positions to the ON 0 position DIP Switch SW105 is the ID number switch Set this to the ID number you desire Each unit in the system must have a unique ID number For example for ID number 100 64H set positions 1 2 and 5 to th

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