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TM87P0X User's Manual

1. 1 Preliminary TM87POX User s Manual 1004 10 3 0 2 0 SEG31 DC30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 009 SEG19 004 SEG18 SEG17 SEG16 SEG15 XIN SEG14 SEG13 ERIN TM87P08 Die Size 2690 x 2890 um ee Pad Size 90 x 90 um Substrate has to connect to GND VDD2 SEG5 VDD3 CUP2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 DC9 SEGI SEG2 SEG3 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 1 5 PAD COORDINATE TM87R02 No Name 1 XIN 26 SEG11 2 XOUT 27 SEG12 3 FTIN 28 SEG13 4 FTOUT 29 SEG14 5 GND 30 SEG15 6 VDD1 31 SEG16 7 VDD 2 32 SEG17 8 TEST 33 SEG18 9 VDD3 34 SEG19 10 CUP1 35 SEG20 11 CUP2 36 SEG24 IOA1 12 COM1 37 SEG25 IOA2 13 COM2 38 SEG26 IOA3 14 COM3 39 SEG27 IOA4 15 COM4 40 SEG30 IOB3 BZB 16 SEG1 41 IOBA BZ 17 SEG2 42 IOC1 18 SEG3 43 IOC2 19 SEG4 44 IOC3 20 SEG5 45 IOC4 21 SEG6 46 IOD1 22 SEG7 47 IOD2 23 SEG8 48 RESET 24 SEG9 49 INT 25 SEG10 10 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual TM87P02 TM87P04 Nama TM87P02 TM87P04 X Name XIN SEG15 1667 50 XOUT SEG16 1667 50 FTIN SEG17 1667 50 FTOUT SEG18 1667 50 GND SEG19 1667 50 VDD1 SEG20 1667 50 VDD 2 N C SEG21 1667 50 TEST VPP 1 SEG22 1617 50 VDD3 SEG23 1502
2. Preliminary 87 User s Manual 88 2 Instruction Machine Code Function Flag Remark SRF X 1110 1100 00 X5 Enable Cx Control V xX 4 Enable TM2 Control X3 Enable Counter ENX X2 Enable RH Output EHM X1 Enable RT Output ETP X0 Enable RR Output ERR SRE X 1110 1101 X000 X7 Enable SRF7 key 5 V X5 Enable SRF5 INT X4 Enable SRF4 C port X3 Enable SRF3 D port FAST 1110 1110 0000 0000 SCLK High Speed Clock V SLOW 1110 1110 1000 0000 S CLK Low Speed Clock V CPHL X 110 1111 PC 1 lt force NOP if v x X7 0 IDBF7 0 SPK Rx 1111 0000 XXX 01 16 lt Rx amp AC v x SPK HL 1111 0001 0000 0000 01 16 V X 137 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual 88 2 Instruction Machine Code Function Flag Remark SPKX X 1111 0010 X6 1 KEY S release by v x scanning cycle X6 0 KEY_S release by normal key scanning 7 5 4 000 Set one of KO1 16 1 by 3 0 X7 5 4 001 Setall 1 X7 5 4 010 Set all Hi z X7 5 4 10X Set eight of KO1 16 1 by 3 X320 K01 8 X321 gt K09 16 X7 5 4 110 Set four of KO1 16 1 by X3 2 3 2 00 gt 1 4 3 2 01 gt 05 8 X3 2 10 K09 12 3 2 11 13 16 X7 5 4 111 Set two of KO1 16 1 by X3 2 1 X3 1 000 gt K01 2 X3
3. 127 technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual TM2X X TM87R02 TM87P02 TM87P04 TM87P08 Function Selects timer 2 clock source and preset timer 2 Description The data specified by X X8 X0 is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction X3 The clock source setting for timer 2 0 Po of 47 PHS s 0 T4 FREQ SF X TM87R02 TM87P02 TM87P04 TM87P08 Function Sets flag Description Description of each flag 1 The CF is set to 1 X1 1 The chip enters backup mode and is set to 1 X4 1 The watchdog timer is initiated and active XT 1 Enables the re load function of timer 1 X6 5 is reserved RF X TM87R02 TM87P02 TM87P04 TM87P08 machine code 1111 0100 X700X4 00X1Xo Function Resets flag Description Description of each flag 1 The CF is reset to 0 X1 1 The chip is out of backup mode and is reset to 0 X4 1 The watchdog timer is inactive XT 1 Disables the re load function of timer 1 X6 5 3 is reserved 128 tenx technology inc Rev 1 0 2006 04 11 Preliminary SF2 X Function Description RF2 X Function Description PLC Function Description 87 User s Manual TM87R02 TM87P02 TM87P04 TM87P08 Sets flag Description of ea
4. Depend on Part Number see OVERVIEW OF TM87POX B PORT A PORT C PORT D PORT FCD DRIVER ALARM RFC KEY IN FIXED SEGMENT PLA 4 BITS DATA BUS 222 il FREQUENCY Pir DATA RAM TABLE ROM GENERATOR SE 6BITSPRESET p gt 8LEVELS INSTRUCTION PRE DIVIDER TIMER1 8 2 STACK DECODER CUP1 2 CONTROL 12BITS PROGRAM ROM XTIN OUT CIRCUIT PROGRAM OSCILLATOR CFIN OUT COUNTER FRIN OUT o FTIN OUT RESET INT 87 BLOCK DIAGRAM tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 1 4 PAD DIAGRAM 1001 87 2 Die Size 1740 1980 Pad Size 90 90 um Substrate has to connect to GND ni E Ps VDD2 SEG7 VDD3 CUP2 COM1 COM2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 7 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual I0C4 I0C3 10 2 0 SEG30 SEG29 5 28 SEG26 SEG23 SEG22 D1 SEG21 13 SEG40 SEG41 RESET TM87P04 Die Size 1740 x 1980 um Pad Size 90 x 90 um Substrate has to connect to GND VDD2 SEG7 VDD3 CUP2 COM1 COM2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 8 tenx technology inc Rev 1 0 2006 04 11
5. Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Rx lt IOC Description The data of I OC port is loaded to and data memory Rx SPD X TM87R02 TM87P02 TM87P04 TM87P08 Function Defines the input output mode of each pin for IOD port and enables or disables the pull low device Description Sets the I O mode and turns the pull low device on or off The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Enable the pull low device on Disable the pull low device on 1001 1004 simultaneously 1001 1004 simultaneously X 2 0 IOD2 as output mode IOD2 as input mode IOD1 as output mode IOD1 as input mode TM87RO02 TM87P02 only IOD1 2 OPD Rx TM87R02 TM87P02 TM87P04 TM87P08 Function 1 lt Rx Description The content of Rx is outputted to 1 port IPD Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Rx AC lt Description The data of the I OD port is loaded to AC and data memory Rx SPKX X TM87P08 Function Sets the Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s set 7 0 to specify the key matrix scanning output state for each SEGn pin in the scanning interval Xs 0 when 5 is set to 1 the HALT released request HRF5 will be set to 1 after the key is depressed on the key matrix and then SCF7 will be set to 1 14 when HEF5 is set to 1 the HALT rele
6. N DBUSF DBUSB cy D8USA DBUSB DBUSC DBUSF DBUSE DBUSF DBUSG DBUSB opu DEUSA DBUSB DBUSC A DBUSE DBUSF DBUSG 0 08054 DBUSB DBUSC DBUSE DBUSF DBUSG DBUSH DBUSE DBUSF DBUSG DBUSA DBUSB DBUSC 0BH BH DBUSE DBUSA DBUSE DBUSA 0 0 c Oo x 5 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 5 2 5 SEGIA 5 SEGI6 5 SEGIB SEGIO SEG2O SEG21 5 21 SEG SEG26 SEG29 SEG3O SEGI SEGAL 91 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 87 8 PLA table 1 8 Dut 1 4 Dut gt come 12 DBUSD ig DBUSH 08050 DBUSH DBUSD 1 DBUSH DBUSD 44 DBUSH a 08058 DBUSE DBUSF DBUSG DBUSH peuse 5 2 DBUSH 08050 SEGIA DBUSH Bo DBUSD DBUSH eee DBUSD 4 DBUSH DBUSD DBUSH 08050 DBUSH 08150 71 DBUSH DBUSD DBUSH 08050 15 DBUSH 08080 DBUSH DBUSD DBUSH 1 4 Duty COMB COMB COM DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSA DBUSB DBUSC DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUSD DBUSH DBUS
7. 4 SCF 9 6 11 Halt release 13 15 HEF Operand Data 4 5 0 operand pata TM2 instruction TM2 instruction X8 X7 X6 i Interrupt accept signal R PLC 10h instruction Qu Initial reset DED Control signal of RFC counter falling edge of the 1st clock after TM2 is enabled 2 13 1 NORMAL OPERATION TMR2 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TM2 or TM2X instruction Once the TMR2 counts down to 3Fh it stops counting and then generates an underflow signal and the halt release request flag 4 HRF4 will be set to 1 When HRF4 1 and the TMR2 interrupt enabler IEF4 is set to 1 the interrupt occurred When HRF4 41 IEF4 0 and the TMR2 halt release enabler HEFA4 is set to 1 program will escapes from halt mode if CPU is in halt mode and then HRF4 sets the start condition flag 6 SCF6 to 1 in the status register 4 STS4 After power on reset the default clock source of TMR2 is PH7 If watchdog reset occurred the clock source of TMR2 will still keep the previous selection The following table shows the definition of each bit in TMR2 instructions OPCODE Select clock TM2X X 2 0 2 1 ACO Rx3 R2 Rx1 M2 QHL bite bits Bit4 bits bit2 bit1 bito 37 tenx technology inc Rev 1 0 2006 04 11 Preliminar
8. 87 2 87 4 Extrnal V S Freq amp Power Consumption 400 uA 2 350 uA 1 4MHz EH uA 1 2MHz So uA 1 0MHz 250 uA 0 8MHz 200 uA 0 6MHz 150 uA 0 4MHz 100 uA 0 2MHz 50 uA 0 0MHz 0 uA 10K 49K 100K 120K 150K 300K 499K 3 0V 25 87 8 Extrnal R V S Freq amp Power Consumption 400 uA 1 6MHz 1 4MHz 1 2 2 300 uA 1 0MHz 250 uA 0 8MHz 200 uA 0 6MHz 150 uA 0 4MHz 100 uA 0 2MHz 50 uA 0 0MHz 0 uA 10K 49K 100K 120K 150K 300K 499K 3 0 25 17 technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual DC Output Characteristics TM87P08 Only at 3 VDD2 2 4V Li at 4 VDD2 4 0V Ext V Name Symb Condition Port Min Typ Max Unit Output H Voltage Voh3c loh 1mA 3 1 5 1 8 V Voh4c 4 5 9 2 5 3 0 V EG1 41 Output L Voltage Vol3c lol 2mA 3 SEG 0 6 0 9 V Vol4c lol 6mA Z4 1 0 1 5 V Segment Driver Output Characteristics at 3 VDD2 2 4V Li at 4 VDD2 4 0V Ext V Name Symb Condition For Min Typ Max Unit 1 2 Bias Display Mode Output H Voltage Voh3f 1 2 2 V Voh4f loh 1uA Z4 3 8 V Vol3f lol 1uA 3 esp 0 2 V
9. 87 8 Only After the reset cycle the port is set as input mode and each bit of port be defined as input mode or output mode individually by executing SPC instruction Executed OPC instruction may output the content of specified data memory to the pins defined as output the other pins which are defined as the input will still remain the input mode Executed IPC instructions may store the signals applied to the IOC pins in the specified data memory When the IOC pins are defined as the output executing IPC instruction will save the data stored in the output latches in the specified data memory Before executing SPC instruction to define the IOC pins as output the OPC instruction must be executed to output the data to those output latches This will prevent the chattering signal when the IOC pins change to output mode 69 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual D bit0 E Q CLK bitO OC 1 nono gt bit1 lt q CLK 1 bit1 bt gt 7o gt 1 z Initial 5 x 554 edge dectect amp SCF 5 chattering 1 low option Bus bit2 yale CLK qe bit3
10. 3 7 1 RC Oscillation Network TM87P08 Only The RFC circuitry may build up 3 RC oscillation networks through RR RT or RH and CX pins with external resistors Only one RC oscillation network may be active at a time When the oscillation network is built up executing SRF 1h SRF 2h SRF 4h instructions to enable RR RT RH networks respectively the clock will be generated by the oscillation network and transferred to the 16 bit counter through the CX pin It will then enable or disable the 16 bit counter in order to count the oscillation clock Build up the RC oscillation network 76 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 1 Connect the resistor and capacitor on the RR RT RH and CX pins Fig 2 24 illustrates the connection of these networks 2 Execute SRF 1h SRF 2h or SRF 4h instructions to activate the output pins for RC networks respectively The RR RT RH pins will become of a tri state type when these networks are disabled 3 Execute SRF 8 SRF 18h or SRF 28h instructions to enable the RC oscillation network and 16 bit counter The RC oscillation network will not operate if these instructions have not been executed and the RR RT RH pins output 0 state at this time To get a better oscillation clock from the CX pin activate the output pin for each RC network before the counter is enabled The RFC function provides 3 modes for the operation of the 16 bit counter Each mode will be
11. Multiplexer zn amp LCD circuit driver DBUSA DBUSH LCD output Segment PLA Figure 5 3 Principal Drawing of LCD Driver Section The LCD driver section consists of the following units e Data decoder to decode data supplied from RAM or table ROM Latch circuit to store LCD lighting information LO to L4 decoder to decode the Lz specified data in LCD related instructions which specifies the strobe of the latch circuit Multiplexer to select 1 4 duty and 1 8 duty LCD driver circuitry Segment PLA circuit connected between data decoder LO to 14 decoder and latch Circuit TM87P08 Only The data decoder is used for decoding the contents of the working registers as specified in LCD related instructions They are decoded as 7 segment patterns on the LCD panel The decoding table is shown below 86 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Content Output of data decoder of data BUSA DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH memory 1 BR sam 53 RE SENSE RES Note The DBUSF of decoded output be selected as 0 1 by option The LCD pattern of this option is shown below DBUSA DBUSA DBUSF J DBUSB DBUSF DBUSB lt pBUsG gt lt gt DBUSG DBUSG DBUSE DBUSC DBUSE DBUSC lt lt Na DBUSD
12. User s Manual TM87R02 TM87P02 TM87P04 TM87P08 AC BCD AC Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected TM87R02 TM87P02 TM87P04 TM87P08 AC Rx lt BCD AC Converts the content of AC to decimal format and then restores to AC and data memory specified by Rx When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected TM87P08 QHL lt BCD AC Converts the content of AC to binary format and then restores to AC and the data memory HL When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected TM87P08 AC HL lt BCD AC HL HL 1 Converts the content of AC to binary format and then restores to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction is executed the AC must be the result of any subtracted instruction The carry flag CF will be affected AC data before DAS data before DAS AC data after DAS CF data after DAS execution execution execution execution 0 lt lt 9 6 lt AC lt F AC A 5 8 JUMP INSTRUCTIONS JBO X F
13. 87 2 87 2 87 4 87 8 LCD latch Lz lt data decoder lt Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder If the content of Ry is 0 the outputs of the data decoder are all 0 TM87R02 TM87P02 TM87P04 TM87P08 LCD latch Lz lt Ry AC The working register contents specified by Ry and the contents of AC are loaded to the LCD latch specified by Lz 93 tenx technology inc Rev 1 0 2006 04 11 Preliminary LCD Lz HL Function Description LCT Lz HL Function Description LCB Lz HL Function Description LCP Lz HL Function Description LCDX D Function Description LCTX D function description 87 User s Manual TM87P08 LCD latch Lz lt T HL HL indicates an index address of table ROM The contents of table ROM specified by HL are loaded to the LCD latch specified by Lz directly TM87P08 LCD latch Lz lt data decoder lt The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder TM87P08 LCD latch Lz lt data decoder lt R HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder If the content of is the outputs of the data decoder are all TM87P08 LCD latch Lz
14. HL indicates an index address of data memory TM87P08 AC HL lt HL amp AC HL HL 1 Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory TM87R02 TM87P02 TM87P04 TM87P08 AC lt Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC TM87P08 AC lt Exclusive Ors the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory TM87P08 AC lt Q HL AC HL 1 Exclusive Ors the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory TM87RO02 TM87P02 TM87P04 TM87P08 AC Rx Rx AC Exclusive Ors the contents of Rx and AC the result is loaded to AC and the data memory Rx TM87P08 AC HL HL AC Exclusive Ors the contents of HL and AC the result is loaded to AC and the data memory QHL HL indicates an index address of data memory 109 tenx technology inc Rev 1 0 2006 04 11 Preliminary EOR HL Function Description OR Rx Function Description
15. R HL The contents of index RAM specified by HL and the contents of AC are loaded to the LCD latch specified by Lz TM87P08 Mullti LCD latches Lz s TAB HL HL indicates an index address of table ROM The content of table ROM specified by HL are loaded to several LCD latches Lz simultaneously Refer to Table 5 2 The range of multi Lz is specified by data D D 0 3 0 0 Multi Lz 00H 0FH Multi Lz 10H 1FH Table 5 2 The range of multi Lz latches TM87P08 Mullti LCD latch Lz lt data decoder lt HL The contents of index RAM specified by HL are loaded to several LCD latches Lz simultaneously The range of multi Lz is specified by data Refer to Table 5 2 D 0 3 94 tenx technology inc Rev 1 0 2006 04 11 Preliminary LCBX D Function Description LCPX D Function Description SPA X Function Description 87 User s Manual TM87P08 Mullti LCD latch Lz lt data decoder lt HL The contents of index RAM specified by HL are loaded to the LCD latch specified by Lz through the data decoder The range of multi Lz is specified by data Refer to Table 5 2 D 0 3 TM87P08 Mullti LCD latch Lz lt HL AC The contents of index RAM specified by HL and the contents of AC are loaded to several LCD latches Lz simultaneously Refer to Table 5 2 The range of multi Lz is specifi
16. 2 3 PROGRAM COUNTER PC This is an 11 bit counter which addresses the program memory ROM up to 2048 addresses The program counter PC is normally increased by one 1 with every instruction execution PC PC 1 When executing JMP instruction subroutine call instruction CALL interrupt service routine or reset occurs the program counter PC loads the specified address corresponding to table 2 1 PC specified address shows in When executing a jump instruction except JMP and CALL the program counter PC loads the specified address in the operand of instruction PC current page PC11 specified address in operand e Return instruction RTS PC content of stack specified by the stack pointer Stack pointer stack pointer 1 27 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Table 2 1 TM87R02 TM87P 02 TM87P 04 TM87P 08 s PCIIPCIO PC9 8 7 6 PC5 4 PC3 PC2 PC1 PC Interrupt Source EBEN Interrupt 2 Interrupt 0 input port C amp D timer 1 interrupt ma 010 pre divider interrupt 010 timer 2 interrupt niin Key Scanning interrupt m UD RFC counter interrupt Jump instruction P10 to PO Low order 11 bits of instruction operand TM87P08 Only When executing the subroutine call instruction or interrupt service routi
17. HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC The content of the index register will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory 103 tenx technology inc Rev 1 0 2006 04 11 Preliminary ADC Rx Function Description ADC HL Function Description ADC HL Function Description SBC Rx Function Description SBC HL Function Description SBC HL Function Description 87 User s Manual TM87R02 TM87P02 TM87P04 TM87P08 AC Rx lt RX AC CF The contents of Rx AC and CF are binary added the result is loaded to AC and data memory Rx Carry flag CF will be affected TM87P08 AC R HL lt R HL AC CF The contents of data memory specified by HL AC and CF are binary added the result is loaded to AC and data memory specified by HL Carry flag CF will be affected TM87P08 HL HL AC CF HL HL 1 Binary adds the contents of HL AC and CF the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory TM87RO02 TM87P02 TM87P04 TM87P08 AC lt Rx AC B CF The conte
18. OR HL Function Description OR HL Function Description OR Rx Function Description OR HL Function Description OR HL Function Description 87 User s Manual TM87P08 AC HL HL AC HL HL 1 Exclusive Ors the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory TM87R02 TM87P02 TM87P04 TM87P08 AC lt Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC TM87P08 AC lt HL AC Binary Ors the contents of HL AC the result is loaded to AC HL indicates an index address of data memory TM87P08 AC lt HL AC HL HL 1 Binary Ors the contents of HL AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory TM87R02 TM87P02 TM87P04 TM87P08 AC Rx Rx AC Binary Ors the contents of Rx and AC the result is loaded to AC and the data memory Rx TM87P08 AC HL HL AC Binary Ors the contents of HL and AC the result is loaded to AC and the data memory QHL HL indicates an index address of data memory TM87
19. The carry flag CF will be affected 106 tenx technology inc Rev 1 0 2006 04 11 Preliminary SUB Rx Function Description SUB HL Function Description SUB HL Function Description ADN Rx Function Description ADN HL Function Description ADN HL Function Description 87 User s Manual 87 2 87 2 87 4 87 8 lt Rx AC B 1 Binary subtracts the content of from the content of Rx the result is loaded to AC and Rx The carry flag CF will be affected TM87P08 AC HL HL AC B 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected TM87P08 AC HL HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected 87 2 87 2 87 4 87 8 Rx AC Binary adds the contents of Rx and the result is loaded to AC The result will not affect the carry flag CF TM87P08 lt HL
20. i bit3 IOC Control 2 IPC OPC lt s This figure shows the organization of IOC port Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state IOC port had built in pull down resistor and executing SPC instruction to enable disable this device IOC port also built in the pull low device for each pin but these devices are enable by option The pull down resistor and low level hold device in each IOC pin can t exist in the same time When the pull down resistor is enabled the low level hold device will be disable vise versa Executing SPC 10h instruction to enable the pull low device and 70 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual disable the low level hold device executing SPC Oh to disable the pull low device and enable the low level hold device When the low level hold device is enabled by option the initial reset will enable the pull low device and disable the low level hold device When the IOC pin has been defined as the output mode both the pull low and low level hold devices will be disabled Low level hold function option Option name Selected item C PORT LOW LEVEL HOLD 1 USE C PORT LOW LEVEL HOLD 2 NO US
21. 3 5 4 1 Chattering Prevention Function and Halt Release The port IOD is capable of preventing high low chattering of the switch signal applied on the IOD1 to IOD4 pins Chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing the SCC instruction the default selection is PH10 after the reset cycle When the pins of the IOD port are set as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry SPD 1 SPD 2 SPD 4 SPD 8 Interrupt request IOD1 IOD2 IOD3 IOD4 SCF3 HALT released request chattering PH10 chattering EHE prevention clcok PLC 1 Interrupt accept SCC intruction 5 intruction This figure shows the organization of chattering prevention circuitry Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOD1 is changed from L level to H level or from H level to L level and the remaining pins ex IOD2 to IOD4 are held level When the signal changes at the input pins of IOD port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will deliver the halt release request signal SCF3 At that time the chattering pre
22. ADN HL 0010 1001 1100 0000 AC HL lt HL AC HL lt HL 1 AND 0010 1010 AC lt RxANDAC AND 0010 1010 1000 0000 lt HLAND AC lt AND AC V AND HL 0010 1010 1100 0000 HL 414141 AND Rx 0010 1011 XXXX lt Rx AND AC V AND 0010 1011 1000 0000 AC HL lt HLAND AC V AND HL 0010 1011 1100 0000 AC HL lt GHLAND AC V HL lt HL 1 EOR Rx 0010 1100 AC lt Rx EOR AC V EOR 0010 1100 1000 0000 AC lt HLEOR AC V 132 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual 8 8 Instruction Machine Code Function Flag Remark EOR 0010 1100 1100 0000 lt HLEOR AC v xX HL lt HL 1 EOR Rx 0010 1101 XXXX lt Rx EOR AC V EOR 0010 1101 1000 0000 AC GHL lt HLEOR AC V X EOR HL_ 0010 1101 1100 0000 AC HL lt HLEOR AC v xX HL lt HL 1 OR RX 0010 1110 AC lt Rx OR AC OR 0010 1110 1000 0000 HLOR AC v x OR 00101110 1100 0000 AC lt OR AC vI x HL lt HL 1 OR Rx 0010 1111 XXXX lt Rx OR AC V OR 0010 1111 1000 0000 AC GHL lt GHL OR AC v x OR HL_ 0010 1111 1100 0000 AC GHL lt GHL
23. 07 6 11 TD7 6 10 TD7 6 201 TD7 6 200 TD5 0 Ctm FREQ Ctm 2 PH15 Ctm Ctm PH9 Set Timerl Value TMSX X 1110 001X XXXX X8 7 6 111 X8 7 6 110 X8 7 6 101 X8 7 6 100 X8 7 6 011 X8 7 6 010 X8 7 6 001 X8 7 6 000 5 0 Ctm PH13 Ctm PH11 Ctm PH7 Ctm PH5 Ctm FREQ Ctm 15 Ctm Ctm PH9 Set Timerl Value 2 Rx 1110 0100 2 lt Rx amp AC 2 GHL 1110 0101 0000 0000 Timer2 lt T HL TM2X X 1110 011X XXXX XXXX X8 7 6 111 X8 7 6 110 X8 7 6 101 X8 7 6 100 X8 7 6 011 X8 7 6 010 X8 7 6 001 X8 7 6 000 5 0 Ctm PH13 Ctm PHI Ctm PH7 Ctm PH5 Ctm Ctm 15 Ctm PH3 Ctm 9 SetTimer2 Value SHE 1110 1000 X6 X5 X4 X3 X2 1 Enable HEF6 Enable HEF5 Enable HEF4 Enable HEF3 Enable HEF2 Enable HEF1 RFC KEY_S TMR2 PDV INT TMR1 SIE X 1110 1001 X6 X5 4 3 2 1 0 Enable IEF6 Enable 5 Enable IEF4 Enable IEF3 Enable IEF2 Enable IEF1 Enable IEFO RFC 5 TMR2 PDV INT 1 C DPT X 1110 101X OXXX XXXX X8 X6 0 Reset P H15 11 Reset HRF 6 5 4 0 136 tenx technology inc Rev 1 0 2006 04 11
24. 2 output SRO 1 Shifts bit 3 to bit 0 OPAS 1 1 Bit 3 output Oe ee 10 1 1 Last data 11 5 1 Shift gate closes The timing chart below illustrates the above program 1 2 3 4 5 6 7 8 9 10 11 0 5 AC 2 1 IOA1 for 5 Bit1 for Rx 5 Bit2 for Rx 5 for 5 M M IOA2 M M M IOA3 M n jJ L M M lt t BCLK 2 If IOA1 pin is used as the CX pin for RFC function and the other pins IOA2 IOA3 are used for normal IO pins IOA1 pin must always be defined as the output mode to avoid the influence from the CX when the input chattering prevention function is active On the other hand the RFC counter can receive the signal changes on IOA1 when the RFC counter is enabled 67 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 3 5 2 IOB PORT IOB1 IOB4 pins are MUXed with SEG28 SEG29 BZB SEG30 and BZ SEG31 pins respectively by option OPTION table Option name Selected item SEG28 IOB1 2 IOB1 SEG29 IOB2 2 2 SEG30 IOB3 BZB 2 IOB3 SEG31 IOB4 BZ 2 4 87 8 Only following figure shows the organization of IOB port Initial clear SPB 1 IOB1 Initial clear SPB 2 IOB3 Initial clear SPB 8 SPB IOA Pull low option Note If the inpu
25. D 0H FH TM87R02 TM87P02 TM87P04 TM87P08 AC Ry lt Ry D D represents the immediate data Exclusive Ors the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH 87 2 87 2 87 4 87 8 AC Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC D 0H FH 87 2 87 2 87 4 87 8 AC Ry lt Ry D D represents the immediate data Binary Ors the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH 113 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 5 4 LOAD STORE INSTRUCTIONS STA Rx Function Description STA HL Function Description STA HL Function Description LDS Rx D Function Description LDA Rx Function Description LDA HL Function Description LDA HL Function Description LDH Rx HL Function Description 87 2 87 2 87 4 87 8 Rx lt The content of AC is loaded to data memory specified by Rx TM87P08 R HL AC The content of AC is loaded to data memory specified by HL TM87P08 HL AC HL HL 1 The content of AC is loaded to the data memory specified by HL The content of the index register
26. HL HLH 0110 1101 CF lt Rx3 HL Rx 0110 1110 AC HL lt Rx v x MRW HL Rx 0110 1110 1XXX XXXX AC HL I lt Rx v x HL HLH MWR Rx HL 0110 1111 AC Rx lt HL V X MWR IRX HL 0110 1111 1XXX XXXX AC Rx lt HL V X HL HLH RyRx 0111 OYYY lt Rx V MWR RxRy 0111 1YYY AC Rx Ry V 180 X 1000 P C lt X 1 181 X 1000 1XXX P C lt X ifAC1 1 182 X 1001 P C lt X ifAC2 1 183 1001 1XXX P C lt X ifAC3 1 JNZ X 1010 lt X 0 V JNC X 1010 1XXX P C lt X if CF 0 V 2 1011 P C lt X ifAC 0 V JC X 1011 1 XXXX P C lt X ifCF 1 CALL X 1100 STACK lt PC 1 lt X JMP X 1101 PC X V TMS Rx 1110 0000 AC3 2 511 Ctm FREQ AC3 2 10 Ctm PH15 AC3 2 01 Ctm PH3 AC3 2 00 Ctm PH9 AC1 0 PB3 0 Set Timerl Value 135 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Instruction Machine Code Function Flag Remark TM87P08 TM87P04 TM87RO2 PO02 TMS J HL 1110 0001 0000 0000
27. Two types of reset method for RESET pin and the type could be option the one is level reset and other is pulse reset It is recommended to connect a capacitor 0 1uf between RESET pin and VBAT This connection will prevent the bounce signal on RESET pin 3 2 1 1 Level Reset Once a 1 signal applied on the RESET pin TM87P0X will not release the reset cycle until the signal RESET pin returned to 0 After the signal on reset pin is cleared to TM87P0X begins the internal reset cycle and then release the reset status automatically OPTION table Option name Selected item RESET PIN TYPE 1 LEVEL 3 2 1 2 Pulse Reset TM87P08 Only Once a 1 signal applied on the RESET pin TM87P08 will escape from reset state and begin the normal operation after internal reset cycle automatically no matter what the signal on RESET pin returned to 0 or not OPTION table Option name Selected item RESET PIN TYPE 2 PULSE 57 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual The following table shows the initial condition of TM87P0X in reset cycle PC SCF1 7 BCF SRF3 4 5 7 SEF3 4 Program counter Start condition flags Backup flag Stop release enable flag Switch enable flags Halt release request flag Halt release enable flag Interrupt enable flag Alarm output Pull down flags in 1 1 00 port Input output ports 1
28. XXXX AC lt Rx ACB CF CF V SBC 0010 0010 1000 0000 AC lt HL ACB CF CF V SBC 0010 0010 1100 0000 AC lt HL ACB CF CF HL lt HL 1 SBC Rx 0010 0011 AC Rx lt Rx ACB CF CF V SBC 0010 0011 1000 0000 AC GHL lt GHL ACB CF V SBC I HL 0010 0011 1100 0000 AC GHL lt GHL ACB CF V HL lt HL 1 ADD Rx 0010 0100 XXXX JAC Rx AC CF V ADD HL 0010 0100 1000 0000 JAC lt 9HL CF V ADD BHL 0010 0100 1100 0000 AC lt 9HL CF V HL lt HL 1 ADD Rx 0010 0101 lt Rx AC CF V ADD HL 0010 0101 1000 0000 AC GHL lt CF V ADD HL_ 0010 0101 1100 0000 AC HL lt QHL V HL lt HL 1 SUB Rx 0010 0110 XXXX AC lt Rx 1 V SUB HL 0010 0110 1000 0000 AC lt 1 CF V SUB J HL 0010 0110 1100 0000 AC lt ACB 1 V HL lt HL 1 SUB Rx 0010 0111 XXXX AC Rx lt Rx 1 CF V SUB 0010 0111 1000 0000 AC HL lt GHL ACB 1 V SUB HL 0010 0111 1100 0000 AC GHL lt GHL ACB 1 HL lt HL 1 ADN Rx 0010 1000 AC lt Rx 4 AC V ADN 00101000 1000 0000 lt HL AC V ADN 0010 1000 1100 0000 JAC lt HL HL lt HL 1 ADN Rx 0010 1001 XXXX AC Rx lt Rx AC V ADN HL_ 0010 1001 1000 0000 AC HL
29. lt Rx Loads content of Rx to lower nibble of index address buffer L L3 Rx 3 L2 Rx 2 L1 Rx 1 LO Rx O TM87P08 If HL X force the next instruction as NOP Compare the content of the index register HL in lower 8 bits h and L with the immediate data X Note In the duration of the comparison of the index address all the interrupt enable flags IEF have to be cleared to avoid malfunction If the compared result is equal the next executed instruction that is behind the CPHL instruction will be forced as NOP If the compared result is not equal the next executed instruction that is behind CPHL instruction will operate normally The comparison bit pattern is shown below CPHL X X6 X5 X4 X3 X2 X1 HL IDBF7 IDBF6 IDBF5 IDBF4 IDBF3 IDBF2 IDBF1 IDBFO 119 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual 5 7 DECIMAL ARITHMETIC INSTRUCTIONS DAA TM87P04 TM87P08 Function AC lt BCD AC Description Converts the content of AC to binary format and then restores to AC When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected DAA Rx TM87P04 TM87P08 Function AC Rx BCD AC Description Converts the content of AC to binary format and then restores to AC and data memory specified by Rx When this instruction is execu
30. IEFO IEF6 are cleared and should be set with the next execution of the SIE instruction Refer to Table 3 1 Example Assume all interrupts are requested simultaneously when all interrupts are enabled and all of the the pins of IOC have been defined as input mode PLC 7Fh Clear all of the flags SCA 18h enable the interrupt request of IOC IOD SIE 5Fh enable all interrupt requests all interrupts are requested simultaneously 54 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Interrupt caused by the predivider overflow occurs and interrupt service is concluded SIE 57h Enable the interrupt request except the predivider Interrupt caused by the TM1 underflow occurs and interrupt service is concluded SIE 55h Enable the interrupt request except the predivider and TMR1 Interrupt caused by the TM2 underflow occurs and interrupt service is concluded SIE 45h Enable the interrupt request except the predivider TMR1 and TMR2 Interrupt caused by the RFC counter overflow occurs and interrupt service is concluded SIE 05h Enable the interrupt request except the predivider TMR1 2 and the RFC counter Interrupt caused by the IOC port and interrupt service is concluded SIE 04h Enable the interrupt request except the predivider TMR1 TMR2 RFC counter and IOC IOD port Interrupt caused by the INT pin and interrupt service is conclude
31. In stop mode this oscillator will be stopped 32768Hz Crystal 1 X tal When backup flag is set to 1 the oscillator operates with an extra buffer in parallel in order to shorten the oscillator start up time but this will increase the power consumption Therefore the backup flag should be reset unless required otherwise If XIIN pin is unused it must be connected to VDD2 The following table shows the power consumption of Crystal oscillator in different conditions EXT V power option BCF 1 0 Normal Increased Initial reset Increased Increased After reset Normal Increased 21 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 2 2 2 CONNECTION DIAGRAM OF FAST CLOCK OSCILLATOR CF CLOCK The CF clock is a multiple type oscillator option which provides a faster clock source to system In single clock operation fast only this oscillator will provide the clock to the system clock generator pre divider timer I O port chattering prevention clock and LCD circuitry In dual clock operation CF clock provides the clock to system clock generator only When the dual clock option is selected by option this oscillator will be inactive most of the time except when the FAST instruction is executed After the FAST instruction is executed the clock source BCLK of the system clock generator will be switched to CF clock and the clock source
32. Interrupt request HEF2 SCF2 Halt release request Mask option HRF2 PLC 4h nitial clear pulse Mask option Interrupt 2 receive signal Open type This figure shows the INT Pin Configuration 75 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual 3 7 Resister to Frequency Converter RFC TM87P08 Only The resistor to frequency converter RFC can compare two different sensors with the reference resister separately This figure shows the block diagram of RFC SRF 8h Controlled by Timer 2 SRF 18h interrupt SRF 28h signal J request SCF9 counter over nable CNT HRF6 CLKIN 16 bit counter flow flag MRF1 4 4 bit data bus SRF 18h to data memory and AC i gt SRF 28h FREQ output from frequency generator This RFC contains four external pins CX the oscillation Schmitt trigger input RR the reference resister output pin RT the temperature sensor output pin RH the humidity sensor output pin this can also be used as another temperature sensor or can even be left floating These CX RR RT and RH pins are MUXed with IOA1 SEG37 to IOA4 SEG40 respectively and selected by option TM87P08 Only OPTION table Option name Selected item SEG24 IOA1 CX 3 CX SEG25 IOA2 RR 3 RR SEG26 IOA3 RT 3 RT SEG27 IOA4 RH 3 RH
33. STS1 consists of 2 flags 1 Carry flag CF The carry flag is used to save the result of the carry or borrow during the arithmetic operation 2 Zero flag Z Indicates the accumulator AC status When the content of the accumulator is 0 the Zero flag is set to 1 If the content of the accumulator is not 0 the zero flag is reset to 3 The MAF instruction can be used to transfer data in status register 1 STS1 to the accumulator AC and the data memory RAM 4 The MRA instruction can be used to transfer data of the data memory RAM to the status register 1 STS1 The bit pattern of status register 1 STS1 is shown below Bit 3 Bit 2 Bit 1 BitO Carry flag AC Zero flag Z Read write Read only Read only Read only 2 14 2 STATUS REGISTER 2 STS2 Status register 2 STS2 consists of start condition flag 1 2 3 SCF1 SCF2 SCF3 and the backup flag The MSB instruction can be used to transfer data of status register 2 STS2 to the accumulator AC and the data memory RAM but it is impossible to transfer data of the data memory RAM to status register 2 STS2 The following table shows the bit pattern of each flag in status register 2 STS2 Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 3 Start condition flag 2 Start condition flag 1 Backup flag SCF3 SCF2 SCF1 BCF Halt release caused Halt release caused Halt release caused by The backup mode by the port by 5 4 5 6 7 9 the IOC port status Rea
34. The address of the data memory is specified by the instruction and the addressing range is from 00H to 7 2 Index addressing mode TM87P08 Only The index address register HL specifies the address of the data memory and all address space from 00H to FFH can be accessed The 16 specified addresses 70 to 7FH in the direct addressing memory are also used as 16 working registers The function of working register will be described in detail in section 2 8 31 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual RAM Direct Address Access d 70H 5 0 Working Register 2 lt vy 7FH 5 80 TM87P08 Only FFH K 4 Bts This figure shows the Data Memory RAM and Working Register Organization 2 8 WORKING REGISTER WR The locations 70H to 7FH of the data memory are not only used as general purpose data memory but also as the working register The following will introduce the general usage of working registers 1 Be used to perform operations on the contents of the working register and immediate data Such ADCI ADCI SBCI SBCI ADDI ADDI SUBI SUBI ADNI ADNI ANDI ANDI EORI EORI ORI ORI 2 Be transferred the data between the working register and any address in the direct addressing data memory RAM Such as MWR Rx Ry MRW Ry Rx 3 Decode or directly transfer the contents of the working register and output to the LC
35. When the IOD pins are set as output executing IPD instructions will save the data stored in the output latches in the specified data memory locations Before executing SPD instructions to define the IOD pins as output the OPD instructions must be executed to output the data to those output latches This will prevent the chattering signal when the IOD pins change to output mode IOD port has a built in pull low device for each pin that is selected by option To enable or disable this device execute the SPD instruction When the IOD pin has been set to the output mode the pull low device will be disabled OPTION table Pull low function option Option name Selected item IOC PULL LOW RESISTOR 1 USE IOC PULL LOW RESISTOR 2 NO USE Note If the input level is in the floating state a large current straight through current flows to the input buffer when both the pull low and L level hold devices are disabled The input level must not be in the floating state 72 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual bitO bitO IOD1 bit1 bit1 IOD2 Initial clear 9 57 SCF1 SPD 8 Data IOD Bus low option bit2 bit2 IOD3 bit3 bit3 IOD4 Control 2 IPD OPD This figure shows the organization of IOD port 73 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual
36. tribler circuit PH10 PH13 PH14 To sound circuit This figure shows the Pre divider and its Peripherals The PH14 delivers the halt mode release request signal setting the halt mode release request flag HRF3 In this case if the pre divider interrupt enable mode IEF3 is provided the interrupt is accepted and if the halt release enable mode HEF3 is provided the halt release request signal is delivered setting the start condition flag 7 SCF7 in status register 3 STS3 The clock source of pre divider is PH0 and 4 kinds of frequency of PH0 could be selected by option OPTION table Option name Selected item PH0 lt gt BCLK FOR FAST ONLY 1 PH0 BCLK PH0 lt gt BCLK FOR FAST ONLY 2 PH0 BCLK 4 PH0 lt gt BCLK FOR FAST ONLY 3 PH0 BCLK 8 PH0 lt gt BCLK FOR FAST ONLY 4 PH0 BCLK 16 26 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual 2 2 5 SYSTEM CLOCK GENERATOR For the system clock the clock switch circuit permits the different clock input from XTOSC and CFOSC to be selected The FAST and SLOW instructions can switch the clock input of the system clock generator The basic system clock is shown below SCLK T1 T2 T3 T4 Machine 2 Instruction N Cycle
37. will be incremented automatically after executing this instruction HL indicates an index address of data memory 87 2 87 2 87 4 87 8 AC Rx lt D Immediate data D is loaded to the AC and data memory specified by Rx D 0H FH 87 02 87 2 87 4 87 8 lt The content of Rx is loaded to AC TM87P08 lt R HL The content of data memory specified by HL is loaded to AC TM87P08 AC lt HL HL HL 1 The content specified by HL is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory TM87P08 Rx AC lt H T HL The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx 114 tenx technology inc Rev 1 0 2006 04 11 Preliminary LDH Rx HL Function Description LDL Rx HL Function Description LDL Rx HL Function Description MRF1 Rx Function Description MRF2 Rx Function Description MRF3 Rx Function Description 87 User s Manual TM87P08 Rx AC lt H T HL amp HL QHL 1 The higher nibble data of Table ROM specified by HL is loaded to data memory specified by Rx and then is increased in HL TM87P08 Rx lt L T HL The lower nibb
38. 0 Disables timer 2 to control the 16 bit counter timer 2 Disables timer 2 to control the 16 bit counter control the 16 bit counter The 16 bit counter is controlled by the signal X5 1 on CX pin must be setto 1 when this bitis 5 0 dl counter Note X4 and 5 can not be set to 1 at the same time 5 2 ACCUMULATOR MANIPULATION INSTRUCTIONS AND MEMORY MANIPULATION INSTRUCTIONS MRW Ry Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Rx Rx Description The content of Rx is loaded to AC and the working register specified by Ry MRW Rx TM87P08 Function R HL lt Rx Description The content of data memory specified by Rx is loaded to AC and data memory specified by HL MRW Rx TM87P08 Function AC R HL Rx HL HL 1 Description The content of data memory specified by Rx is loaded to AC and the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction 100 tenx technology inc Rev 1 0 2006 04 11 Preliminary MWR Rx Ry Function Description MWR Rx HL Function Description MWR Rx HL Function Description SRO Rx Function Description SR1 Rx Function Description SL0 Rx Function Description 87 User s Manual TM87R02 TM87P02 TM87P04 TM87P08 AC Rx Ry The content of
39. 000H to 7FFH or 800H to FFFH JZ X TM87R02 TM87P02 TM87P04 TM87P08 Function Program counter jumps to X if AC 0 Description If the content of AC is 0 jump occurs If 1 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH 4 X TM87R02 TM87P02 TM87P04 TM87P08 Function Program counter jumps to X if CF 1 Description If the content of CF is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH 122 tenx technology inc Rev 1 0 2006 04 11 Preliminary JMP X Function Description CALL X Function Description RTS Function Description TM87POX User s Manual TM87R02 TM87P02 TM87P04 TM87P08 Program counter jumps to X Unconditional jump The range of X is from 000 to FFFH TM87R02 TM87P02 TM87P04 TM87P08 STACK lt PC 1 Program counter jumps to X A subroutine is called The range of X is from 000 to FFFH 87 02 87 2 87 4 87 8 lt STACK A return from a subroutine occurs 123 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 5 9 MISCELLANEOUS INSTRUCTIONS SCC X TM87R02 TM87P02 TM87P04 TM87P08 Function Setting the clock source for IOC IOD chattering prevention PWM output and frequency generator Description The following table shows the meaning of each bit for this instruction Bit pattern Cloc
40. 1 001 gt K03 4 X3 1 010 gt K05 6 X3 1 011 gt K07 8 X3 1 100 gt K09 10 X3 1 101 gt K011 12 X3 1 110 gt K013 14 3 1 111 gt 015 16 5 1111 0100 0000 0000 lt STACK V CALL Return SCC X 1111 0100 1 0 X6 1 Cfq BCLK V X6 0 PH0 X4 1 Set P C Cch X321 Set P D Cch X2 1 0 001 Cch 2 PH10 X2 1 0 010 Cch PH8 X2 1 0 100 Cch 2 PH6 SCA X 1111 0101 000X X000 X4 Enable SEF 4 C1 4 TM87P 08 only V X3 Enable SEF3 D1 4 SPA X 1111 0101 100X 4 Set A4 1 Pull Low 1 P ull low V X3 0 SetA4 1 1 0 1 Output 0 Input 138 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 8 8 Instruction Machine Code Function Flag Remark SPB X 1111 0101 101X X4 Set B4 1 Pull Low 1 P ull low TM87P08 3 0 Set B4 11 0 1 0 utput 0 Input 1111 0101 101X XX00 TM87P 04 R02 P 02 Only 87 4 02 2 B4 3 SPC X 1111 0101 110X X4 Set C4 1 Pull Low 1 P ull low 0 LLH V Low Level Hold X3 0 Set C4 11 0 1 0 utput 0 Input SPD X 1111 0101 111X XXXX X4 Set D4 1 Pull Low 1 P ull low 87 3 0 56104 11 0 1 Output 0 Input 1111 0101 111X 00 TM87R02 P 02 Only D2 1 87 02 02 SF X 1111 0110 00XX 7 Reload 1 Set V X4 WDT Enable X1 BCF Set X0 CF Set RF X 1111 0111 X00X 7 Reload 1
41. 1 and interrupt 5 is accepted the instruction at address 24H will be executed automatically 87 Only 3 1 1 2 Internal interrupt factor The internal interrupt factor involves the use of timer 1 TMR1 timer 2 TMR2 counter and the pre divider 1 Timer1 2 TMR1 2 interrupt request An interrupt request signal HRF1 4 is delivered when timer1 2 TMR1 2 underflows In this case if the interrupt enable flag 1 4 IEF1 4 is set interrupt 1 4 is accepted and the instruction at address 18H 20H is executed automatically 2 Pre divider interrupt request An interrupt request signal HRF3 is delivered when the pre divider overflows In this case if the interrupt enable flag3 IEF3 is set interrupt 3 is accepted and the instruction at address 1CH is executed automatically 3 16 bit counter of RFC CX pin control mode interrupt request An interrupt request signal HRF6 is delivered when the 2 falling edge applied on CX pin and 16 bit counter stops to operate In this case if the interrupt enable flag6 IEF6 is set interrupt 6 is accepted and the instruction at address 28H is executed automatically TM87P08 Only 3 1 2 INTERRUPT PRIORITY If all interrupts are requested simultaneously during a state when all interrupts are enabled the pre divider interrupt is given the first priority and other interrupts are held When the interrupt service routine is initiated all of the interrupt enable flags
42. 122 CHAPTER 6 Programming Wavetform 128 APPNDIX A TM87P0X Instruction Table 129 APPNDIX B Typical Application 138 2 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Chapter 1 General Description 1 1 GENERAL DESCRIPTION The TM87P02 TM87R02 TM87P04 TM87P08 is an embedded high performance 4 bit micro controller with LCD driver 1 2 FEATURES 1 Powerful instruction set eBinary addition subtraction BCD adjusts logical operation in direct and index addressing mode Single bit manipulation set reset decision for branch e Various conditional branches 16 working registers and manipulation LCD driver data transfer 3 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 1 2 1 Overview of TM87POX TM87POX ROX 87 02 Part 87 08 87 04 ITM87P02 Clock Source Dual Operating 3 0 5 0V 3 0V Voltage Lc ae 8 x 32 Fixed 4 x 25 Fixed ProgrmROM ak x 1601 Table ROM AK 8 RAM 256 x 4 128 x4 INT PIN Yes RESET POR Pulse Level Level Debounce IOC D IOC RFC Yes EL 5 Yes 5 Pre Divider Yes Ti Timer1 2 6 bit p
43. 2 Note 2 is a factor For example if the LCD frame frequency is 32Hz and duty cycle is 1 5 duty the scanning frequency for the key matrix is 320Hz 32 x 5 x 2 key scanning SKI input amp latch key scanning input amp latch key scanning BIS i input amp latch Rising edge strobe Q HRF5 LU key scanning 5 input amp latch pet key scanning enable signal IPC PLC 20h Initial Reset Interrupt 5 request This figure shows the organization of Key matrix scanning input Example SPC Ofh Disables all the pull down devices on the internal IOC port Sets all of the IOC pins as the output mode SPKX 10h Generates HALT release request when a key is depressed 82 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Scans every column simultaneously in each cycle PLC 20h Clears HRF5 SHE 20h Sets HEF5 HALT waits for the halt release caused by the key matrix MCX 10h Checks SCF8 SKI JB0 ski_release ski_release IPC 10h reads the KI1 4 input latch state JBO ki1_release JB1 ki2_release JB2 ki3 release JB3 ki4 release ki1 release SPKX 40h Checks the key depressed on 1 column PLC 20h Clears HRF5 to avoid the false HALT release CALL wait scan again Waits for the next key matrix scanning cycle The waiting period must be longer than the key matrix scanning cycle IPC 10h Reads the KI1 i
44. 87 8 Only 28 2 0 Stack R egister STACK 28 2 Memory 29 2 8 Working Register WR u 30 2 9 Accumulator AG accom UU NEU UNI DI NUI DIM UD 30 2 10 ALU Arithmetic and Logic Unit 30 2 11 Hexadecimal Convert to Decimal HCD 31 2 12 Hime WA TIMER A ite mua m cas Piste DU pe a akun Ne 32 2 19 Timer 2 TMRZ a ste b RR DER anasu RUM DU E EUER 35 2 14 talus Register S TS s cp eoe DU 39 2 19 Control Register cocci eee e ee Fx pee Fn Eten tore temet geben tegebant ker 44 2 16 HALT PURCHON 47 ZAM Pi BICK UF UIC HOM ER 48 2 10 STOP DAMM QM eMe 48 1 technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual CHAPTER 3 Control Function J 50 ag s on a suu nasua 50 3 2 Em 54 3 3 Clock Generator Frequency Generator and Pr
45. D Duty Cycle D1 DO O 0 144 0 1 Bday O dwy FRQX D X 87 2 87 2 87 4 87 8 Function Frequency generator lt D X Description Loads the data X X7 X0 and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting x 1 1 ThebitpattemofpresetletterN Note X0 X7 represents the data specified in operand X 1100 0 10 _ O 1 dy 1 O ady 1 FRQ D Rx The content of Rx and AC as preset data N 2 FRQ D HL The content of tables TOM specified by index address buffer as preset data N 3 FRQX D X The data of operand in the instruction assigned as preset data N 125 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual TMS Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Select timer 1 clock source and preset timer 1 Description The content of data memory specified by Rx and AC are loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction Select clock Setting value The clock source option for timer 1 TMS HL TM87P08 Function Select timer 1 clock source and preset timer 1 Description The content of table ROM specified by HL is loaded to timer 1 to start the timer The following table sho
46. DBUSH DBUSD DBUSH DBUSF 0 DBUSF 1 The following table shows the options table for displaying the digit 7 pattern OPTION table Option name Selected item SEGMENT FOR DISPLAY 7 1 SEGMENT FOR DISPLAY 7 2 OFF Both LCT and LCB instructions use the data decoder table to decode the content of the specified data memory location When the content of the data memory location specified by the LCB instruction is 0 the decoded outputs of DBUSA DBUSH are all 0 this is used for blanking the leading digit 0 on the LCD panel The LCP instruction transfers data about the RAM Rx and accumulator AC directly from DBUSA to DBUSH without passing through the data decoder The LCD instruction transfers the table ROM data T HL directly from DBUSA to DBUSH without passing through the data decoder Table 2 2 The mapping table of LCP and LCD instructions 87 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual __ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH There are 8 data decoder outputs from DBUSA to DBUSH 32 LO to L4 decoder outputs from PSTB Oh to PSTB 1Fh The input data and clock signal of the latch circuit are DBUSA to PSTB Oh to PSTB 1Fh respectively Each segment pin has 8 latches corresponding to COM1 8 The segment PLA performs the function of combining DBUSA outputs
47. HL HLH DAS 0101 0110 0000 0000 JAC BCD AC CF V DAS Rx 0101 0111 XXXX AC Rx BCD AC CF V DAS 0101 0111 1000 0000 AC GHL lt BCD AC CF v X DAS HL 0101 0111 1100 0000 AC GHL 8 V x HL HLH LDS RxD 0101 1 DXXX AC Rx lt LDH 0110 0000 XXXX AC Rx lt H T HL v X LDH Rx HL 0110 0001 AC Rx lt H TGHL V X HL lt HL 1 134 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 8 gg Instruction Machine Code Function Flag Remark LDL RxGHL 0110 0010 AC Rx lt L T HL v x LDL Rx HL 0110 0011 AC RX lt L T HL HL lt HL 1 MRF1 Rx 0110 0100 lt RFC3 0 v x MRF2 Rx 0110 0101 lt RFC7 4 v x MRF3 Rx 0110 0110 lt 11 8 v x MRF4 Rx 0110 0111 lt 15 12 v x 0110 1000 R X lt V STA 0110 1000 1000 0000 HL v x HL lt AC vl x STA HL 0110 1000 1100 000010 141 LDA 0110 1100 lt Rx V LDA 110 1100 1000 0000 AC lt HL LA oes LDA HL 0110 1100 1100 0000 AC lt HL
48. TM87P02 TM87P04 TM87P08 no operation no operation 87 2 87 2 87 4 87 8 Enters mode The following 3 conditions cause the halt mode to be released 1 An interrupt is accepted 2 The signal change specified by the SCA instruction is applied to IOC 3 The halt release condition specified by SHE instruction is met When an interrupt is accepted to release the halt mode the halt mode returns by executing the RTS instruction after completion of interrupt service TM87R02 TM87P02 TM87P04 TM87P08 Enters stop mode and stops all oscillators Before executing this instruction all signals on IOC port must be set to low The following 3 conditions cause the stop mode to be released 1 One of the signal on KI1 4 is H L LED LCD in scanning interval 2 A signal change in the INT pin 3 One of the signals on IOC port is H TM87R02 TM87P02 TM87P04 TM87P08 The data specified by X causes the halt mode to be released The signal change at port IOA IOC is specified The bit meaning of X X4 is shown below Bit pattern Description Halt mode is released when signal applied to IOC X7 5 X3 0 is reserved 116 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual SIE X TM87R02 TM87P02 TM87P04 TM87P08 Function Set Reset interrupt enable flag Description X0 1 The IEFO is set so that interrupt 0 Signal change at port IOC
49. described in the following sections 3 7 2 Enable Disable the Counter by Software TM87P08 Only The clock input of the 16 bit counter comes from the CX pin and is enabled disabled by the S W When SRF 8h instruction is executed the counter will be enabled and will start to count the signals on the CX pin The counter will be disabled when SRF 0 instruction is executed Executing MRF 1 4 instructions may load the result of the counter into the specified data memory and AC Each time the 16 bit counter is enabled the content of the counter will be cleared automatically Example If you intend to count the clock input from the CX pin for a specified time period you can enable the counter by executing SRF 8 instruction and setting timer1 to control the time period Check the overflow flag RFOVF of this counter when the time period elapses If the overflow flag is not set to 1 read the content of the counter if the overflow flag has been set to 1 you must reduce the time period and repeat the previous procedure again In this example use the RR network to generate the clock source Timer 1 is used to enable disable the counter LDS 0 0 Set the TMR1 clock source PH9 LDS Td initiate TMR1 setting value to 3F LDS 2 OFh SHE 2 enable halt release by TMR1 RE CNT LDA 0 OR 1 combine the 1 setting value TMS 2 enable the TMR1 SRF 9 build up the RR network and enable the counter HALT SRF 1 stop the counter when TMR1 underflo
50. don t care X7X5X4 111 in this setting each scanning cycle checks two specified columns on key matrix The specified columns are defined by the setting of X gt and X4 X3X2X1 000 activates K1 K2 columns simultaneously X3X2X1 001 activates K3 K4 columns simultaneously X3X2X1 110 activates K13 K14 columns simultaneously X3X2X1 111 activates K15 K16 columns simultaneously Xo is not a factor When Kl1 4 is defined for the Key matrix scanning input by option it is necessary to execute the SPC instruction to set the internal unused IOC port to output mode before the key matrix scanning function is activated Fig 2 27 shows the organization of the Key matrix scanning input port Each one of the SKI1 4 changed to High will set HRF5 to 1 If HEF5 has been set to 1 beforehand this will cause SCF7 to be set as well as releasing the HALT mode After the key scanning cycle the states of SKI1 4 will be latched and executing the IPC instruction could store these states into data RAM Executing the PLC 20h instruction clears the HRF5 flag 81 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual Since the key matrix scanning function shares the timing of LCD waveform the scanning frequency corresponds to the LCD frame frequency and the LCD duty cycle The formula for the key matrix scanning frequency is shown below key matrix scanning frequency Hz LCD frame frequency x LCD duty cycle x
51. flag of IOC port CSR to output and stop release enable flag 4 5 is set beforehand A high level signal comes from the OR ed output of the pins defined as input mode in IOD port which causes the stop release flag of IOD port DSR to output The stop release enable flag3 SRF 3 must be set beforehand The signal change from the INT pin causes the halt release flag 2 HRF2 to output and the stop release enable flag 5 SRF5 is set beforehand The stop release flags 5 CSR DSR HRF2 were specified by the stop release enable flags SRFx These flags should be clear before the chip enters stop mode All of the pins in the and IOC ports have to be set in input mode and keep in 0 state before the chip enters the STOP mode otherwise the program cannot enter STOP mode Instruction SRE is used to set or reset the stop release enable flags SRF4 5 7 TM87P08 Only The following figure shows the organization of start condition flag 11 SCF 11 HRF2 scF11 Stop release request SRF7 SRF4 The following table shows the stop release request flags The OR ed latched The OR ed input mode The rising or falling signals for 1 4 pins oflOC IOD port edge on INT pin 45 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual Stop release request flag CSR DSR HRF2 Stop release enable flag SRF7 SRFA SRF3 SRF5 TM87P08 Only 2 15 CONTROL REGISTE
52. for other functions will still come from XT clock Halt mode stop mode or SLOW instruction execution will stop this oscillator and the system clock BCLK will be switched to XT clock There are 2 type oscillators can be used in fast clock oscillator selected by option 2 2 2 1 RC OSCILLATOR WITH EXTERNAL RESISTOR CF CLOCK If TM87P02 TM87P04 FRIN TM87P08 pin is unused it must be connected to GND OPTION table Option name Selected item CLOCK SOURCE 1 FAST ONLY or 3 Dual Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 1 EXTERNAL RESISTOR TM87P04 R TM87P08 External External Resistor Resistor 22 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 2 2 2 2 External 3 58MHz Ceramic Resonator oscillator If TM87P02 TM87P04 is unused it must be connected to GND If TM87P08 CFIN pin is unused it must be connected to VDD OPTION table Option name Selected item CLOCK SOURCE 1 FAST ONLY or 3 DUAL Option name Selected item FAST CLOCK OSC TYPE FOR FAST ONLY OR DUAL 2 3 58MHz CERAMIC RESONATOR 87 4 TM87P08 p CFOUT I 1 C CFIN _ 3 58MHz 3 58MHz Ceramic Ceramic Resonator Resonator Notes 1 When the program has to reset the BCF flag to 0 in Li battery power mode don t use a 3 58MHz Ceramic Resonator as the
53. if TMR2 underflows 4 When halt release or interrupt occurs clear the HRF4 flag by PLC instruction and increase the counting value to count the underflow times 5 When halt release or interrupt occurs for the 7 time reset the DED flag 6 When halt release or interrupt occurs for the 8 time disable the re load function and the counting is completed In the following example S W enters the halt mode to wait for the underflow of TM2 39 tenx technology inc Rev 1 0 2006 04 11 Preliminary LDS PLC SHE SRF TM2X SF2 RE LOAD HALT INC PLC LDS SUB JNZ RF2 NOT RESET DED LDA JB3 1 subroutine JMP RE LOAD END 1 RF2 0 0 10h 10h 19h 34h 3h 0 10h 20h 7 0 87 User s Manual initiate the underflow counting register enable the halt release caused by TM2 enable RFC and controlled by TM2 initiate the TM value 52 and clock source is 9 enable the re load function and set DED flag to 1 increase the underflow counter clear HRF4 when halt is released for the 7 time reset DED flag NOT RESET DED 2 0 1 reset DED flag store underflow counter to AC if the TM2 underflow counter is equal to 8 exit this disable the re load function TM2 i 5 ant u count 08 count NN count M count ANE count count icles HRF4 lt PLC Re load DED _ TENX This figure s
54. lt amp AC D 0 1 V X OPA Rx 0000 1010 Port A lt Rx X OPAS Rx D 10000 1011 1 2 3 4 8 0 8 1 0 5 V OPB Rx 0000 1100 Port B lt Rx OPC Rx 0000 1101 XXXx P ort C lt Rx V OPD Rx 0000 1110 XXXX ort D lt Rx V FRQ D Rx 0001 OODD OXXX XXXx FREQ lt Rx amp AC 0 00 1 4 Duty 0 01 1 3 Duty D 10 1 2 Duty D 11 1 1 Duly FRQ D HL 0001 01DD 0000 0000 FREQ lt T HL V FRQX DX 00011100 lt X V MVL 0001 1100 XxXxx IDBFO0 3 lt Rx Rx 0001 1101 0 4 7 lt Rx MVU Rx 0001 1110 IDBF8 11 lt Rx V ADC Rx 0010 0000 XXXX AC lt Rx AC CF ADC 0010 0000 1000 0000 JAC lt AC CF v X ADC HL_ 0010 0000 1100 0000 AC lt HL AC CF v x HL lt HL ADC 0010 0001 XXXX lt Rx AC CF CF V ADC 0010 0001 1000 0000 AC HL lt AC CF v x ADC HL_ 0010 0001 1100 0000 AC HL lt QHL AC CF CF V x HL lt HL l 131 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 88 2 Instruction Machine Code Function Flag Remark SBC Rx 0010 0010
55. oscillator 2 2 3 THE COMBINATION OF THE CLOCK SOURCES There are three types of combination of the clock sources that can be selected by option 2 2 3 1 DUAL CLOCK OPTION table Option name Selected item CLOCK SOURCE 3 DUAL The operation of the dual clock option is shown in the following figure When this option is selected by option the clock source BCLK of system clock generator will switch between XT clock and CF clock according to the user s program When the halt and stop instructions are executed the clock source BCLK will switch to XT clock automatically The XT clock provides the clock to the pre divider timer I O port chattering prevention and LCD circuitry in this option 23 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual Halt Halt Halt mode Slow mode Slow Fast mode XTOSC active XTOSC active lt XTOSC active CFOSC stop HALT CFOSC stop EL CFOSC active released Stop released Reset Stop release Reset Reset state Reset Stop mode XTOSC active H XTOSC stop Power on reset Reset pin reset Watchdog timer reset Key reset CFOSC stop CFOSC stop State Diagram of Dual Clock Option was shown on above figure After executing FAST instruction the system clock generator will hold 12 CF clocks after the CF clock oscillator starts up and then switches CF clock to BCLK This will prevent the incorrect clock from delivering to the
56. reset to 0 and the corresponding HRF flag will be cleared the interrupt enable flags IEF must be set again in the interrupt service routine as required 3 2 RESET FUNCTION TM87POX contains four reset sources power on reset RESET pin reset port reset and watchdog timer reset When reset signal is accepted TM87POX will generate a time period for internal reset cycle and there are two types of internal reset cycle time could be selected by option the one is PH15 2 and the other is PH12 2 TM87P08 Only 11 011 dox 11111 11111111 t Hold 16384 or 2048 clocks for l Normal operation gt internal reset cycle Internal reset cycle time is PH15 2 OPTION table Option name Selected item RESET TIME 1 PH15 2 In this option the reset cycle time will be extended 16384 clocks clock source comes form pre divider long at least Internal reset cycle time is PH12 2 TM87P08 Only OPTION table Option name Selected item RESET TIME 2 PH12 2 In this option the reset cycle time will be extended 2048 clocks clock source comes form pre divider long at least 56 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 3 2 1 RESET PIN RESET When level is applied to the reset pin the reset signal will issue Built in a pull down resistor on this pin
57. specified by SCA is accepted X1 1 The IEF1 is set so that interrupt 1 underflow from timer 1 is accepted X2 1 The IEF2 is set so that interrupt 2 the signal change at the INT is accepted The IEF3 is set so that interrupt 3 overflow from the predivider is accepted 4 1 The IEF4 is set so that interrupt 4 underflow from timer 2 is accepted X6 1 IEF6 is set so that interrupt 6 overflow from the RFC counter is accepted XT is reserved TM87P08 Only SHE X TM87R02 TM87P02 TM87P04 TM87P08 Function Set Reset halt release enable flag Description 6 1 The HEF6 is set so that the halt mode is released by counter overflow XT is reserved TM87P08 Only SRE X 87 2 87 2 87 4 87 8 Function Set Reset stop release enable flag Description 3 1 The SRF3 is set so that the stop mode is released by the signal changed IOD port 4 1 The SRF4 is set so that the stop mode is released by the signal changed on IOC port 5 1 The SRF5 is set so that the stop mode is released by the signal changed on INT pin SRF7 is set so that the stop mode is released by the signal changed on Key scan port X6 X3 0 is reserved TM87P08 Only FAST TM87R02 TM87P02 TM87P04 TM87P08 Function Switches the system clock to CFOSC clock Description Starts up the CFOSC high speed osc and then switches t
58. system clock in the start up duration of the fast clock oscillator CF 41 clock XT clock FAST so HOLD 12 CF CLOCKS This figure shows the System Clock Switches from Slow to Fast After executing SLOW instruction the system clock generator will hold 2 XT clocks and then switches XT clock to BCLK 24 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual CF Fast clock stops operating clock XT clock SLOW BCLK This figure shows the System Clock Switches from Fast to Slow 2 2 3 2 SINGLE CLOCK OPTION table For Fast clock oscillator only Option name Selected item CLOCK SOURCE 1 FAST ONLY For slow clock oscillator only Option name Selected item CLOCK SOURCE 2 SLOW ONLY The operation of the single clock option is shown in the following figure Either XT or CF clock may be selected by option in this mode The FAST and SLOW instructions will perform as the NOP instruction in this option The backup flag BCF will be set to 1 automatically before the program enters the stop mode This could ensure the Crystal oscillator would start up in a better conditio
59. technology inc Rev 1 0 2006 04 11 Preliminary Symbol Description TM87P0X User s Manual Symbol Description Symbol Description Content of Register D Immedia te Data Accumulator D of Immediate Data AC n Content of Accumulator bit n PC Program Counter AC B Complement of content of Accumulator CF Carry Flag X Address of program or control data ZERO Zero Flag Rx Address X of data RAM WDF Watch Dog Timer Enable Flag Rx Bit n content of Rx 7 segment decoder for LCD Ry Address Y of working register BCLK ISystem clock for instruction of data RAM specified by HL IEFn Interrupt Enable Flag BCF Backup flag HRFn Release Flag Generic Index address register HEFn HALT Release Enable Flag Content of generic Index address register Lz Address of LCD PLA Latch L Content of lowest nibble Index register SRFn STOP Release Enable Flag Content of middle nibble Index register SCFn Condition Flag QU Content of highest nibble Index register Cch Clock Source of Chattering prevention ckt T HL_ Address of Table ROM Cfq Source of Frequency Generator H T HL High Nibble content of Table ROM SEFn Switch Enable Flag L T HL Low Nibble content of Table ROM FREQ Frequency Generator setting Value TMR Timer Overflow Release Flag CSF Clock Sourc
60. working register specified by Ry is loaded to AC and data memory specified by Rx TM87P08 Rx lt R HL The content of data memory specified by HL is loaded to AC and data memory specified by Rx TM87P08 AC Rx lt R HL HL HL 1 The content of the data memory specified by HL is loaded to AC and the data memory specified by Rx The content of the index register HL will be incremented automatically after executing this instruction TM87R02 TM87P02 TM87P04 TM87P08 Rxn ACn lt Rx n 1 AC n 1 Rx3 0 The Rx content is shifted right and 0 is loaded to the MSB The result is loaded to the AC 0 gt Rx3 gt Rx2 gt Rx1 gt Rx0 gt TM87R02 TM87P02 TM87P04 TM87P08 Rxn ACn lt Rx n 1 AC n 1 Rx3 1 The Rx content is shifted right and 1 is loaded to the MSB The result is loaded to the AC 1 gt Rx3 gt Rx2 gt Rx1 gt Rx0 gt TM87R02 TM87P02 TM87P04 TM87P08 Rxn ACn lt Rx n 1 AC n 1 Rx0 ACO 0 The Rx content is shifted left and 0 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 lt 1 lt Rx0 0 101 tenx technology inc Rev 1 0 2006 04 11 Preliminary SL1 Rx Function Description MRA Rx Function Description MAF Rx Function Description TM87P0X User s Manual TM87R02 TM87P02 TM87P04 TM87P08 Rxn l
61. 100 1000 XXXX AC Rx Port D V 133 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual TM87P08 TM87P04 TMS87RO2 PC2 Instruction Machine Code Function Flag Remark Rx 0100 1010 AC Rx lt 5 51 B3 CF V B2 ZERO B1 No use No use MSB 0100 1011 XXXX AC Rx lt STS2 B3 SCF3 DPT V B2 SCF2 HRx 1 5 MSC 0100 1100 lt 5153 B3 SCF7 PDV B2 PH15 1 5 5 1 SCFA INT MCX 0100 1101 XXXX AC Rx lt STS3X SCF9 RFC B2 unused 1 5 6 2 0 55 8 5 MSD Rx 0100 1110 XXXX lt 5154 No use V B2 FROVF B1 WDF B0 CSF 580 Rx 0101 0000 ACn lt Rx n 1 V AC3Rx3 0 5 1 0101 0001 lt 1 1 SLO Rx 0101 0010 Rxn lt Rx n 1 0 8 0 0 511 0101 0011 Rxn lt Rx n 1 0 8 0 lt 1 DAA 0101 0100 0000 0000 AC BCD AC CF V DAA Rx 0101 0101 XXXX AC Rx BCD AC V DAA 0101 0101 1000 0000 AC HL lt BCD AC CF v X DAA HL 0101 0101 1100 0000 AC GHL lt BCD AC GF V X
62. 5 102 70 30 00301083 878 1053 45 COM7 DC7 OD7 1592 15 102 70 SEG31 IOB4 BZ 902 15 COM8 DC8 OD8 1762 55 102 70 lOC1 KI1 763 45 DC9 OD9 1907 45 102 70 IOC2 KI2 616 25 SEG1 K1 2038 55 102 70 IOC3 KI3 496 25 SEG2 K2 2182 75 102 70 IOC4 KI4 349 05 SEG3 K3 2320 15 102 70 IOD1 102 70 SEG4 K4 2587 30 256 50 IOD2 102 70 SEG5 K5 2587 30 400 70 IOD3 102 70 SEG6 K6 2587 30 538 10 IOD4 102 70 SEG7 K7 2587 30 682 30 40 102 70 SEG8 K8 2587 30 819 70 SEG41 102 70 SEG9 K9 2587 30 963 90 TEST 102 70 12 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 1 6 PIN DESCRIPTION TM87P04 LCD supplies voltage and positive supply voltage Connect 3 0V battery positive pin to 1 Above 4 0V is need to VDD2 for Serial Program Read Mode B pin LSI reset request signal with internal pull down resistor Control Signal for Serial Program Read Mode Reset Time can select PH15 2 or PH12 2 by option Reset Type can select Level or Pulse by option EE pin for external INT request signal falling edge or rising edge triggered by option BEES pull down or pull up resistor is selected by option nes Serial Data for Serial Program Read Mode cm No Connected TIMB7RQ2 No Connected NA Above 11 5V is connected to VPP for Program Mode In Norma mode it must be connected to VDD2 Above 11 5V is connect
63. 50 CUP1 1 3 SEG24 IOA1 1387 50 CUP2 SEG25 IOA2 1272 50 COM1 SEG26 IOA3 1157 50 COM2 SEG27 IOA4 1042 50 COM3 1 SEG28 927 50 4 N C SEG29 812 50 SEG1 3 SEG30 IOB3 BZB 697 50 SEG2 IOB4 BZ 582 50 SEG3 IOC1 467 50 SEG4 IOC2 352 50 SEG5 IOC3 237 50 SEG6 122 50 SEG7 70 00 SEG8 I 70 00 SEG9 1 70 00 SEG10 70 00 SEG11 2 70 00 SEG12 x 70 00 SEG13 70 00 SEG14 70 00 z 11 technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual TM87P08 Name X XIN 102 70 1732 00 SEG10 K10 2587 30 XOUT 102 70 1610 20 SEG11 K11 2587 30 FRIN 102 70 1495 20 SEG12 K12 2587 30 FROUT 102 70 1373 40 SEG13 K13 2587 30 CFIN 102 70 1258 40 SEG14 K14 2587 30 CFOUT 102 70 1136 60 SEG15 K15 2587 30 GND 102 70 1018 85 SEG16 K16 2587 30 RESET 102 70 901 10 SEG17 2587 30 INT 102 70 779 10 SEG18 2587 30 VDD1 102 70 662 00 SEG19 2587 30 VDD 2 102 70 547 00 SEG20 2587 30 VPP 102 70 341 50 SEG21 2587 30 VDD3 145 60 106 70 SEG22 2301 15 283 05 102 70 SEG23 2156 95 CUP2 425 35 102 70 SEG24 IOA1 CX 1987 05 COM1 569 75 102 70 SEG25 IOA2 RR 1842 85 2 740 15 102 70 SEG26 IOA3 RT 1640 45 910 55 102 70 SEG27 lIOA4 RH 1496 25 4 1080 95 102 70 SEG28 IOB1 1326 35 5 5 5 1251 35 102 70 SEG29 IOB2 1182 15 COM6 DC6 OD6 1421 7
64. 8 DC9 and DC30 to be defined as CMOS type DC output or P open drain DC output ports by option In these cases it is possible to use some LCD driver output pins as DC output and the rest of the LCD driver output pins as LCD drivers Refer to 4 3 4 The configurations of CMOS output type and P open drain type are shown below When the LCD driver output pins SEG are defined as DC output ports the output data on those ports will not be affected when the program enters stop mode or LCD turn off mode VDD VDD zl SEG P SEG GND Figure 5 1 CMOS Output Type Figure 5 2 P Open Drain Output Type Only unused COM and SEG pads can be defined as DC output pins The COM pad sequence for LCD drivers cannot be interrupted when the COM pads are defined as DC output ports For example when the LCD lighting system is specified as 1 4 duty the COM pad used for LCD driver must be COM1 COM4 Each of COM6 COM8 DC9 pad be defined as DC output ports 85 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 4 3 SEGMENT PLA CIRCUIT FOR LCD DISPLAY 4 3 1 PRINCIPLE OF OPERATION OF LCD DRIVER SECTION The explanation below explains how the LCD driver section operates when the instructions are executed Table ROM AC amp RAM data be memory Data decoder Data bus Strobe data Decoder of sropelOio related L4 instruction TM87P08 Only HL gt
65. A SRE AS 9 3 BIS ZX tenx technology inc 87 Include 87 2 4 Bit Micro Controller with LCD Driver User s Manual tenx technology inc tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual CONTENTS CHAPTER 1 General Description 3 Tet General Descriptio Ni eee I EO 3 12 ya ahay 3 ESCH 45 21 5211 6 1 4 Pad DIagFamOo eee o eo deseo 7 1 5 Pau Coordinate 9 laps Pin DOSCPIDBOIS 63 ois Co UN SE NA uN Qusa eu es 12 le C haracterzatOfni ea anan s 14 CHAPTER 2 TM87POX Internal System Architecture 17 ZA OWE Supply 9 teet bi 17 2 2 System CIOGK xax xc eeu I Ce re I AR Su a AREAS AE REA 18 2 3 Program Counter PO dois it Da added d do dag nnd 25 2 4 Program Table Memory 9 26 2 5 Index Address Register
66. AC Binary adds the contents of HL and AC the result is loaded to AC The result will not affect the carry flag CF HL indicates an index address of data memory TM87P08 AC lt HL AC HL HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory 107 tenx technology inc Rev 1 0 2006 04 11 Preliminary Rx Function Description HL Function Description ADN HL Function Description AND Rx Function Description AND HL Function Description AND HL Function Description AND Rx Function Description TM87P0X User s Manual TM87R02 TM87P02 TM87P04 TM87P08 AC Rx lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and data memory Rx The result will not affect the carry flag CF TM87P08 HL HL AC Binary adds the contents of HL and AC the result is loaded to AC and the data memory HL The result will not affect the carry flag CF HL indicates an index address of data memory TM87P08 AC HL HL AC HL 1 Binary adds the contents of HL and AC the result is loaded to AC and the data memory QHL The
67. D 1 8 Duty DC5 OD5 DC6 OD6 DC7 OD7 DBUSA DBUSB DBUSC DC8 OD8 DC9 OD9 DC30 0D30 DBUSD DBUSE DBUSH 92 DC9 OD9 DC30 OD30 DBUSE DBUSH tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual Chapter 5 Detail Explanation of TM87POX Instructions Before using the data memory it is necessary to initiate the content of data memory because the initial value is unknown The working registers are part of the data memory RAM and the relationship between them can be shown as follows The absolute address of working register Rx Ry 70H Note Ry Address of working register the range of addresses specified by Rx is from 70H to 7FH Rx Address of data memory the range of addresses specified by Ry is from OH to FH Ry use for LCD instruction only 7 Address of working registers Absolute address of data memory specified by Ry Rx Lz represents the address of the latch of LCD PLA the address range specified by Lz is from to OFH TM87P04 or 1FH TM87P08 5 1 INPUT OUTPUT INSTRUCTIONS LCT Lz Ry Function Description LCB Lz Ry Function Description LCP Lz Ry Function Description TM87R02 TM87P02 TM87P04 TM87P08 LCD latch Lz lt data decoder lt Ry The working register contents specified by Ry are loaded to the LCD latch specified by Lz through the data decoder
68. D PLA circuit Such as LCT LCB LCP 2 9 ACCUMULATOR AC The accumulator AC is a register that plays the most important role in operations and controls By using it in conjunction with the ALU Arithmetic and Logic Unit data transfer between the accumulator and other registers or data memory can be performed 2 10 ALU Arithmetic and Logic Unit This is a circuitry that performs arithmetic and logic operation The ALU provides the following functions Binary addition subtraction INC DEC ADC SBC ADD SUB ADN ADCI SBUI ADNI 32 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Logic operation AND EOR OR ANDI EORI ORI Shift SR0 SR1 SL0 SL1 Decision JB0 JB1 JB2 JB3 JC JNC JZ and JNZ BCD operation DAA DAS 2 11 HEXADECIMAL CONVERTS TO DECIMAL HCD Decimal format is another number format for TM87P0X When the content of the data memory has been assigned as decimal format it is necessary to convert the results to decimal format after the execution of ALU instructions When the decimal converting operation is processing all of the operand data including the contents of the data memory RAM accumulator AC immediate data and look up table should be in the decimal format or the results of conversion will be incorrect Instructions DAA DAA DAA HL can convert the data from hexadecimal to decimal format after any addition operation The conversion rules are shown i
69. E 87 8 Only 3 5 3 1 Chattering Prevention Function and Halt Release The port IOC is capable of preventing high low chattering of the switch signal applied on IOC1 to IOCA pins The chattering prevention time can be selected as PH10 32ms PH8 8ms or PH6 2ms by executing SCC instruction and the default selection is PH10 after the reset cycle When the pins of the IOC port are defined as output the signals applied to the output pins will be inhibited for the chattering prevention function The following figure shows the organization of chattering prevention circuitry IEFO Interrupt Edge HRFO request detect edge dectect amp chattering SPC 1 SPC 2 SPC 4 SPC 8 IOC1 IOC2 IOC3 _ chattering PH10 f 8 prevention PH6 clcok SCC n intruction request C 1 Interrupt accept SCA intruction Note The default prevention clock is PH10 This chattering prevention function works when the signal at the applicable pin ex IOC1 is changed from L level to H level or from H level to L level and the remaining pins ex IOC2 to IOCA are held level When the signal changes at the input pins of IOC port specified by the SCA instruction occur and keep the state for at least two chattering clock PH6 PH8 PH10 cycles the control circuit at the input pins will
70. Each is MUXed with IOB3 and IOB4 by option respectively BZB and BZ pins are versatile output pins with complementary output polarity When buzzer output function combined with the clock source comes from the frequency generator this output function may generate melody sound effect or carrier output of remote control OPTION table Option name Selected item SEG30 DC30 IOB3 BZB 3 BZB SEG31 IOB4 BZ 3 BZ 05 MUX ALM X X8 X7 X6 This figure shows the organization of the buzzer output 3 4 1 BASIC BUZZER OUTPUT The buzzer output BZ BZB is suitable for driving a transistor for the buzzer with one output pin or driving a buzzer with BZ and BZB pins directly It is capable of delivering a modulation output in any combination of one signal of FREQ PH3 4096Hz PH4 2048Hz PH5 1024Hz and multiple signals of PH10 32Hz PH11 16Hz PH12 8Hz PH13 4Hz PH14 2Hz PH15 1Hz The ALM instruction is used to specify the combination The higher frequency clock is the carrier of modulation output and the lower frequency clock is the envelope of the modulation output 63 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual Note 1 The high frequency clock source should only be one of PH3 PH4 PH5 or FREQ and the lower frequency may be any all of the combinations from PH10 15 2 The frequencies in corresponding to the input clock of the pre divider P
71. FUNCTION There are 7 interrupt resources 3 external interrupt factors and 4 internal interrupt factors When an interrupt is accepted the program in execution is suspended temporarily and the corresponding interrupt service routine specified by a fixed address in the program memory is called The following table shows the flag and service of each interrupt Table 3 1 Interrupt information Interrupt IOC TMR1 TMR2 A HBS INT pin matrix counter source port underflow overflow underflow overflow 010H 014H OH 020 028 vector IEF2 IEF0 IEF1 IEF3 IEF4 IEF5 IEF6 enable flag Interru pt e gth 2nd 1 st grd 7 ath priority Interrupt request flag Interrupt 2 Interrupt 0 Interrupt 1 Interrupt 3 Interrupt 4 Interrupt 5 Interrupt 6 TM87P08 Only The following figure shows the Interrupt Control Circuit 52 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Interrupt 0 Specified signal change at IOC or IOD port Priority control circuit Interrupt 1 Tim er TM underflow Interrupt request signal Specified signal Interrupt 2 change at INT pin Interrupt vector address generator Interrupt 3 Predivider overflow Interrupt 4 TM2 underflow Specified signal enable at Key matrix Scan
72. H0 is 32768Hz 3 The BZ and BZB pins will output DC0 after the initial reset Example Buzzer output generates a waveform with 1KHz carrier and PH15 PH14 envelope LDS 20h ALM 70h Output the waveform In this example the BZ and BZB pins will generate the waveform as shown in the following figure PH15 1HZ 1 a 5 1 2 BZ BZ m e qp 3 4 2 THE CARRIER FOR REMOTE CONTROL If buzzer output combines with the timer and frequency generator the output of the BZ pin may deliver the waveform for the IR remote controller For remote control usage the setting value of the frequency generator must be greater than or equal to 3 and the ALM instruction must be executed immediately after the FRQ related instructions in order to deliver the FREQ signal to the BZ pin as the carrier for IR remote controller Example SHE 2 Enable timer 1 halt release enable flag TMSX 3Fh Setvalue for timer 1 is 3Fh and the clock source is PHY SCC 40h Setthe clock source of the frequency generator as BCLK FRQX 2 3 FREQ BCLK 4 2 setting value for the frequency 64 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual generator is 3 and duty cycle is 1 2 ALM 1COh signal is outputted This instruction must be executed after the FRQ related instructions HALT Wait for the halt re
73. I OB VOD I OD port chattering clock Frequency generator clock source and duty cycle Resistor frequency converter LCD driver output Timer 1 2 Watchdog timer PORT I OA I OD Cfq WDT Clock source BCLK Notes PH3 the 3rd output of predivider PH10 the 10th output of predivider option can unlighted all of the LCD output TM87P08 Only 3 2 3 Port RESET 87 08 Only Address 000 1 Li B option DC 0 1 with pull down resistor Input mode PH10 PHO duty cycle is 1 4 output is inactive Inactive RR RT RH output 0 All lighted option Inactive Reset mode WDF 0 XT clock slow speed clock in dual clock option Key reset function is selected by option When IOC port is in used the 0 signal applied to all these pins that had be set as input mode in the same time reset signal is delivered OPTION table IOC or KI pins are used as key reset Option name Selected item IOC1 FOR KEY RESET 1 USE 2 FOR KEY RESET 1 USE IOC3 FOR KEY RESET 1 USE IOC4 FOR KEY RESET 1 USE 58 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual IOC pins aren t used as key reset Option name Selected item 1 1 FOR KEY RESET 2 NO USE 2 FOR KEY RESET 2 NO USE 1 FOR KEY RESET 2 NO USE 1 FOR KEY RESET 2 NO USE The f
74. LCD drivers will automatically switch to the GND state to avoid DC voltage bias on the LCD panel 88 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual 4 3 2 Relative Instructions 1 LCT Lz Ry TM87R02 TM87P02 TM87P04 TM87P08 Decodes the content specified in Ry with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz 2 LCB Lz Ry TM87R02 TM87P02 TM87P04 TM87P08 Decodes the content specified Ry with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz DBUSA to DBUSH are all set to 0 when the input data of the data decoder is 0 3 LCD Lz HL TM87P08 Transfers the table data specified by HL directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown in table 2 32 4 LCP Lz Ry TM87R02 TM87P02 TM87P04 TM87P08 The data the RAM and accumulator are transferred directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown below 5 LCT Lz HL TM87P08 Decodes the index RAM data specified in HL with the data decoder and transfers DBUSA H to the LCD latch specified by Lz 6 LCB Lz HL TM87P08 Decodes the index RAM data specified in HL with the data decoder and transfers the DBUSA H to the LCD latch specified by Lz The to DBUSH are all set to 0 when the input data of the data decoder is 0 7 LCP Lz HL TM87P08
75. OR AC V Xx HL lt HL 1 ADCI RyD 0011 0000 DDDD YYYY lt Ry D CF V ADCI JRyD 0011 0001 DDDD YYYY AC Ry lt Ry D CF V SBCI Ry D 0011 0010 DDD YYYY AC lt Ry DB V SBCI RyD 0011 0011 DDD YYYY AC Ry Ry DB CF V ADDI RyD 0011 0100 Dopp AC Ry D V ADDI RyD 0011 0101 Dopp IAC Ry lt Ry D 5 SUBI Ry D 0011 0110 DDD YYYY lt Ry DB 1 V SUBI RyD 0011 0111 DDD YYYY AC Ry lt Ry 0 1 V ADNI Ry D 0011 1000 DDD Yyyy AC lt Ry D V ADNI IRyD 0011 1001 DDDD YYYY lt Ry D V ANDI RyD 0011 1010 DDD YYYY Ry ANDD V ANDI RyD 0011 1011 DDD YYvv AC Ry Ry ANDD V EORI RyD 10011 1100 DDD YYYy AC lt Ry EOR D V EORI RyD 0011 1101 DDDD lt Ry EOR D V ORI 0011 1110 Dopp YYYY lt Ry OR D ORI RyD 00111111 DDD YYYY AC Ry lt Ry ORD INC 0100 0000 XXXX lt Rx 1 CF V INC 0100 0000 1000 0000 AC HL lt GHL 1 CF V x INC 0100 0000 1100 0000 AC HL lt HL 1 CF V x HL lt HL 1 DEC Rx 0100 0001 XXXX AC Rx lt Rx 1 V DEC 0100 0001 1000 0000 lt QHL 1 V DEC HL 0100 0001 1100 0000 AC HL lt 1 V HL lt HL 1 IPA 0100 0010 XXXX AC Rx Port A V IPB 0100 0100 XXXX AC Rx Port B V IPC 0100 0111 XXXX lt Port C V IPD 0
76. Output L Voltage 2 Vol4f lol 1uA 4 0 2 V Output H Voltage Voh3g loh 10uA 3 COM n 2 2 V Voh4g 100 4 3 8 V Output M Voltage Vom3g_ lol n 10uUA 3 1 0 1 4 V Vom4g_ lol n 10uA 4 COM n 1 8 2 2 Output L Voltage Vol3g 10 3 0 2 V Vol4g lol 10uA 4 0 2 V 1 3 Bias display Mode Output H Voltage loh 1uA 3 3 4 V Vohdi 1 84 5 8 V Output M1 Voltage lol h 10uA 3 1 0 1 4 V Vom14i_ lol n 10UA 4 SEG n 1 8 2 2 n Vom23i lol h 10uA 3 2 2 2 6 V Output M2 Voltage Vom24i_ lol n 10uA 4 3 8 4 2 Output L Voltage Vol lol 1uA 3 0 2 V Vol4i lol 1uA 4 0 2 V Output H Voltage vols loh 10UA 3 3 4 Voh4j 100 4 5 8 Output M1 Voltage lol h 10uA 3 1 0 1 4 V Vom14j lol n 10uA 4 COM n 1 8 2 2 V m Vom23j 101 100 3 2 2 2 6 V Output M2 Voltage Vom24j_ lol n 10uA 4 3 8 4 2 lol 10uA 1 Output L Voltage 019 Y Vol4j lol 100A 4 0 2 V 18 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual Chapter 2 TM87P0X Internal System Architecture 2 1 Power Supply TM87P08 could operate at Li and ExtV 2 types supply voltage all of these operating types are defined by option TM87P02 TM87P04 could operate at Li type voltage The power supply circuitry also generated the necessary voltage level to drive the LCD panel with different bi
77. P08 AC HL HL AC HL 1 Binary Ors the contents of HL and AC the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory 110 tenx technology inc Rev 1 0 2006 04 11 Preliminary ADCI Ry D Function Description ADCI Ry D Function Description SBCI Ry D Function Description SBCI Ry D Function Description ADDI Ry D Function Description 87 User s Manual TM87R02 TM87P02 TM87P04 TM87P08 lt D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC The carry flag CF will be affected D 0H FH TM87R02 TM87P02 TM87P04 TM87P08 Ry D CF D represents the immediate data Binary ADDs the contents of Ry D and CF the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH TM87R02 TM87P02 TM87P04 TM87P08 AC Ry D CF D represents the immediate data Binary subtracts the CF and immediate data D from the working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH TM87RO02 TM87P02 TM87P04 TM87P08 AC Ry Ry D CF D represents the immediate data Binary subtracts the CF and
78. R CTL The control register CTL comes in 4 types control register 1 1 to control register 4 CTLA 2 15 1 CONTROL REGISTER 1 CTL1 The control register 1 CTL 1 being a 1 bit register 1 Switch enable flag 4 SEF4 Stores the status of the input signal change at pins of IOC set in input mode that causes the halt mode or stop mode to be released 2 Switch enable flag 3 SEF3 Stores the status of the input signal change at pins of IOD set in input mode that causes the halt mode or stop mode to be released Executed the SCA instruction may set or reset these flags The following table shows Bit Pattern of Control Register 1 1 Bit 4 Bit 3 Switch enable flag 4 SEF 4 Switch enable flag 3 SEF 3 Enables the halt release caused by the Enables the halt release caused by the signal change on IOC port signal change on IOD port Write only Write only TM87P08 Only The following figure shows the organization of control register 1 CTL1 HALT loc Released SEF4 Request SCA 10h Interrupt 0 request SCA 8h Interrupt accept 2 15 1 1 The Setting for Halt Mode 46 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual If the SEF4 is set to 1 the signal changed on IOC port will cause the halt mode to be released and set SCF1 to 1 Because the input signal of IOC port were ORed so it is necessary to keep the unchanged input signals at 0 state and only o
79. Reset V X4 WDT Reset X1 BCF Reset 0 CF Reset ALM X 1111 110X X8 7 6 111 FREQ X8 7 6 100 DC1 X8 7 6 011 PH3 X8 7 6 010 PH4 X8 7 6 001 PH5 X8 7 6 000 DCO 5 0 PH15 10 SF2 X 1111 1110 0000 X3 Enable INT powerful P ull low V X2 Close all Segments X1 Dis ENX Set X0 Reload 2 Set RF2 X 1111 1110 1000 XXXX X3 Disable INT powerful Pull low V X2 Release Segments X1 Dis ENX Reset X0 Reload 2 Reset HALT 1111 1111 0000 0000 Halt Operation 1111 1111 1000 0000 Stop Operation TM87P08 Only 139 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Appendix TYPICAL APPLICATION CIRCUIT This application circuit is simply an example and is not guaranteed to work LCD Panel 3 58MHz Ceramic COM1 4 SEG1 23 SEG40 41 15P H XN 32 768KHz z Crystal 3 3 b 0 10 CUP2 RH VDD3 aX VPP T ud VDD 2 AAA RR 50141 1 P 21010 GND e e e mor TM87P 0X I RESET External INT INT 10 Port 108 0 00 Choke gt Buzzer SEG1 16 1 K4 BZ BZB Key Scaning TM87P08 Only Key Matrix 1 3 Bias 1 4Duty 140 tenx
80. S3 After power on reset the default clock source of TMR1 is PH3 If watchdog reset occurred the clock source of TMR1 will still keep the previous selection 34 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual The following table shows the definition of each bit in TMR1 instructions OPCODE _ Select clock TMSX X TMSRx 0 2 ACO Rx3 Rx2 Rx1 Rx0 TMS QHL bit7 bit6 bits Bit4 bits bit2 bit bito The following table shows the clock source setting for TMR1 Notes 1 When the TMR1 clock is PH3 TMR1 set time Set value error 8 1 fosc KHz ms 2 When the TMR1 clock is PH9 TMR1 set time Set value error 512 1 fosc KHz ms 3 When the TMR1 clock is PH15 TMR1 set time Set value error 32768 1 fosc KHz ms 4 When the TMR1 clock is PH5 TMR1 set time Set value error 32 1 fosc KHz ms 5 When the TMR1 clock is PH7 TMR1 set time Set value error 128 1 fosc KHz ms 6 When the TMR1 clock is PH11 TMR1 set time Set value error 2048 1 fosc KHz ms 7 When the TMR1 clock is PH13 TMR1 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 lt error lt 1 fosc Input of the predivider PH3 The 3rd stage output of the predivider PH5 The 5th stage output of the predivider PH7 The 7th stage output of
81. The data of the index RAM and accumulator AC are transferred directly to DBUSA through DBUSH without passing through the data decoder The mapping table is shown below Table 2 4 The mapping table of LCP and LCD instructions _ DBUSA DBUSB DBUSC DBUSD DBUSE DBUSF DBUSG DBUSH 5 SF2 4h 87 2 87 2 87 4 87 8 Turns off the LCD display 6 RF2 4h TM87R02 TM87P02 TM87P04 TM87P08 Turns on the LCD display 4 3 3 CONCRETE EXPLANATION TM87P08 Only Each LCD driver output corresponds to the LCD 1 8 duty panel and has 8 latches refer to Figure 4 3 Sample Organization of Segment PLA Option Since the latch input and the signal to be applied to the clock strobe are selected with the segment PLA the combination of segments in the LCD driver outputs is fixed In other words one of the data decoder outputs from DBUSA to DBUSH is applied to the latch input L and one of the PSTBO to PSTB 1Fh outputs is applied to clock CLK 89 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual TM87P08 provide a flash type instruction to update the LCD pattern When the LCTX D LCBX D LCPX D and LCDX D instructions are executed the pattern of DBUS will be outputted to the 16 latches Lz specified by D simultaneously D Specified range of latched 00 Lz 00h OFh 01 Lz 10h 1F
82. as Shown below are the connection diagrams for 1 2 bias 1 3 bias application 2 1 1 LIBATTERY and ExtV POWER SUPPLY Operating voltage range 2 4V 3 6V Li B 2 4 5 25V ExtV For different LCD bias application the connection diagrams are shown below 2 1 1 1 1 2 BIAS Application Circuit TM87P04 lt gt PP TM87PO8 CUPT on CuP2 _ VDD3 VDD2 Internal VDD1 Logic Q luF 0 3 0V GND OPTION table Option name Selected item LCD BIAS 2 1 2 BIAS Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the oscillator circuit becomes large in driver size When the backup flag is set the operating current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 2 17 19 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual 2 1 2 2 1 3 BIAS TM87P04 _ Application Circuit TM87P08 Internal Logic Q luF 0 luF 49 OPTION table Option name LCD BIAS 3 1 3 BIAS Selected item Note 1 The input output ports operate between GND and VDD2 Note 2 The backup flag BCF is set in the initial clear mode When the backup flag is set the oscillator circuit becomes large in driver size When the backup flag is set the operating
83. ased request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF7 will be set to 1 X7X5X4 000 this setting each scanning cycle only checks one specified column K1 K16 on the key matrix The specified column is defined by the setting of Xs Xo Xo 0000 activates the K1 column 97 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual Xs Xo 0001 activates the K2 column Xo 1110 activates the K15 column Xo 1111 activates the K16 column X7Xs5X4 001 in this setting all of the matrix columns K1 K16 will be checked simultaneously in each scanning cycle Xs Xo are not a factor X7X5X4 010 in this setting the key matrix scanning function will be disabled X3 Xo are not a factor X7X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of 0 activates the K1 K8 columns simultaneously Xs 1 activates the K9 K16 columns simultaneously Xo are not a factor X7X5X4 110 in this setting each scanning cycle checks four specified columns on the key matrix The specified columns are defined by the setting of and X X3X2 00 activates the K1 K4 columns simultaneously X3X2 01 activates the K5 K8 columns simultaneously X3X2 10 activates the K9 K12 columns simultaneously X3X2 11 activa
84. ch flag X4 1 Enable low battery detected function X3 1 Enable INT powerful pull low X2 1 Disables the LCD segment output X1 1 Sets the DED flag Refer to 2 12 3 for detail 1 Enables the re load function of timer 2 X7 6 15 reserved TM87R02 TM87P02 TM87P04 TM87P08 Resets flag Description of each flag X3 1 Disable INT powerful pull low X2 1 Enables the LCD segment output X1 1 Resets the DED flag Refer to 2 12 3 for detail X0 1 Disables the re load function of timer 2 XT 4 is reserved TM87R02 TM87P02 TM87P04 TM87P08 Pulse control The pulse corresponding to the data specified by X is generated 1 Halt release request flag HRFO caused by the signal at I O port C is reset X1 1 Halt release request flag HRF1 caused by underflow from the timer 1 is reset and stops the operating of timer 1 TM1 X2 1 Halt or stop release request flag HRF2 caused by the signal change at the INT pin is reset 1 Halt release request flag HRF3 caused by overflow from the predivider is reset X4 1 Halt release request flag HRF4 caused by underflow from the timer 2 is reset and stops the operating of timer 2 TM2 X5 1 Halt release request flag HRF5 caused by the signal change to L on KI1 4 in scanning interval is reset X6 1 Halt release request flag HRF6 caused by overflow from the RFC counter is reset X8 1 The last 5 bits of the prediv
85. cified by the index address register HL The data width could be 8 bits or 4 bits which depends on the different usage Refer to the explanation of instruction chapter 29 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 2 5 INDEX ADDRESS REGISTER TM87P08 Only This is a versatile address pointer for the data memory RAM and table ROM TROM The index address register HL is a 12 bit register and executing MVU MVH and MVL instructions can modify the contents of the register Executed MVL instruction will load the content of specified data memory to the lower nibble of the index register L In the same manner executed MVH and MVU instructions will load the contents of the data RAM Rx to the higher nibble of the register H and U respectively U register H register L register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit3 Bit2 Bit1 BitO IDBF11 IDBF10 IDBF9 IDBF8 IDBF7 IDBF6 IDBF5 IDBFA IDBF3 IDBF2 IDBF1 IDBFO The index address register can specify the full range addresses of the table ROM and data memory bit3 M index Rx addressing bito DATA RAM bit3 MVH bitO TABLE ROM index addressing This figure shows the diagram of the index address register 2 6 STACK REGISTER STACK Stack is a special design register following the first in last out rule It is used to save the contents of
86. circuit sound circuit 1 port chattering prevention circuit and LCD driver output circuits are in operation If the timer has started operating the timer counter still operates in the halt mode After the HALT instruction is executed and no halt release signal SCF1 SCF3 HRF1 6 is delivered the CPU enters the halt mode The following 3 conditions are available to release the halt mode 1 An interrupt is accepted When an interrupt is accepted the halt mode is released automatically and the program will enter halt mode again by executing the RTS instruction after completion of the interrupt service When the halt mode is released and an interrupt is accepted the halt release signal is reset automatically 2 The signal change specified by the SCA instruction is applied to port IOC SCF1 IOD SCF3 3 The halt release condition specified by the SHE instruction is met HRF1 HRF6 When the halt mode is released in either 2 or 3 it is necessary that the MSB MSC or MCX instruction is executed in order to test the halt release signal and that the PLC instruction is then executed to reset the halt release signal HRF 49 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual Even when the halt instruction is executed in the state where the halt release signal is delivered the CPU does not enter the halt mode 2 17 BACK UP FUNCTION TM87POX provides back up mode to avoid system malfunc
87. content of the index register HL will be incremented automatically after executing this instruction The result will not affect the carry flag CF HL indicates an index address of data memory TM87R02 TM87P02 TM87P04 TM87P08 AC Rx amp AC Binary ANDs the contents of Rx and AC the result is loaded to AC TM87P08 AC lt HL amp AC Binary ANDs the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory TM87P08 AC lt Q HL 8 AC HL HL 1 Binary ANDs the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory TM87R02 TM87P02 TM87P04 TM87P08 AC Rx lt Rx Binary ANDs the contents of Rx and AC the result is loaded to AC and the data memory Rx 108 tenx technology inc Rev 1 0 2006 04 11 Preliminary AND HL Function Description AND HL Function Description EOR Rx Function Description EOR HL Function Description EOR HL Function Description EOR Rx Function Description EOR HL Function Description 87 User s Manual TM87P08 HL HL amp AC Binary ANDs the contents of HL and AC the result is loaded to AC and the data memory HL
88. current is increased Therefore the backup flag must be reset unless otherwise required For the backup flag refer to 2 17 2 2 SYSTEM CLOCK XT clock slow clock oscillator and CF clock fast clock oscillator compose the clock oscillation circuitry and the block diagram is shown below Stop Halt BCLK Fast instruction T1 T2 T3 T4 Sclk Slow instruction Clock switch System clock XT Clock circuit generator circuit Single clock option Dual clock option 20 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual The system clock generator provided the necessary clocks for execution of instruction The pre divider generated several clocks with different frequencies for the usage of LCD driver frequency generator etc The following table shows the clock sources of system clock generator and pre divider in different conditions O PH Initial state dual clock option Halt mode dual clock option XT clock XT clock Slow mode dual clock option XT clock XT clock Fast mode dual clock option XT clock CF clock 2 2 1 CONNECTION DIAGRAM OF SLOW CLOCK OSCILLATOR XT CLOCK This clock oscillation circuitry provides the lower speed clock to the system clock generator pre divider timer chattering prevention of IO port and LCD circuitry This oscillator will be disabled when the fast clock only option is selected by option or it will be active all the time after the initial reset
89. d interrupt requests have been processed 3 1 3 INTERRUPT SERVICING When an interrupt is enabled the program in execution is suspended and the instruction at the interrupt service address is executed automatically Refer to Table 3 1 In this case the CPU performs the following services automatically 1 As for the return address of the interrupt service routine the addresses of the program counter PC installed before interrupt servicing began are saved in the stack register STACK 2 The corresponding interrupt service routine address is loaded in the program counter PC The interrupt request flag corresponding to the interrupt accepted is reset and the interrupt enable flags are all reset When the interrupt occurs the TM87POX will follow the procedure below Instruction 1 In this instruction interrupt is accepted NOP 1M87POX stores the program counter data into the STACK At this time no instruction will be executed as with NOP instruction Instruction A program jumps to the interrupt service routine 55 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual Instruction B Instruction C RTS Finishes the interrupt service routine Instruction 1 re executes the instruction which was interrupted Instruction 2 Note If instruction 1 is halt instruction the CPU will return to halt after interrupt When an interrupt is accepted all interrupt enable flags are
90. d only Read only Read only Read only TM87P08 Only Start condition flag 1 SCF1 When the SCA instruction specified signal change occurs at port IOC to release the halt mode SCF 1 will be set Executing the SCA instruction will cause SCF1 to be reset to 0 Start condition flag 2 SCF2 When a factor other than port IOC causes the halt mode to be released SCF2 will be set to1 In this case if one or more start condition flags in SCF4 5 6 7 9 is set to 1 SCF2 will also be set to 1 simultaneously When all of the flags in SCF4 5 6 7 9 are clear start condition flag 2 SCF 2 is reset to 0 Note If start condition flag is set to 1 the program will not be able to enter halt mode 42 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual Start condition flag 3 SCF3 When the SCA instruction specified signal change occurs at port IOD to release the halt mode SCF3 will be set Executing the SCA instruction will cause SCF3 to be reset to 0 Backup flag This flag could be set reset by executing the SF 2h RF 2h instruction TM87P08 Only 2 14 3 STATUS REGISTER 3 STS3 When the halt mode is released caused by the start condition flag 2 SCF2 status register 3 STS3 will store the status of the factor in the release of the halt mode Status register 3 STS3 consists of 4 flags 1 Start condition flag 4 SCF4 Start condition flag 4 SCF4 is set to 1 when the signal cha
91. deliver the halt release request signal SCF1 At that time the chattering prevention clock will stop due to the delivery of SCF1 The SCF1 will be reset to O by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF1 has been set to 1 the halt release request flag 0 71 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual HRF0 will be delivered In this case if the port IOC interrupt enable mode IEF0 is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOC1 to the input data at the port IOC must be read into the RAM immediately after the halt mode is released 3 5 4 IOD PORT IOD1 IOD4 pins are MUXed with SEG36 SEG37 SEG38 and SEG39 pins respectively by option OPTION table Option name Selected item SEG36 IOD1 2 IOD1 SEG37 IOD2 2 IOD2 SEG38 IOD3 2 IOD3 SEG39 IOD4 2 IOD4 After the reset cycle the IOD port is set to input mode each bit of port can be set to input or output mode individually by executing SPD instructions Executing the OPD instruction outputs the contents of specified data memory locations to the pins set as output the other pins which are set as input will still remain the in the input mode Executing IPD instructions will store the signals applied to the IOD pins in the specified data memory locations
92. e Flag Ctm Clock Source of Timer P Program Page PDV RFOVF Overflow Flag STACK Content of stack RFC Resistor to Frequency counter TM1 1 RFC n Bit data of Resistor to Frequency counter TM2 2 141 tenx technology inc Rev 1 0 2006 04 11
93. e pull low device Description Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O was set as input mode The meaning of each bit of X X3 X2 X1 X0 is shown below 1 oss as output mode X2 0 oss as input mode C NGTPOS Only OPB Rx TM87R02 TM87P02 TM87P04 TM87P08 Function I OB lt Rx Description The contents of Rx are outputted to I OB port IPB Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Rx AC lt IOB Description The data of I OB port is loaded to AC and data memory Rx SPC X TM87R02 TM87P02 TM87P04 TM87P08 Function Defines the input output mode of each pin for IOC port and enables disables the pull low device or low level hold device Description Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X4 X3 X2 X1 X0 is shown below Bit pattern Bit pattern Enables all of the pull low and Disables all of the pull low and X4 1 disables the low level hold 4 0 enables the low level hold devices devices IOC4 as output mode X3 0 IOC4 as input mode X0 0 OPC Rx TM87R02 TM87P02 TM87P04 TM87P08 Function lt Rx Description The content of Rx is outputted to 1 port 96 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual
94. ed by data D 0 3 TM87R02 TM87P02 TM87P04 TM87P08 Defines the input output mode of each for port and enables disables the pull low device Sets the I O mode and turns on off the pull low device The input pull low device will be enabled when the I O pin was set as input mode The meaning of each bit of X X3 X2 X1 X0 is shown below Bit pattern Setting Bit pattern Setting X4 1 Enable IOA pulllowR X4 0 Disable IOA pull low R 3 1 OA4asoutputmode X3 0 4 mode X2 1 OA3asoutputmode 2 0 IOA3 as input mode 1 1 2 outputmode X1 0 2 as input mode 0 1 lOA1asoutputmode X0 0 input mode OPA Rx Function Description OPASRx D Function Description IPA Rx Function Description TM87R02 TM87P02 TM87P04 TM87P08 1 lt Rx The content of Rx is outputted to I OA port TM87R02 TM87P02 TM87P04 TM87P08 1 2 Rx IOA3 D IOA4 lt pulse Content of Rx is outputted to IOA port D is outputted to IOA3 pulse is outputted to 4 0 1 TM87R02 TM87P02 TM87P04 TM87P08 Rx AC IOA The data of I OA port is loaded to AC and data memory Rx 95 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual SPB X TM87R02 TM87P02 TM87P04 TM87P08 Function Defines the input output mode of each pin for IOB port and enables disables th
95. ed on the key matrix and then SCF7 will be set to 1 1 when HEF5 is set to 1 the HALT released request HRF5 will be set to 1 after each scanning cycle regardless of key depression and then SCF7 will be set to 1 X7Xs5X4 000 in this setting each scanning cycle only checks one specified column K1 K16 on the key matrix The specified column is defined by the setting of Xo Xo 0000 activates K1 column Xo 0001 activates K2 column Xo 1110 activates K15 column Xo 1111 activates K16 column X7X5X4 001 in this setting all of the matrix columns K16 will be checked simultaneously in each scanning cycle Xs Xo are not a factor X7X5Xq4 010 in this setting the key matrix scanning function will be disabled Xo are not a factor X7X5X4 10X in this setting each scanning cycle checks 8 specified columns on the key matrix The specified column is defined by the setting of Xs 0 activates K1 K8 columns simultaneously Xs 1 activates K9 K16 columns simultaneously X Xo don t care X7 X5X4 110 in this setting each scanning cycle checks four specified columns on key matrix The specified columns are defined by the setting of X3 and X X3X2 00 activates K1 K4 columns simultaneously X3X2 01 activates K5 K8 columns simultaneously X3X2 10 activates 9 K12 columns simultaneously 11 activates K13 K16 columns simultaneously X1 Xo
96. ed to VPP for Program Mode In TEST VPP I P INormal mode it must be connected to VDD2 Test signal input pin TM87P02 TM87P04 Switching pins for supply the LCD driving voltage to the VDD1 2 3 pins CUP1 2 Connect the 1 and CUP2 pins with non polarized electrolytic capacitor if 1 2 or 1 3 bias mode has been selected In no BIAS mode these pins should be open XIN is unused it must be connected to VDD2 XOUT 32KHz Crystal oscillator for Slow Clock 3 58MHz ceramic resonator CFIN oscillator for Fast Clock If CFIN CFOUT pin is unused it must be N A N A connected to VDD2 FRIN External R oscillation for Fast FROUT Clock If FRIN pin is unused it must be connected to GND FTIN FTOUT pan fo 3 58MHz ceramic resonator and External R oscillation for Fast Clock NA E _ connected to GND COM1 8 Output pins for driving the COM1 4 Output pins for driving the common pins of common pins of the LCD or LED panel the LCD panel 0 5 8 is muxed with DC Open Drain and set option pco SEG1 20 b 27 30 SEG1 29 30 10 AT Output pins SEG1 29 31 40 41 Output pins SEGn Output pins for driving driving the LCD panel segment driving the LCD or LED panel the LCD panel segment segment lota Output port A can use software to define internal pull low resistor This port is muxed with SEG24 27 and set by option 1 1 4 I O I
97. edivider 58 3 4 Buzzer Output PINS 61 PONS joi dot bog bon to fot iod doa ond dodo Baan a bot band Sant bs 63 S O ExternaliINTr Pip oo eoe mulu ert se cod anat aun tete Ha ead Ma eat es 73 3 7 Resistor to Frequency Converter RFC 87 8 74 3 7 Key Matrix Scanning 87 08 Only 78 CHAPTER 4 LCD Driver Output 82 4 1 LCD Lighting System in TM87P0X 82 4 2 DC OU nce Ande inte toas 83 4 3 Segment PLA Circuit for LCD Display 84 CHAPTER 5 Detail Explanation of TM87POX Instructions 91 5 1 Input Output Instructions Em 91 5 2 Accumulator Manipulation Instructions and Memory Manipulation Instructions 98 5 9 Operation InstruellOPs toot elei ay tok a a tl ot dn oe so 100 5 4 Load Store 2 2 112 5 5 CPU Control 11 11 11011 114 5 6 Index Address Instructions 117 5 7 Decimal Arithmetic Instructions 118 5 3 JUMP Tas UGBODIS e eb akaqa akaqa aad ette 119 5 9 Miscellaneous
98. enx technology inc Rev 1 0 2006 04 11 Preliminary DEC Rx Function Description DEC HL Function Description DEC HL Function Description ADC Rx Function Description ADC HL Function Description ADC HL Function Description TM87P0X User s Manual TM87R02 TM87P02 TM87P04 TM87P08 Rx AC 1 Substrate 1 from the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected TM87P08 R HL AC lt R HL 1 Substrate 1 from the content of data memory specified by HL the result is loaded to data memory specified by HL and AC Carry flag CF will be affected TM87P08 lt R HL 1 HL HL 1 Substrates 1 from the content of HL the result is loaded to the data memory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected HL indicates an index address of data memory TM87R02 TM87P02 TM87P04 TM87P08 AC lt Rx AC CF The contents of Rx AC and CF are binary added the result is loaded to AC Carry flag CF will be affected TM87P08 lt R HL AC CF The contents of data memory specified by and CF binary added the result is loaded to AC Carry flag CF will be affected TM87P08 lt HL AC CF HL
99. ffected D 0H FH TM87R02 TM87P02 TM87P04 TM87P08 AC lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The result will not affect the carry flag CF D 0H FH 87 2 87 2 87 4 87 8 AC Ry lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The result will not affect the carry flag CF D 0H FH 112 tenx technology inc Rev 1 0 2006 04 11 Preliminary ANDI Ry D Function Description ANDI Ry D Function Description EORI Ry D Function Description EORI Ry D Function Description ORI Function Description Ry D Function Description TM87POX User s Manual 87 2 87 2 87 4 87 8 AC lt Ry amp D D represents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC D 0H FH 87 2 87 2 87 4 87 8 AC Ry lt Ry amp D Drepresents the immediate data Binary ANDs the contents of Ry and D the result is loaded to AC and the working register Ry D 0H FH 87 2 87 2 87 4 87 8 AC lt Ry EOR D Drepresents the immediate data Exlusive Ors the contents of Ry and D the result is loaded to AC
100. g CF will be affected TM87P08 AC HL lt HL AC B CF HL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected TM87R02 TM87P02 TM87P04 TM87P08 AC lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC The carry flag CF will be affected TM87P08 AC lt HL AC Binary adds the contents of HL and AC the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected TM87P08 AC lt HL AC HL 1 Binary adds the contents of HL and AC the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected 105 tenx technology inc Rev 1 0 2006 04 11 Preliminary ADD Rx Function Description ADD HL Function Description ADD HL Function Description SUB Rx Function Description SUB HL Function Description SUB HL Function Description TM87P0X User s Manual TM87R02 TM87P02 TM87P04 TM87P08 AC R
101. g divider and letter D into the duty cycle generator The frequency generator will then output the clock using the following formula FREQ clock source N 1 X Hz X 1 2 3 4 for 1 1 1 2 1 3 1 4 duty This letter N is a combination of data memory and accumulator AC or the table ROM data or operand data specified in the FRQX instruction The following table shows the bit pattern of the combination 60 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual The following table shows the bit pattern of the preset letter N 2122 ThebitpatternofpresetletterN Programming divider Notes 1 TO T7 represents the data of table ROM 2 represents the data specified in operand X The following table shows the bit pattern of the preset letter D Preset Letter D Duty Dr cor cee ee 0 1 4 duty 0 1 1 3 duty 110 1 2 duty The following diagram shows the output waveform for different duty cycles clock source N 1 Hz TJ LI LI LI LI LI LI LI I 1 4 duty carrier out 1 3 duty carrier out 1 2 duty carrier out 1 1 duty carrier out 61 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual 3 3 2 Melody Output The frequency generator may generate the frequency for melody usage When the frequency generator is used to generate the melody output the tone table is shown be
102. h Refer to Chapter 5 for detailed description of these instructions PSTBO PSTB3Fh DBUSA DBUSH driver Figure 4 3 Sample Organization of Segment PLA Option 90 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 4 3 4 THE CONFIGURATION FORMAT FOR FIXED PLA MAPPING The TM87POX is fixed PLA structure PLA table is shown below TM87R02 TM87P02 PLA table TM87P04 PLA table COML COMB come DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG pay DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG LDBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSF DBUSG DBUSH DBUSE DBUSF DBUSG osy L DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG pegy DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG gp DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG ogy DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG DBUSA DBUSD DBUSA DBUSB DBUSC DBUSE DBUSH DBUSE DBUSF DBUSG DBUSA DBUSB DBUSC O DBUSE 08056 08054 08058 DBUSC DBUSE DBUSF DBUSG B N B N c mm c c mm x mm c x c c c c co 4 a mm x x x
103. he system clock to high speed clock SLOW TM87R02 TM87P02 TM87P04 TM87P08 Function Switches the system clock to XTOSC clock low speed osc Description Switches the system clock to low speed clock and then stops the CFOSC 117 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual MSB Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Rx lt SCF3 SCF1 SCF2 BCF Description The SCF1 SCF2 and BCF flag contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 SCF 3 SCF2 SCF1 BCF Halt release Halt release caused Halt release The Backup caused by the by 5 4 5 6 7 8 9 caused by the mode status in port IOC port 87 TM87P08 Only MSC Rx TM87R02 TM87P02 TM87P04 TM87P08 Function AC Rx lt SCF4 7 Description The 5 4 to SCF7 contents are loaded to AC and the data memory specified by Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 Bit 2 Bit 1 Bit 0 SCF7 stage of the predivider SCF5 SCF4 predivider overflow TM1 underflow caused by INT pin MCX Rx TM87R02 TM87P02 TM87P04 TM87P08 Function AC Rx lt SCF8 SCF6 SCF9 Description The SCF8 SCF6 SCF9 contents are loaded to AC and the data memory specified by Rx The content
104. hows the operating timing of TMR2 re load function for RFC 40 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 2 14 STATUS REGISTER STS The status register STS is organized with 4 bits and comes in 4 types status register 1 STS1 to status register 4 STS4 The following figure shows the configuration of the start condition flags for TM87P08 Chattering prevention output of IOC SEF4 SCA 10h Chattering prevention output of IOD SEF3 SCA 8h Timer 1 underflow PRETI N SCF5 HEF1 SHE 2h E IEF2 SIE 4h changed 2 m onINT pin SCF4 HEF2 SHE 4h IEF3 _ SIE 8h Predivide Loe 222277 overflow 5 7 5 8 IEFA SIE 10h Timer 2 HRF4 EI DES 2228 underflow SCF6 HEF4 SHE 10h IEF5 SIE 20h Key ny HRES Scanning SCF7 overflow HEF5 m SHE 20h IEF6 SIE 40h FRC counter HRF6 overflow J SCF9 HEF 6 SHE 40h PLC SCF1 PLC1h SCF3 IEF1 SIE 2h IEF0 SIE Initial reset Interrupt e SCF2 Interrupt O Halt release request Interrupt 1 Interrupt 2 Interrupt 3 Interrupt 4 Interrupt 5 Interrupt 6 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 2 14 1 STATUS REGISTER 1 5151 Status register 1
105. ider 15 bits are reset When executing this instruction X3 must be set to 1 simultaneously 129 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Chapter 6 Programming Waveform 12V TM87P04 Programming Waveform VPP jd 5V VDD2 K 8PULSES 9 PULSES 8 PULSES 2 4 8 PULSES OP CUN Min EUM flf t tu NER 2 mnn mE P Ves R INT bit6 TON bit7 X bit6 Do bit7 ote bito PASS bit7 X bit6 bit1 X 580 M 1 Pass 0 fal Inernal i Address 0000H 0001H Value INT T n sucessfu N etatis Password in Password return out 0000H Data in single 3 0001H Data in out 87 8 Programming Waveform y 5V VDD2 K 16PULSES 17 PULSES 16 PULSES 2 54 16 PULSES 3 PEU Min RE reser 111 DM t 1 1 i 1 INT w X D OX DON M bit X bito DON M bitl wo X AX 0115 w bitl X bito M 11 Pass 0 fail Inernal Address 0000H aY 0001H Value y PGM y INT sucessful 3 Status lt 569 Password in R Password
106. immediate data D from the working register Ry the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH 87 2 87 2 87 4 87 8 AC Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC The carry flag CF will be affected D 0H FH 111 tenx technology inc Rev 1 0 2006 04 11 Preliminary ADDI D Function Description SUBI Ry D Function Description SUBI Ry D Function Description ADNI Ry D Function Description Ry D Function Description 87 User s Manual TM87R02 TM87P02 TM87P04 TM87P08 AC Ry lt Ry D D represents the immediate data Binary ADDs the contents of Ry and D the result is loaded to AC and the working register Ry The carry flag CF will be affected D 0H FH TM87R02 TM87P02 TM87P04 TM87P08 AC Ry D 1 D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC The carry flag CF will be affected D 0H FH TM87R02 TM87P02 TM87P04 TM87P08 AC Ry lt Ry Y 1 D represents the immediate data Binary subtracts the immediate data D from the working register Ry the result is loaded to AC and the working register Ry The carry flag CF will be a
107. is set by SHE instruction The bit pattern of the control register CTL2 is shown below release HF Sable HE 5 4 Enable the halt release Enable the halt release Enable the halt release condition caused by counter caused by Key caused by TMR2 to be finished HRF6 Scanning HRF5 underflow HRF4 HF HEF2 HEF1 Enable the halt release Enable the halt release Enable the halt release caused by pre divider caused by INT pin caused by TM1 overflow HRF3 HRF2 underflow HRF1 release enable a MES Halt release condition TM87P08 Only When the halt release enable flag 6 HEF6 is set a finish signal from the 16 bit counter of RFC causes the halt mode to be released In the same manner when HEF1 to HEF4 are 47 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual set to 1 the following conditions will cause the halt mode to be released respectively an underflow signal from TMR1 the signal change at the INT pin an overflow signal from the pre divider and an underflow signal from TMR2 When the stop release enable flag 5 SRF5 and the HEF2 are set the signal change at the INT pin can cause the stop mode to be released 2 15 3 CONTROL REGISTER 3 CTL3 Control register 3 CTL3 is organized with 6 bits of interrupt enable flags IEF to enable disable interrupts The interrupt enable flag IEF is set reset b
108. k and the system clock selection flag CSF is reset to 0 Executing FAST instruction will change the clock source BCLK of the system clock generator to the fast speed oscillator CF clock and the system clock selection flag CSF is set to 1 For the operation of the system clock generator refer to 3 3 2 Watchdog timer enable flag WTEF The watchdog timer enable flag WDF indicates the operating status of the watchdog timer 3 Overflow flag of 16 bit counter of RFC RFOVF The overflow flag of 16 bit counter of RFC RFOVF is set to 1 when the overflow of the 16 bit counter of occurs The flag will reset to 0 when this counter is initiated by executing SRF instruction The MSD instruction can be used to transfer the contents of status register 4 STS4 to the accumulator AC and the data memory RAM 44 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual The following table shows the Bit Pattern of Status Register 4 STS4 Bit 3 Bit 2 Bit 1 Bit 0 NA The overflow flag of 16 bit Watchdog timer System clock counter of RFC RFVOF Enable flag WDF selection flag CSF Read only Read only Read only Read only TM87P08 Only 2 14 6 START CONDITION FLAG 11 SCF11 Start condition flag 11 SCF 11 will be set to 1 in STOP mode when the following conditions are met A high level signal comes from the OR ed output of the pins defined as input mode in IOC port which causes the stop release
109. k source setting Bit pattern Clock source setting X6 1 The clock source comes from X6 0 The clock source comes from the the system clock BCLK 00 Refer to section 3 3 4 for 00 Bit pattern Clock source setting Bit pattern Clock source setting X2 X1 X0 001 clock of IOD port PHO X2 X1 X0 001 of IOC port PHO X2 X1 X0 010 clock of IOD port PH8 X2 X1 X0 010 of IOC port PH8 2 1 0 100 of IOD port PH6 _ X2 X1 X0 100jof IOC port PH6 FRQ D Rx TM87R02 TM87P02 TM87P04 TM87P08 Function Frequency generator lt D Rx Description Loads the content of AC and data memory specified by Rx and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting bit pattern of preset letter Programming divider FRQ Rx Preset Letter D Duty Cycle o J may x O ty pot 124 D1 124 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual FRQ D HL TM87P08 Function Frequency generator lt D T HL Description Loads the content of Table ROM specified by HL and D to frequency generator to set the duty cycle and initial value The following table shows the preset data and the duty cycle setting fon es te Hl The bit pattern of preset letter N Programming divider Note TO T7 represents the data of table ROM Preset Letter
110. l 1 7 CHARACTERIZATION TM87P02 TM87P04 TM87P08 Only ABSOLOUTE MAXIMUM RATINGS GND 0V Name Symbol Range Unit VDD1 2 3 0 3 0 5 5 Maximum Supply Voltage VPP 0310135 Maximum Input Voltage Vin 0 3 to VDD1 2 0 3 V Maximum output Voltaqe Vout1 0 3 to VDD1 2 0 3 9 Vout2 0 3 to VDD3 0 3 Maximum Operating Temperature Topg 20 to 70 Maximum Storage Temperature Tstg 25 to 125 ALLOWABLE OPERATING CONDITIONS at Ta 20 C to 70 C GND 0V Name Symb Condition Part No Min Max Unit VDD2 TM87P02 2 4 3 6 VDD3 TM87P04 2 4 5 4 0 2 4 12 5 VDD2 24 5 25 VDD3 TM87P08 2 4 8 0 VPP 2 4 12 5 Oscillator Start Up VDD 32 768KHz Crystal Mode 1 4 V Voltage TP 3 58 ceramic resonator Mode 1 8 Oscillator Sustain VDD 32 768KHz Crystal Mode 1 3 Voltage 3 58 ceramic resonator Mode 1 55 Input H Voltage Vih1 VDD2 0 7 VDD2 0 7 Li Battery Input L Voltage viti EIN US 217 0 7 Input H Voltage OSCIN at Li Battery Mode 0 8xVDD2 VDD2 Input L Voltage Vil2 0 0 2xVDD2 Operating Freq Fopg1 32 768KHz Crystal Mode 32 KHZ Fopg2 External R mode 10 1000 15 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual ELECTRICAL CHARACTERISTICS Input Resistance at 1 VDD2 3 0V Li at 2 VDD2 5 0V Ext V O
111. le data of Table ROM specified by QHL is loaded to the data memory specified by Rx TM87P08 Rx AC lt L T HL HL HL 1 The lower nibble data of Table ROM specified by QHL is loaded to the data memory specified by Rx and then incremented the content of HL TM87P08 Rx lt 3 0 Loads the lowest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 3 Bit 2 RFC 2 Bit 1 RFC 1 Bit 0 RFC O TM87P08 Rx AC lt RFC 7 4 Loads the 274 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 7 Bit 2 RFC 6 Bit 1 RFC 5 Bit 0 RFC 4 TM87P08 Rx AC lt RFC 11 8 Loads the 3 nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 11 Bit 2 RFC 10 Bit 1 RFC 9 Bit 0 RFC 8 115 tenx technology inc Rev 1 0 2006 04 11 Preliminary MRF4 Rx Function Description 87 User s Manual TM87P08 Rx AC lt RFC 15 12 Loads the highest nibble data of 16 bit counter of RFC to AC and data memory specified by Rx Bit 3 RFC 15 Bit 2 RFC 14 Bit 1 RFC 13 Bit 0 RFC 12 5 5 CPU CONTROL INSTRUCTIONS NOP Function Description HALT Function Description STOP Function Description SCA X Function Description TM87R02
112. lease caused by timer 1 Me se quede Halt released ALM 0 Stop the buzzer output 3 5 INPUT OUTPUT PORTS Three I O ports are available TM87POX IOA IOB and IOC Each I O port is composed of 4 bits or 2bit and has the same basic function When the I O pins are defined as function by option the input output function of the pins will be disabled 3 5 1 IOA PORT 1 IOA4 pins are MUX with CX SEG24 SEG25 SEG26 and SEG27 pins respectively by option 87 08 Only OPTION table Option name Selected item SEG24 IOA1 CX 2 IOA1 SEG25 IOA2 RR 2 2 SEG26 IOA3 RT 2 IOA3 SEG27 IOA4 RH 2 IOA4 In initial reset cycle the IOA port is set as input mode and each bit of port can be defined as input mode or output mode individually by executing SPA instructions Executing OPA instructions may output the content of specified data memory to the pins defined as output mode the pins defined as the input mode will still remain the input mode Executing IPA instructions may store the signals applied to the IO pins into the specified data memory When the IO pins are defined as the output mode executing IPA instruction will store the content that stored in the latch of the output pin into the specified data memory Before executing SPA instruction to define the I O pins as the output mode the OPA instruction must be executed to outpu
113. low 1 The clock source is PH0 i e 32 768KHz 2 The duty cycle is 1 2 Duty D 2 3 FREQ is the output frequency 4 ideal is the ideal tone frequency 5 is the frequency deviation The following table shows the note table for melody application Tone N FREQ Idel 96 Tone FREQ Ideal C2 249 65 5360 65 4064 0 19 C4 62 260 063 261 626 0 60 0 64 198 82 3317 82 4069 0 09 E4 49 327 680 329 628 0 59 0 18 0 0 0 64 0 48 1 16 0 64 0 42 0 53 528 516 523 251 1 01 546 133 554 365 1 48 0 37 1 27 0 59 1 99 0 64 0 48 1 37 2 01 2 37 963 765 Note 1 Above variation does not include X tal variation 2 If PH0 65536Hz C3 B5 may have more accurate frequency During the application of melody output sound effect output or carrier output of remote control the frequency generator needs to combine with the alarm function BZB BZ For detailed information about this application refer to section 3 4 62 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 3 3 3 Halved Doubler Tripler The halved doubler triple circuits are used to generate the bias voltage for LCD and are composed of a combination of PH2 PH3 PH4 PH5 3 3 4 Alternating Frequency for LCD The alternating frequency for LCD is a frequency used to make the LCD waveform 3 4 BUZZER OUTPUT PINS There are two output pins BZB and BZ
114. matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit pattern of the table ROM corresponding to SPKX is shown below Instruction Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SPK QHL T HL 7 Te HL 6 TO HL 5 T HL 4 TGHL 3 T HL 2 TOHL 1 TOHL O SPKX X XT X6 X5 X4 X3 X2 X1 XO ALM X TM87R02 TM87P02 TM87P04 TM87P08 Function Sets buzzer output frequency Description The waveform specified X X8 is delivered to the BZ and BZB pins The output frequency could be any combination in the following table The bit pattern of X for higher frequency clock source clock source higher frequenc FREQ DC1 3 4KHz 4 2 2 5 1 2 The bit pattern of X for lower frequency clock source clock source lower frequency 15 1Hz 014 2 2 99 technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual 013 4 2 912 8 2 011 16 2 610 32Hz Notes 1 FREQ is the output of frequency generator 2 When the buzzer output does not need the envelope waveform X5 X0 should be set to 0 3 The frequency inside the bases on the 0 is 32768Hz SRF X TM87P08 Function The operation control for RFC Description The meaning of each control bit X5 is shown below 4 Timer 2 the 16 bit counter 3 must celto Then thie bitis tetto T 4 X4
115. mer 2 Example In this example use the RT network to generate the clock source SRF 1Ah Build up the RT network and enable the counter controlled by TM2 SHE 10h enable the halt release caused by TM2 TM2X 20h set the PH9 as the clock source of TM2 and the down 78 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual count value is 20h HALT PLC 10h Clear the halt release request flag of TM2 MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 7 4 Enable Disable the Counter by CX Signal TM87P08 Only This is another use for the 16 bit counter In previous modes CX is the clock source of the counter and the program must specify a time period by timer or subroutine to control the counter In this mode however the counter has a different operation method CX pin becomes the controlled signal to enable disable the counter and the clock source of the counter comes from the output of the frequency generator FREQ The counter will start to count the clock FREQ after the first rising edge signal applied on the CX pin when the counter is enabled Once the second rising edge is applied to the CX pin after the counter is enabled the halt release request HRF6 will be delivered and the counter will stop counting In this case if the interrupt enable mode IEF6 is provided the interrupt is accepted and if the halt release enable mode HEF6 is provided the halt release reque
116. n Halt Normal mode Halt Halt mode OSC active released OSC active Stop Reset Reset release Stop Release Stop mode OSC stop Reset mode Power onreset OSC active Reset Reset pin reset Watchdog timer reset Key reset This figure shows the State Diagram of Single Clock Option 25 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 2 2 4 PREDIVIDER The pre divider is a 15 stage counter that receives the clock from the output of clock switch circuitry as input When is changed from H level to L level the content of this counter changes The PH11 to PH15 of the pre divider are reset to 0 when the PLC 100H instruction is executed or at the initial reset mode The pre divider delivers the signal to the halved triple circuit alternating frequency for LCD display system clock sound generator and release request signal 1 port chattering prevention clock 1 Interrupt request Frequency Generator Halt mode BCLK Initial SLOW instruction T1 T2 T3 T4 Sclk PLC 8H FAST instruction 7 1 Interrupt HALT release Clock System Fall edge HRF3 request flag switch clock detector XTOSC circuit generator MSC instruction SEE Data bus 2 OC CFOSC E Switch E To timer circuit 1 PLC 100H initial Single clock oton li i Dual clock option s D TIT aj a a a 7 PH9
117. n the following table and illustrated in example 1 AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt lt 9 lt lt 6 0 lt lt 3 1 6 Example 1 LDS 10h 9 Load immediate data 9 to data memory address 10H LDS 11h 1 Load immediate data 1 to data memory address 11H and AC RF 1h Reset CF to 0 ADD 10h Contents of the data memory address 10H and AC are Binary added the result loads to amp data memory address 10H Rio AC CF 0 DAA 10h Convert the content of AC to decimal format The result in the data memory address 10H is O and the CF is 1 This represents the decimal number 10 Instructions DAS DAS DAS HL can convert the data from hexadecimal format to decimal format after any subtraction operation The conversion rules are shown in the following table and illustrated in Example 2 data before DAS CF data before DAS AC data after DAS CF data after DAS execution execution execution execution 33 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 0 lt lt 9 6 lt AC lt F AC AC A Example 2 LDS10h 1 Load immediate data 1 to the data memory address 10H LDS11h 2 Load immediate data 2 to the data memory address 11H and SF 1 Set CF to 1 which means no borrowing has
118. nction is another solution to minimize the current dissipation for TM87POX In stop mode all of functions in 87 are held including oscillators All of the LCD corresponding signals COM and Segment will output L level In this mode 87 does not dissipate any power in the stop mode Because the stop mode will set the BCF flag to 1 automatically it is recommended to reset the BCF flag after releasing the stop mode in order to reduce power consumption Before the stop instruction is executed all of the signals on the pins defined as input mode of IOC port must be in the L state and no stop release signal SRFn should be delivered The CPU will then enter the stop mode The following conditions cause the stop mode to be released One of the signals on the input mode pin of IOC port is in H state and holds long enough to cause the CPU to be released from halt mode 50 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual A signal change in the INT pin The stop release condition specified by the SRE instruction is met INT pin is exclusive When the TM87P0X is released from the stop mode the TM87P0X enters the halt mode immediately and will process the halt release procedure If the H signal on the IOC port does not hold long enough to set the SCF1 once the signal on the IOC port returns to L the TM87P0X will enter the stop mode immediately The backup flag BCF will be set t
119. ne the contents of the program counter PC are automatically saved to the stack register STACK 2 4 PROGRAM TABLE MEMORY ROM The PROM is shown below 87 8 TM87P04 OTP TM87R02 Mask ROM 87 2 OTP 1605 16bi s l 1665 FFFh FFFh 7FFh Note The data width of table ROM is 8 bit 28 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual 2 4 1 INSTRUCTION ROM PROM There are some special locations that serve as the interrupt service routines such as reset address 000 interrupt 0 address 014 interrupt 1 address 018H interrupt 2 address 010H interrupt 3 address 01 interrupt 4 address 020H interrupt 5 address 024H and interrupt 6 address 028H in the program memory TM87P08 Only Address Address 000h Initial reset 000h 010h Interrupt 2 014h Interrupt 0 018h Interrupt 1 01Ch Interrupt 3 High Low Nibble Nibble 020h Interrupt 4 024h Interrupt 5 028h Interrupt 6 FFFh 8 Bits 16bits Instruction ROM PROM organization Table ROM TROM organization TM87P08 Only This figure shows the Organization of ROM 2 4 2 TABLE ROM TM87P08 Only This memory space stores the constant data or look up table for the usage of main program All of the table ROM addresses are spe
120. ne of the input signal could change state 2 15 1 2 The Setting for Stop Mode If SRF4 and SEF4 are set the stop mode will be released to set the SCF1 when a high level signal is applied to one of the input mode pins of IOC port and the other pins stay in 0 state After the stop mode is released TM87POX enters the halt condition The high level signal must hold for a while to cause the chattering prevention circuitry of IOC port to detect this signal and then set SCF 1 to release the halt mode or the chip will return to the stop mode again 2 15 1 3 Interrupt for CTL1 The control register 1 CTL 1 performs the following function in the execution of the SIE instruction to enable the interrupt function The input signal changes at the input pins in IOC port will deliver the SCF1 when SEF4 has been set to 1 by executing SCA instruction Once the SCF1 is delivered the halt release request flag HRFO will be set to 1 In this case if the interrupt enable flag 0 IEFO is set to 1 by executing SIE instruction the interrupt request flag 0 interrupt 0 will be delivered to interrupt the program If the interrupt 0 is accepted by SEF4 and IEFO the interrupt 0 request to the next signal change at IOC will be inhibited To release this mode SCA instruction must be executed again Refer to 2 16 1 1 2 15 2 CONTROL REGISTER 2 CTL2 Control register 2 CTL2 consists of halt release enable flags 1 2 3 4 5 6 1 2 3 4 5 6 and
121. nge at the INT pin causes the halt release request flag 2 HRF2 to be outputted and the halt release enable flag 2 HEF2 is set beforehand To reset start condition flag 4 SCF4 the PLC instruction must be used to reset the halt release request flag 2 HRF2 or the SHE instruction must be used to reset the halt release enables flag 2 HEF2 2 Start condition flag 5 SCF5 Start condition flag 5 SCF5 is set when an underflow signal from Timer 1 TMR1 causes the halt release request flag 1 HRF1 to be outputted and the halt release enable flag 1 HEF1 is set beforehand To reset start condition flag 5 SCF5 the PLC instruction must be used to reset the halt release request flag 1 HRF1 or the SHE instruction must be used to reset the halt release enables flag 1 HEF1 3 Start condition flag 7 SCF7 Start condition flag 7 SCF7 is set when an overflow signal from the pre divider causes the halt release request flag 3 HRF3 to be outputted and the halt release enable flag 3 HEF3 is set beforehand To reset start condition flag 7 SCF7 the PLC instruction must be used to reset the halt release request flag 3 HRF3 or the SHE instruction must be used to reset the halt release enables flag 3 HEF3 4 The 15th stage s content of the pre divider The 5 instruction is used to transfer the contents of status register 3 STS3 to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Regi
122. ning Interrupt 5 RFC counter Interrupt 6 overflow Interrupt accept signal SIE instruction Initial clear 3 1 1 INTERRUPT REQUEST AND SERVICE ADDRESS 3 1 1 1 External interrupt factor The external interrupt factor involves the use of the INT pin IOC ports or ports 1 External INT pin interrupt request By using option either a rise or fall of the signal at the INT pin can be selected for applying an interrupt If the interrupt enable flag 2 IEF2 is set and the signal on the INT pin change that matches the option will issue the HRF2 interrupt 2 is accepted and the instruction at address 10H is executed automatically It is necessary to apply level L before the signal rises and level H after the signal rises to the INT pin for at least 1 machine cycle 2 port IOC IOD interrupt request An interrupt request signal HRFO is delivered when the input signal changes at I O port IOD specified by the SCA instruction In this case if the interrupt enabled by flag 0 IEFO is set to 1 interrupt 0 is accepted and the instruction at address 14H is executed automatically 53 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual 3 Key matrix Scanning interrupt request An interrupt request signal HRF5 is delivered when the input signal is generated in the scanning interval If the interrupt enable flag 5 IEF5 is set to
123. nly TM87P08 Name Symb Condition Min Typ Max Unit Vi 0 2VDD2 1 10 40 100 KO RIIh2 Vi 0 2VDD2 2 5 20 50 KO Rmad1 Vi VDD2 1 200 500 1000 Pull Down Sm npa UT ago Vi VDD2 2 100 250 500 Rintu1 Vi VDD2 1 200 500 1000 INT Pull up Tr Rintu2 Vi VDD2 2 100 250 50 Rintd1 Vi GND 1 200 500 1000 INT Pull Down T Rintd2 Vi GND 2 100 250 500 KQ Rres1 Vi GND or VDD2 1 9 35 90 KO RES Pull Down R Rres2 Vi GND VDD2 2 5 18 45 KQ 16 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual POWER CONSUMPTION at VDD2 3 0 Ta 20 C to 70 C GND OV Name Sym Condition Min Typ Unit Only 32 768KHz Crystal oscillator operating HALT IHALT without loading 0 1 4 duty phO BCLK ibi STOP mode ISTOP 1 Only 32 768KHz Crystal oscillator operating N IM Mode vithout loading 0 1 4 duty phO BCLK uA R 150K oscillator operating without loading Ext IR lex ER BCF 0 1 4 duty phO BCLK e 3 58 2 ceramic Only 3 58MHz ceramic resonator operating 480 resonator 359V without loading 0 1 4 duty phO BCLK Note When External R oscillator function is operating the current consumption will depend on the frequency of oscillation
124. nput Output port B can use software to define internal pull low resistor 13 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Only 4 This This port is muxed with SEG28 29 This port is muxed with SEG28 31 port is muxed with DC30 SEG31 BZB BZ and set BZB BZ and set by option SEG29 BZB BZ by option and set by option Input Output port C can use software to define internal pull low low level hold resistor IOC1 4 and chattering clock to reduce input bounce This port is muxed with 11 4 and set by option Input Output port D can use software to define internal pull low resistor IOD1 4 Only 10D1 2 2002 22 01 2 clock to reduce input bounce 87802 1 87 02 TM87P04 TM87P08 227 N A RFC application RR RT RH This port is muxed with 5 24 27 1 4 and set by option ALM Output port for alarm frequency or melody generator This port is muxed with SEG30 SEG31 IOB3 4 and This port is muxed with DC30 SEG31 BZB BZ set by option 1083 4 and set by option Keyboard scanning input port 1 4 This port is muxed with SEG32 35 0 1 4 and set by option GND Negative supply voltage Connect for Serial Program Read Mode Serial Program Read TM87R02 87 2 87 4 TM87P08 Connect Pins VPP VDD2 GND RESET INT 14 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manua
125. nput latch state JBO ki seg1 SPK 4fh Enables only the SEG16 scanning output PLC 20h Clear HRF5 to avoid the false HALT released CALL wait scan again Waits for the time over the halt LCD clock cycle to ensure and scans again IPC 10h Reads the KI1 input latch state JBO kil seg16 wait scan again HALT PLC 20h RTS 83 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual CHAPTER 4 LCD DRIVER OUTPUT There are maximum 32 segment pins with 8 common pins in the LCD driver outputs in 87 OPTION table During the initial reset cycle the LCD lighting system may be lit or extinguished by option All of the LCD or DC output will remain in the initial setting until instructions relative to the LCD are executed to change the output data OPTION table Option name Selected item LCD DISPLAY IN RESET CYCLE 1 ON LCD DISPLAY IN RESET CYCLE 2 OFF 4 1 LCD LIGHTING SYSTEM IN TM87P0X There are several LCD lighting systems that can be selected by option in TM87P0X they are e 1 2 bias 1 4 duty 1 2 bias 1 8 duty 1 3 bias 1 4 duty 1 3 bias 1 8 duty TM87P08 Only All of these lighting systems are combined with 2 kinds of options one is LCD DUTY CYCLE and the other is BIAS OPTION table LCD duty cycle option TM87P08 Only Option Name Selected Item LCD DUTY CYCLE 4 1 4 DUTY LCD DUTY CYCLE 8 1 8 DUTY LCD bias op
126. nts of AC and CF are binary subtracted from content of Rx the result is loaded to AC Carry flag CF will be affected TM87P08 AC lt R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC Carry flag CF will be affected TM87P08 lt HL AC B CF QHL HL 1 Binary subtracts the contents of AC and CF from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected 104 tenx technology inc Rev 1 0 2006 04 11 Preliminary SBC Rx Function Description SBC HL Function Description SBC HL Function Description ADD Rx Function Description ADD HL Function Description ADD HL Function Description TM87P0X User s Manual TM87R02 TM87P02 TM87P04 TM87P08 Rx The contents of AC and CF are binary subtracted from content of Rx the result is loaded to AC and data memory Rx Carry flag CF will be affected TM87P08 AC R HL lt R HL AC B CF The contents of AC and CF are binary subtracted from content of data memory specified by HL the result is loaded to AC and data memory specified by HL Carry fla
127. o 1 automatically after the program enters the stop mode The following diagram shows the stop release procedure STOP HALT MODE STOP Yes released release Figure 3 16 The stop release state machine Before the stop instruction is executed the following operations must be completed Specify the stop release conditions by the SRE instruction Specify the halt release conditions corresponding to the stop release conditions if needed Specify the interrupt conditions corresponding to the stop release conditions if needed When the stop mode is released by an interrupt request the TM87POX will enter the halt mode immediately While the interrupt is accepted the halt mode will be released by the interrupt request The stop mode returns by executing the RTS instruction after completion of interrupt service After the stop release it is necessary that the MSB MSC or MCX instruction be executed to test the halt release signal and that the PLC instruction then be executed to reset the halt release signal Even when the stop instruction is executed in the state where the stop release signal SRF is delivered the CPU does not enter the stop mode but the halt mode When the stop mode is released and an interrupt is accepted the halt release signal HRF is reset automatically HALT released decision 51 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Chapter 3 Control Function 3 1 INTERRUPT
128. occurred SUB 10h Content of data memory address 10H is binary subtracted the result loads to data memory address 10H Rio AC Fu CF 0 DAS 10h Convert the content of the data memory address 10H to decimal format The result in the data memory address 10H is 9 and in the CF is 0 This represents the decimal number 1 2 12 TIMER 1 TMR1 Re load RL1 Si lt TMS instruction IEF1 Q R Initial reset 0 TMR1 2 Interrupt FREQ 6 bit binary down __ Ho counter HRF1 PH9 SCF5 Halt release Reset PH15 Operand data 5 0 TMS instruction Interrupt accept signal PLC 2 instruction x8 x7 x6 TMS instruction Initial reset Operand data This figure shows the TMR1 organization 2 12 1 NORMAL OPERATION TMR1 consists of a programmable 6 bit binary down counter which is loaded and enabled by executing TMS or instruction Once the TMR1 counts down to 3Fh it generates an underflow signal to set the halt release request flag1 HRF 1 to 1 and then stop to count down When 1 1 and the TMR1 interrupt enable flag IEF1 1 the interrupt is generated When 1 1 if the IEF1 0 and the TMR1 halt release enable HEF 1 1 program will escapes from halt mode if CPU is in halt mode and then set the start condition flag 5 SCF5 to 1 in the status register 3 ST
129. of AC and meaning of bit after execution of this instruction are as follows Bit 2 Bit 1 Start condition flag 9 Start condition flag 6 Start condition flag 8 SCF9 SCF6 SCF8 Halt release Halt release Haltrelease caused caused by RFC caused by TM2 by the signal change counter overflow underflow to L applied on KI1 4 in scanning interval TM87P08 Only 118 tenx technology inc Rev 1 0 2006 04 11 Preliminary MSD Rx Function Description TM87P0X User s Manual TM87R02 TM87P02 TM87P04 TM87P08 Rx lt WDF CSF RFOVF The watchdog flag system clock status overflow flag of RFC counter and low battery detected flag are loaded to data memory specified by Rx and AC The content of AC and meaning of bit after execution of this instruction are as follows Bit 2 Bit 1 Bit 0 The overflow flag Watchdog timer System clock NA of 16 bit counter enable flag selection flag of RFC RFVOF WDF CSF 5 6 INDEX ADDRESS INSTRUCTIONS MVU Rx Function Description MVH Rx Function Description MVL Rx Function Description CPHL X Function Description TM87P08 U lt Rx Loads content of Rx to the index address buffer U U3 Rx 3 U2 Rx 2 U1 Rx 1 U0 Rx 0 TM87P08 lt Rx Loads content of Rx to higher nibble of index address buffer oH H3 Rx 3 H2 Rx 2 H1 Rx 1 HO2 RX O TM87P08 L
130. ollowing figure shows the key reset organization IOC1 Le D IOC2 p I reset IOC r IOC3 IOC4 Le D 3 2 4 WATCHDOG RESET The timer is used to detect unexpected execution sequence caused by software run away The watchdog timer consists of a 9 bit binary counter The timer input PH10 is the 10th stage output of the pre divider When the watchdog timer overflows it generates a reset signal to reset TM87P0X and most of the functions in TM87P0X will be initiated except for the watchdog timer which is still active WDF flag will not be affected and PHO PH10 of the pre divider will not be reset The following figure shows the watchdog timer organization mask option 9 bit counter PH10 HALT Edge detector WDF WDRST to reset TM8706 Reset pin POR RF 10H 59 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual During initial reset power on reset or reset pin the timer is inactive and the watchdog flag WDF is reset Instruction SF 10h will enable the watchdog timer and set the watchdog flag WDF to 1 At the same time the content of the timer will be cleared Once the watchdog timer is enabled the timer will be paused when the program enters the halt mode or stop mode When the TM87POX wakes up from the halt or stop mode the timer operates c
131. on IOD TM87P08 Only When the stop release enable flag 5 SRF5 is set to 1 the input signal change at the INT pins causes the stop mode to be released In the same manner when SRF4 SRF3 is set to 1 the input signal change at the input mode pins of IOC port and the signal changed on INT pin causes the stop mode to be released respectively 48 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Example This example illustrates the stop mode released by port IOC and INT pin Assume all of the pins in IOD and IOC have been defined as input mode PLC 05h Reset the HRF0 and HRF2 SHE 04h HEF2 and 5 is set so that the signal change at INT pin causes start condition flag 4 or 8 to be set SCA 18h SEF4 is set so that the signal changes at port IOC and IOD cause the start conditions SCF1 to be set SRE 038h SRF5 4 are set so that the signal changes at port IOC IOD and INT pin cause the stop mode to be released STOP Enter the stop mode STOP release 5 10h Check the signal change at INT pin that causes the stop mode to be released MSB 11h Check the signal change at port IOC IOD that causes the stop mode to be released 2 16 HALT FUNCTION The halt function is provided to minimize the current dissipation of the TM87POX when LCD is operating During the halt mode the program memory ROM is not in operation and only the oscillator circuit pre divider
132. ontinuously It is recommended to execute SF 10h instruction before the program enters the halt or stop mode in order to initialize the watchdog timer Once the watchdog timer is enabled the program must execute SF 10h instruction periodically to prevent the timer overflowed The overflow time interval of watchdog timer is selected by option OPTION table Option name Selected item WATCHDOG TIMER OVERFLOW TIME INTERVAL 1 8 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 2 64 x PH10 WATCHDOG TIMER OVERFLOW TIME INTERVAL 3 512 x PH10 Note timer overflow time interval is about 16 seconds when 32 768KHz 3 3 CLOCK GENERATOR 3 3 1 FREQUENCY GENERATOR The Frequency Generator is a versatile programmable divider that is capable of delivering a clock with wide frequency range and different duty cycles The output of the frequency generator may be the clock source for the alarm function timer1 timer2 and RFC counter The following shows the organization of the frequency generator BCLK 8 bit Programmable Duty Cycle Frequency output AC1 AC0 Rx3 RxO SC FRQ D Rx SCC instruction may specify the clock source selection for the frequency generator The frequency generator outputs the clock with different frequencies and duty cycles corresponding to the presetting data of FRQ related instructions The FRQ related instructions preset a letter N into the programmin
133. ot affect the display of the LCD panel The input port of the key matrix circuitry is composed of KI1 pins these pins are muxed with SEG32 SEG35 pins and selected by option OPTION table Option name Selected item SEG32 IOC1 KI1 3 KI1 5 2 2 3 2 3 5 4 4 3 4 The typical application circuit of the key matrix scanning is shown below Executing SPKX X SPK Rx SPK HL instructions could set the scanning type of K16 K15 K14 K13 K12 K11 10 K9 K8 K7 K6 K5 K4 K2 K i Gg dap WERE 15212 1 2 4 14 18 O Q Q 0 O 0 0 0 0 0 0 O 0 0 0 0 4 0 0 0 0 O L o 0 4 42 0 0 0 L o 0 4 0 0 0 4 42 0 0 0 the key matrix The bit pattern of these 3 instructions shown below Instruction Bit Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 BitO SPKX X XT X6 X5 X4 X3 X2 X1 XO SPK Rx AC3 AC2 AC1 ACO Rx3 Rx2 Rx1 Rx0 SPK HL T HL7 T HL6 T HL5 T HL4 T HL3 T HL2 T HL1 T HLO The following description shows the bit definitions in the operand of the SPKX instruction 80 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual Xs 0 when HEF5 is set to 1 the HALT release request HRF5 will be set to 1 after the key depress
134. return out 0000H Data in single 0001H Data out This programming application circuit is simply an example TM87P04 87 08 CUP1 CUP2 RESET 130 lt PROGRAMMING CLOCK r1 M PROGRAMMING DATA I O tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual Appendix A TM87P0X Instruction Table JRE Instruction Machine Code Function Flag Remark NOP 0000 0000 0000 0000 No Operation V LCT Lz Ry 0000 0012 ZZZZ LZ lt 15 Ry 70 7 V LCB 25 0000 0107 ZZZZ LZ lt 75 Ry 70 7 Blank Zero LCP 2 00000117 7777 Yyyy Lz lt Ry amp AC Ry 70H 7F H V LCD 1 2 0000 1007 7777 0000 12 lt T HL V X LCT Lz HL o000 1007 zzzz 0001 12 75 0 lt V X LCB Lz HL 0000 1007 zzzz 0010 12 lt 75 lt V X Blank Zero LCP Lz HL 0000 1007 7777 0011 12 lt 9HL amp AC v x LCDX D 0000 100D D000 0100 Multi Lz lt T HL D 0 1 v X D 00 Multi Lz 00H 0F H D 01 Multi Lz 10H 1F H LCTX 0000 100D D000 0101 Multi Lz lt 7SEG lt HL D 0 1 V x LCBX 0000 100D D000 0110 Multi Lz lt 7SEG lt HL 0 0 1 v X Blank Zero LCPX 0000 1000 D000 0111 Multi Lz
135. rogrammable timer with imer programmable clock source Tone Alarm Frequency or Melody generator Buzzer BZB BZ Multiple with IOB3 IOB4 Stack 8 Level HALT STOP Yes Watch Dog Yes Open Drain 0 5 8 0 9 DC30 LCD Duty 1 4 1 8 1 4 Bias 1 2 1 3 LED Yes VO With Pull Low 16 14 12 IOA B C D 409 45 4 4 409 209 4 4 409 5200 4 2 Slow32 KHz XTd Yes 31 358 Yes 9 s External R Yes Intemal RC Yes LowLevel Holder External 4 INT IOC D KI 2 INT IOC 4 Pre Divider Internal Timer1 Timer2 3 Pre Divider Timer1 Timer2 RFC Instruction Set 177 102 4 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual C7 ROM code protection function 2 Individual Table ROM 4 Multiple With Segment With Pull Low 5 Shared With Seg1 16 and IOC 9 Be Combined to 2 pads FTIN FTOUT 5 tenx technology inc Rev 1 0 2006 04 11 Preliminary 1 3 BLOC K DIAGRAM 87 User s Manual SEGn
136. so controlled the operation of RFC function TMR2 will set TENX flag to 1 to enable the RFC counter once the TMR2 underflows the TENX flag will be reset to 0 automatically In this case Timer 2 could set an accurate time period without setting a value error like the other operations of TMR1 and TMR2 Refer to 2 16 for detailed information on controlling the RFC counter The following figure shows the operating timing of TMR 2 in RFC mode Clock source of Timer 2 J4 TM2X X Content of 3Fh N 1 N 2 1 3Fh Timer2 7 HRF4 PO TENX TMR2 also provides the re load function when controlled the RFC function The SF2 1 instruction enables the re load function and the DED flag should be set to 1 by SF2 2h instruction Once DED flag had been set to 1 TENX flag will not be cleared to 0 while TMR2 underflows but HRF4 will be set to1 The DED flag must be cleared to 0 by executing RF2 2h instruction before the last HRF4 occurs thus the TENX flag will be reset to 0 when the last HRF4 flag delivery After the last underflow HRF4 of TMR2 occurred disable the re load function by executing RF2 1h instruction For example if the target set value is 500 it will be divided as 52 7 64 1 Set the initiate value of TMR2 to 52 and start counting 2 Enable the TMR2 halt release or interrupt function 3 Before the first underflow occurs enable the re load function and set the DED flag The TMR2 will continue counting even
137. st signal is delivered setting the start condition flag 9 SCF9 in status register 4 STS4 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 28h SRF Oh SRF control Enable counter a Content of the counter oe oe N 1 NX ___ FREGE 1 10114 released Counter starts Counter stops to count caused by the 2nd rising edge This figure shows the timing of the counter controlled by the CX pin Example SCC 0h Select the base clock of the frequency generator that comes from XT clock FRQX 1 5 set the frequency generator to FREQ PH0 6 3 79 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual the setting value of the frequency generator is 5 and FREQ has 1 3 duty waveform SHE 40h enable the halt release caused by 16 bit counter SRF 28h enable the counter controlled by the CX signal HALT PLC 40h release is caused by the 274 rising edge on CX and then clear the halt release request flag MRF1 10h read the content of the counter MRF2 11h MRF3 12h MRF4 13h 3 8 Key Matrix Scanning TM87P08 Only TM87P08 shares the timing of the LCD waveform to scan the key matrix circuitry These scanning output pins are SEG1 16 for easy to understand named these pins as K1 K16 The time sharing of the LCD waveform will n
138. ster 3 STS3 Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 7 15th stage ofthe Start condition flag 5 Start condition flag 4 SCF7 pre divider SCF5 5 4 palt Halt release caused Halt release caused by 1 underflow by INT pin by pre divider overflow Read only Read only Read only Read only 2 14 4 STATUS REGISTER 3X STS3X When the halt mode is released with start condition flag 2 SCF2 status register 3X STS3X will store the status of the factor in the release of the halt mode Status register 3X STS3X consists of 3 flags 1 Start condition flag 8 SCF8 43 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX User s Manual SCF8 is set to 1 when any one of KI1 4 71 0 KI1 4 1 LED mode KI1 4 0 in LCD mode causes the halt release request flag 5 HRF5 to be outputted and the halt release enable flag 5 HEF5 is set beforehand To reset the start condition flag 8 SCF8 the PLC instruction must be used to reset the halt release request flag 5 HRF5 or the SHE instruction must be used to reset the halt release enable flag 5 HEF5 2 Start condition flag 6 SCF6 SCF6 is set to 1 when an underflow signal from timer 2 TMR2 causes the halt release request flag 4 HRF4 to be outputted and the halt release enable flag 4 HEF4 is set beforehand To reset the start condition flag 6 SCF6 the PLC instruction must be used to reset the halt release request flag 4 HRF4 or the SHE ins
139. t Rx n 1 AC n 1 Rx0 ACO lt 1 The Rx content is shifted left and 1 is loaded to the LSB The results are loaded to the AC lt Rx3 lt Rx2 lt Rx1 lt Rx0 lt 1 87 2 87 2 87 4 87 8 lt Rx 8 Bit3 of the content of Rx is loaded to carry flag CF TM87R02 TM87P02 TM87P04 TM87P08 AC Rx lt CF The content of CF is loaded to AC and Rx The content of AC and meaning of bit after execution of this instruction are as follows Bit 3 CF Bit 2 AC 0 zero flag Bit 1 No Use Bit 0 No Use 5 3 OPERATION INSTRUCTIONS INC Rx Function Description INC HL Function Description INC OHL Function Description TM87R02 TM87P02 TM87P04 TM87P08 Rx AC lt Rx 1 Add 1 to the content of Rx the result is loaded to data memory Rx and AC Carry flag CF will be affected TM87P08 R HL AC lt R HL 1 Add 1 to the content of data memory specified by HL the result is loaded to data memory specified by HL and AC Carry flag CF will be affected TM87P08 HL AC R HL 1 HL 1 Adds 1 to the content of the result is loaded to the data memory HL and AC The content of the index register HL will be incremented automatically after executing this instruction The carry flag CF will be affected OHL indicates an index address of data memory 102 t
140. t level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state After the reset cycle the IOB port is set as input and each bit of port can be defined as input or output individually by executing SPB instructions Executing OPB instructions may 68 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual output the content of specified data memory to the pins defined as output mode the other pins which are defined as the input will still be input Executed IPB instructions may store the signals applied on the IOB pins into the specified data memory When the IOB pins are defined as the output executing IPB instruction will save the data stored in the output latch into the specified data memory Before executing SPB instruction to define the 1 pins as output the OPB instruction must be executed to output the data to the output latches This will prevent the chattering signal on the I O pin when the I O mode changed IOB port had built in pull down resistor and executing SPB instruction to enable disable this device 3 5 3 IOC PORT lOC1 IOCA4 pins are MUXed with SEG32 KI1 SEG33 KI2 SEG34 KI3 SEG35 KIA4 pins respectively by option OPTION table Option name Selected item SEG32 IOC1 KI1 2 IOC1 SEG33 IOC2 KI2 2 IOC2 SEG34 IOC3 KI3 2 IOC3 5 4 4 2 IOC4
141. t the data to those output latches beforehand This will prevent the chattering signal on the I O pin when the I O mode changed port had built in pull down resistor and executing SPA instruction to enable disable this device 65 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Initial clear bitO SPA 1 lt Q L IOA1 Initial clear SPA 2 Initial clear SPA 4 Initial D PA 8 lt V bit3 as IOA4 SPA 1 isa p OPA OPAS IPA This figure shows the organization of IOA port Note If the input level is in the floating state a large current straight through current flows to the input buffer The input level must not be in the floating state 3 5 1 1 Pseudo Serial Output IOA port may operate as a pseudo serial output port by executing OPAS instruction port must be defined as the output mode before executing OPAS instruction 1 BITO and 1 of the port deliver RAM data 2 BIT2 of the port delivers the constant value of the OPAS 3 BIT3 of the port delivers pulses Shown below is a sample program using the OPAS instruction 1 LDS OAH 0 2 OPA OAH SPA OFH LDS 15 3 OPAS 1 1 Bit 0 output shift gate open 66 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X User s Manual SRO 1 Shifts bit 1 to bit 0 OPAS 1 1 Bit 1 output SRO 1 Shifts bit2 to bit 0 OPAS 1 1
142. ted the AC must be the result of any added instruction The carry flag CF will be affected DAA HL TM87P08 Function AC R HL lt BCD AC Description Converts the content of AC to decimal format and then restores to AC and data memory specified by HL When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected AC data before DAA CF data before DAA AC data after DAA CF data after DAA execution execution execution execution 0 lt AC lt 9 A lt AC lt F AC 6 0 lt lt 3 6 DAA HL TM87P08 Function AC HL BCD AC HL 1 Description Converts the content of AC to binary format and then restores to AC and the data memory specified by HL The content of the index register HL will be incremented automatically after executing this instruction When this instruction is executed the AC must be the result of any added instruction The carry flag CF will be affected data before DAA CF data before AC data after DAA CF data after DAA execution Execution execution execution 0 lt AC lt 9 lt lt 6 0 lt lt 3 6 120 technology inc Rev 1 0 2006 04 11 Preliminary DAS Function Description DAS Rx Function Description DAS HL Function Description DAS HL Function Description 87
143. tes the K13 K16 columns simultaneously X4 Xo are not a factor X7X5X4 111 in this setting each scanning cycle checks two specified columns on the key matrix The specified columns are defined by the setting of Xs X gt and X1 X3X2X1 000 activates the K1 K2 columns simultaneously X3X2X4 001 activates the K4 columns simultaneously X3X2X1 110 activates the K13 K14 columns simultaneously X3X2X1 111 activates the K15 K16 columns simultaneously Xo is not a factor 98 tenx technology inc Rev 1 0 2006 04 11 Preliminary SPK Rx Function Description 87 User s Manual TM87P08 Sets the Key matrix scanning output state When 5 1 16 is are used for LCD driver pin s sets the contents of AC and Rx to specify the key matrix scanning output state for each SEGn pin in the scanning interval The bit setting is the same as the SPKX instruction The bit patterns of AC and Rx corresponding to SPKX are shown below Instruction Bit7 Bits Bit4 Bit2 Bit1 BitO SPKRx 2 AC1 ACO Rx3 Rx2 Rx1 SPKX X 7 X6 X5 X4 X3 X2 1 X0 SPK HL TM87P08 Function Sets the Key matrix scanning output state Description When SEG1 16 is are used for LCD driver pin s sets the content of table ROM QHL to specify the key
144. the predivider 9 The 9th stage output of the predivider PH11 The 11th stage output of the predivider PH13 The 13th stage output of the predivider PH15 The 15th stage output of the predivider 35 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual 8 When the TMR1 clock is FREQ TMR1 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 12 2 RE LOAD OPERATION TMR1 provides the re load function which can extend any time interval greater than 3Fh The SF 80h instruction enables the re load function and RF 80h instruction disables it When the re load function is enabled the TMR1 will not stop counting until the re load function is disabled and TMR1 underflows again During this operation the program must use the halt release request flag or interrupt to check the wanted counting value It is necessary to execute the TMS or TMSX instruction to set the down count value before the re load function is enabled because TMR1 will automatically count down with an unknown value once the re load function is enabled Never disable the re load function before the last expected halt release or interrupt occurs If TMS related instructions are not executed after each halt release or interrupt occurs the TMR1 will stop operating immediately after the re load function is disabled For example if the expected count down value is 500 it may be divided as 52 7 64 First set the ini
145. the program counter sequentially during subroutine call or execution of the interrupt service routine The contents of stack register are returned sequentially to the program counter PC while executing return instructions RTS The stack register is organized using 11 bits by 8 levels but with no overflow flag hence only 8 levels of subroutine call or interrupt are allowed If the stacks are full and either interrupt occurs or subroutine call executes the first level will be overwritten 30 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual Once the subroutine call or interrupt causes the stack register STACK overflow the stack pointer will return to 0 and the content of the level 0 stack will be overwritten by the PC value The contents of the stack register STACK are returned sequentially to the program counter PC during execution of the RTS instruction Once the RTS instruction causes the stack register STACK underflow the stack pointer will return to level 7 and the content of the level 7 stack will be restored to the program counter The following figure shows the diagram of the stack Stack pointer CALL instruction Interrupt accepted RTS STACK ring with first in last out function 2 7 DATA MEMORY RAM The static RAM is organized with 128 256 addresses x 4 bits and is used to store data The data memory may be accessed using two methods 1 Direct addressing mode
146. tiate count down value of TMR1 to 52 and start counting then enable the 1 halt release or interrupt function Before the first time underflow occurs enable the re load function The TMR1 will continue operating even though TMR1 underflow occurs When halt release or interrupt occurs clear the HRF1 flag by PLC instruction After halt release or interrupt occurs 8 times disable the re load function and the counting is completed 2 2 pis 7th 8th 64 64 Ru m p 6 count lt count TMS HRF1 PLC K 1 Re load In the following example S W enters the halt mode to wait for the underflow of TMR1 LDS 0 0 initiate the underflow counting register PLC 2 SHE 2 enable the HALT release caused by TMR1 TMSX 34h initiate the TMR1 value 52 and clock source is 09 SF 80h enable the re load function RE_LOAD HALT 36 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual INC 0 increase the underflow counter PLC 2 clear HRF1 JB3 END_TM1 if the TMR1 underflow counter is equal to 8 exit subroutine JMP RE_LOAD END_TM1 RF 80h disable the re load function 2 13 TIMER 2 TMR2 The following figure shows the TMR2 organization Re load RL2 5 2 instruction IEF Q Initial reset TM2 6 bit binary down Interrupt counter FREQ 3 5
147. tion Option name Selected item BIAS 2 1 2 BIAS BIAS 3 1 3 BIAS The frame frequency for each lighting system is shown below these frequencies can be selected by option All of the LCD frame frequencies in the following tables are based on the clock source frequency of the pre divider PHO is 32768 2 84 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual The LCD alternating frequency in 1 4 duty type Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 16Hz LCD frame frequency 2 TYPICAL 32Hz LCD frame frequency 2 FAST 64Hz The LCD alternating frequency 1 8 duty type 87 08 Only Option name Selected item Remark alternating frequency LCD frame frequency 1 SLOW 32Hz LCD frame frequency 2 TYPICAL 64Hz LCD frame frequency 2 FAST 128Hz The following table shows the relationship between the LCD lighting system and the maximum number of driving LCD segments Maximum Number of LCD Lighting System Driving LCD Segments Remarks 1 2 bias 1 4 dut 1 2 bias 1 8 duty 256 Connect VL3 to VL2 TM87P08 Only When choosing the LCD frame frequency it is recommended to chose a frequency higher than 24Hz If the frame frequency is lower than 24Hz the pattern on the LCD panel will start to flash 4 2 DC OUTPUT 87 8 Only TM87P08 permits LCD driver output pins COM5 COM
148. tion when heavy loading occurs Such as buzzer activation LED illumination etc Since heavy loading will cause a large voltage drop in the supply voltage the system will malfunction in this condition Once the program enters back up mode 1 32 768KHz Crystal oscillator will operate in a large driver condition and the internal logic function operates with a higher supply voltage TM87POX will get a higher power supply noise margin while back up mode is active but it will also receive an increase in power consumption The back up flag BCF indicates the status of the back up function BCF flag can be set or reset by executing the SF or RF instructions respectively The back up function has different performance corresponding to different power mode options shown in the following table 3V battery or higher mode TM87POX stat battery or higher mode flag status Initial reset cycle BCF 1 hardware controlled After initial reset cycle BCF 1 hardware controlled Executing SF 2h instruction BCF 1 Executing RF 2h instruction 0 HALT mode Previous state STOP mode BCF 1 hardware controlled 3V battery or higher mode BCF 0 BCF 1 32 768KHz Crystal Oscillator Small driver Large driver 87 Oscillation Note For power saving reasons it is recommended to reset flag to 0 when back up mode is not used 2 18 STOP FUNCTION STOP The stop fu
149. to DBUSH inputs and then sending them to each latch and strobe PSTB Oh to PSTB 1Fh is selected freely by option Of the 512 signals obtainable by combining DBUSA to DBUSH and PSTB Oh to PSTB 1Fh any one of 256 corresponding to the number of latch circuits incorporated in the hardware signals can be selected by programming the aforementioned segment PLA Table 2 7 shows the PSTB Oh to PSTB 1Fh signals Table 2 3 Strobe Signal for LCD Latch in Segment PLA and Strobe in LCT Instruction strobe signal for Strobe in LCT LCB LCP LCD LCD latch instructions The values of Lz in LCT Lz 0012 02 00 ce PSTBO 5 PSTB4 PSTB5 CH ugs s 1 Note The values of Q are the addresses of the working register in the data memory RAM In the LCD instruction Q is the index address in the table ROM The LCD outputs can be turned off without changing segment data The execution of the SF2 4h instruction may turn off the displays simultaneously The execution of the RF2 4h instruction may turn on the display with the patterns turned off These two instructions will not affect the data stored in the latch circuitry When executing the RF2 4h instruction to turn off the LCD the program can still execute LCT LCB LCP and LCD instructions to update the data in the latch circuitry The new content will be outputted to the LCD while the display is being turned on again In the stop state all COM and SEG outputs of
150. truction must be used to reset the halt release enable flag 4 HEF4 3 Start condition flag 9 5 9 SCF9 is set when a finish signal from mode of RFC function causes the halt release request flag 6 HRF6 to be outputted and the halt release enable flag 9 HEF9 is set beforehand In this case the 16 counter of RFC function must be controlled by CX pin please refer to 2 16 9 To reset the start condition flag 9 SCF9 the PLC instruction must be used to reset the halt release request flag 6 HRF6 or the SHE instruction must be used to reset the halt release enable flag 6 HEF6 The MCX instruction can be used to transfer the contents of status register 3X STS3X to the accumulator AC and the data memory RAM The following table shows the Bit Pattern of Status Register 3X STS3X Bit 3 Bit 2 Bit 1 Bit 0 Start condition flag 9 NA Start condition flag 6 Start condition flag 8 SCF9 SCF6 SCF8 Halt release caused by NA Halt release caused by Halt release caused by RFC counter finish TMR2 underflow S KI underflow Read only Read only Read only Read only TM87P08 Only 2 14 5 STATUS REGISTER 4 STS4 Status register 4 5 54 consists of 3 flags 1 System clock selection flag CSF The system clock selection flag CSF indicates which clock source of the system clock generator is used Executing SLOW instruction will change the clock source BCLK of the system clock generator to the slow speed oscillator XT cloc
151. unction Description TM87R02 TM87P02 TM87P04 TM87P08 Program counter jumps to X if ACO 1 If bitO of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH 121 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual JB1 X TM87R02 TM87P02 TM87P04 TM87P08 Function Program counter jumps to X if AC1 1 Description If bit of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH JB2 X TM87R02 TM87P02 TM87P04 TM87P08 Function Program counter jumps to X if AC2 1 Description If bit2 of AC is 1 jump occurs If O the PC increases 1 The range of X is from 000H to 7FFH or 800H to FFFH JB3 X TM87R02 TM87P02 TM87P04 TM87P08 Function Program counter jumps to X if AC3 1 Description If bit3 of AC is 1 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH JNZ X 87 2 87 2 87 4 87 8 Function Program counter jumps to X if AC 0 Description If the content of AC is not 0 jump occurs If 0 the PC increases by 1 The range of X is from 000H to 7FFH or 800H to FFFH JNC X TM87R02 TM87P02 TM87P04 TM87P08 Function Program counter jumps to X if CF 0 Description If the content of CF is 0 jump occurs If 1 the PC increases 1 The range of X is from
152. vention clock will stop due to the delivery of SCF3 The SCF3 will be reset to O by executing SCA instruction and the chattering prevention clock will be enabled at the same time If the SCF3 has been set to 1 the halt release request flag 0 HRFO will be delivered In this case if the port IOD interrupt enable mode IEFO is provided the interrupt is accepted Since no flip flop is available to hold the information of the signal at the input pins IOD1 to IODA the input data at the port IOD must be read into the RAM immediately after the halt mode is released 74 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual 3 6 EXTERNAL INT PIN The INT pin can be selected as pull up or pull down or open type by option The signal change either rising edge or falling edge by option sets the interrupt flag delivering the halt release request flag 2 HRF2 In this case if the halt release enable flag HEF2 is provided the start condition flag 2 is delivered If the INT pin interrupt enable mode IEF2 is provided the interrupt is accepted OPTION table For internal resistor type Option name Selected item INT PIN INTERNAL RESISTOR 1 PULL HIGH INT PIN INTERNAL RESISTOR 2 PULL LOW INT PIN INTERNAL RESISTOR 3 OPEN TYPE For input triggered type Option name Selected item INT PIN TRIGGER MODE 1 RISING EDGE INT PIN TRIGGER MODE 2 FALLING EDGE IEF2
153. ws MRF1 10h read the content of the counter MRF2 11h MRF3 12h 77 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87P0X Users Manual MRF4 13h MSD 20h JB2 CNT1_OF check the overflow flag of counter JMP DATA_ACCEPT CNT1_OF DEC 2 decrease the TM1 value LDS 20h 0 SBC 1 JZ CHG RANGE change the clock source of TMR1 PLC 1 clear the halt release request flag of TMR1 JMP RE CNT 3 7 3 Enable Disable the Counter by Timer 2 87 8 Only TMR2 will control the operation of the counter in this mode When the counter is controlled by SRF 18 instruction the counter will start to operate until TMR2 is enabled and the first falling edge of the clock source gets into TMR2 When the TMR2 underflow occurs the counter will be disabled and will stop counting the CX clock at the same time This mode can set an accurate time period with which to count the clock numbers on the CX pin For a detailed description of the operation of TMR2 please refer to 2 12 Each time the 16 bit counter is enabled the content of the counter will be cleared automatically SRF 18h SRF 02h Y SRF control Counter active Timer 2 3Fh Yoon h X 18h X Oh 3Fh Content of the counter 0 X 1 X 2X 3 N 1 NX N 1 a IC S 1 111 01111 release request counter starts Counting stops caused to count by the Timer 2 underflow This figure shows the timing of the RFC counter controlled by ti
154. ws the bit pattern for this instruction clock Setting value The clock source option for timer 1 0 0 n 5 TM87R02 TM87P02 TM87P04 TM87P08 Function Selects timer 1 clock source and preset timer 1 Description The data specified by X X8 is loaded to timer 1 to start the timer The following table shows the bit pattern for this instruction X3 The clock source setting for timer 1 O 0 0 PH9 PH E 0 1 1 FREQ 0 PH 1 0 1 PH 126 tenx technology inc Rev 1 0 2006 04 11 Preliminary TM87POX Users Manual 12 10 12 2 2 TM87R02 TM87P02 TM87P04 TM87P08 Function Selects timer 2 clock source and preset timer 2 Description The content of data memory specified by Rx and AC is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction OPCODE Select clock Initiate value of timer The clock source setting for timer 2 0 0 PH ERE ANI 1 o haz TM2 HL TM87P08 Function Selects timer 2 clock source and preset timer 2 Description The content of Table ROM specified by HL is loaded to timer 2 to start the timer The following table shows the bit pattern for this instruction The clock source setting for timer 2 oO 0 PH 01
155. x lt Rx AC Binary adds the contents of Rx and AC the result is loaded to AC and the data memory Rx The carry flag CF will be affected TM87P08 AC HL lt HL AC Binary adds the contents of HL and the result is loaded to and the data memory HL HL indicates an index address of data memory The carry flag CF will be affected TM87P08 AC HL HL AC HL HL 1 Binary adds the contents of HL and the result is loaded to and the data memory HL The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory The carry flag CF will be affected TM87R02 TM87P02 TM87P04 TM87P08 Rx AC B 1 Binary subtracts the content of AC from the content of Rx the result is loaded to AC The carry flag CF will be affected TM87P08 AC lt HL AC B 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC HL indicates an index address of data memory The carry flag CF will be affected TM87P08 AC HL AC B 1 HL HL 1 Binary subtracts the content of AC from the content of HL the result is loaded to AC The content of the index register HL will be incremented automatically after executing this instruction HL indicates an index address of data memory
156. y SIE instruction The bit pattern of control register 3 CTL3 is shown below Enable Request flag Interrupt flag No EF6 Enable the interrupt request caused by RFC counter to be finished HRF6 Interrupt 6 IEF5 Enable the interrupt request caused by Key Scanning HRF5 Interrupt 5 IEF4 Enable the interrupt request caused by TMR2 underflow HRF4 Interrupt 4 IEF3 Enable the interrupt request caused by predivider overflow HRF3 Interrupt 3 IEF2 Enable the interrupt request caused by INT pin HRF2 Interrupt 2 IEF1 Enable the interrupt request caused by TM1 underflow HRF1 Interrupt 1 IEFO Enable the interrupt request caused by IOC or 1OD port signal to be changed HRF 0 Interrupt 0 TM87P08 Only When any of the interrupts are accepted the corresponding HRFx and the interrupt enable flag IEF will be reset to 0 automatically Therefore the desirable interrupt enable flag IEFx must be set again before exiting from the interrupt routine 2 15 4 CONTROL REGISTER 4 CTL4 Control register 4 CTL4 being a 3 bit register is set reset by SRE instruction The following table shows the Bit Pattern of Control Register 4 CTL4 FIOR Id e SRF5 SRF4 SRF3 enable flag Sign reloads Enable the stop release Enable the stop release Enable the stop release fla request caused by signal request caused by signal request caused by signal q 9 change on INT pin HRF2 change on IOC change
157. y TM87POX User s Manual The following table shows the clock source setting for TMR2 PH Notes 1 When the TMR2 clock is PH3 TMR2 set time Set value error 8 1 fosc KHz ms 2 When the TMR2 clock is PH9 TMR2 set time Set value error 512 1 fosc KHz ms 3 When the TMR2 clock is PH15 TMR2 set time Set value error 32768 1 fosc KHz ms 4 When the TMR2 clock is PH5 TMR2 set time Set value error 32 1 fosc KHz ms 5 When the timer clock is PH7 TMR2 set time Set value error 128 1 fosc KHz ms 6 When the TMR2 clock is PH11 TMR2 set time Set value error 2048 1 fosc KHz ms 7 When the TMR2 clock is PH13 TMR2 set time Set value error 8192 1 fosc KHz ms Set value Decimal number of timer set value error the tolerance of set value 0 error 1 fosc Input of the predivider PH3 3rd stage output of the predivider PHn The nth stage output of the predivider n 5 7 9 11 13 8 When the TMR2 clock is FREQ TMR2 set time Set value error 1 FREQ KHz ms FREQ refer to section 3 3 4 2 13 2 RE LOAD OPERATION TMR2 also provides the re load function is the same as TMR1 The instruction SF2 1 enables the re load function the instruction RF2 1 disables it 38 tenx technology inc Rev 1 0 2006 04 11 Preliminary 87 User s Manual 2 13 3 TIMER 2 TMR2 IN RESISTOR TO FREQUENCY CONVERTER RFC TMR2 al

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