UltraSPARC IIi Addendum to User's Manual
Contents
1. DIMM pair 0 corresponds to DimmPairPresent 0 and so on A zero indicates not present a 1 indicates present These bits are set by software after probing Note that in 11 bit Column Address mode only DIMM Pair 0 and 2 can be marked present Pairs 1 and 3 should always be marked not present when in 11 bit column addressing mode Note Refresh must be disabled first by clearing the RefEnable bit before changing the memory controller register values Refresh may be enabled again simultaneously with writing DIMMPairPresent and RefInterval Failure to follow this rule may result in unpredictable behavior Table 18 5 Various Memory Configurations System memory DIMM size Base device No of devices min max config 8 MB IMx4 18 16 MB 64 MB 16 MB 2M x 8 9 32 MB 128 MB 32 MB 4M x 4 18 64 MB 256 MB 64 MB 4M x 4 banked 36 128 MB 512 MB 64 MB 8M x 8 9 128 MB 512 MB Chapter 18 MCU Control and Status Registers 267 Table 18 5 Various Memory Configurations Continued System memory DIMM size Base device No of devices min max config 128 MB 8M x 8 banked 18 256 MB 1 GB 128 MB 16M x 4 18 256 MB 1 GB 256 MB 16M x 4 banked 36 512 MB 1 GB RefInterval RefInterval specifies the interval time between refreshes in quanta of 32 CPU clocks SW should program RefInterval according to Table 18 6 Values given are in hexadecimal and derived from this formula refreshPeriod numberOfRows x ClockPeriod x 32 x numberOfPairs that is 322. UltraSPARC IIi CPU Highly Integrated 64 bit RISC L2 Cache DRAM PCI Interface SME1430 805 7291 UItraSPARC II CPU Module 360 440 480 MHz CPU 0 25 to 2 MB L2 Cache UPA64S 66 MHz PCI SME5431PCI 360 SME5431PCI 440 SME5431PCI 480 806 0480 UltraSPARC IIi Highly Integrated 64 bit RISC Processor PCI Interface SME1040 805 0086 User s Manuals UltraSPARC IIi User s Manual 805 0087 01 this addendum applies UltraSPARC IIi User s Manual 805 0087 02 no addendum required iv UltraSPARC IIi User s Manual Addendum June 1999 CHAPTER 18 MCU Control and Status Registers The MCU control and status registers program the operation of the shared memory and UPA64S interfaces which are integrated into the UItraSPARC II CPU Register Access Register accesses should always be of eight bytes at a time The Physical addresses for the MCU control and status registers are shown in Table 18 1 Table 18 1 MCU CSRs PA Register Name Associated I O Port 1FE 0000 F000 FFB Config FFB 1FE 0000 F010 Mem Control0 Memory Control Unit 1FE 0000 F018 Mem Control1 Memory Control Unit Reads of any size up to eight byte to any register are supported regardless of whether reads of that size makes sense Writes of any size up to eight bytes are also supported regardless of whether writes of that size makes sense Writes of any size may corrupt unwritten bits in the register that is writes may result in all eight bytes being
3. Table 18 4 Use of FFBwrToDRAMrdDly Processor Frequency 360 CASRW Trace_Delay 0 Trace_Delay 1 400 440 480 0 ajo a a 5 ao A 1 requires 50 ns DRAMs 2 not applicable or valid RefEnable Main memory is composed of dynamic RAMs which require periodic refreshing to maintain the contents of the memory cells RefEnable 1 is used to enable refresh of main memory RefEnable 0 disables refresh in memory UltraSPARC II User s Manual Addendum June 1999 POR is the only reset condition that clears RefEnable and initializes the rest of the Mem Control0 1 SOFT POR B POR B XIR and SOFT XIR leave RefEnable unchanged and refresh continues normally Any refresh operation in progress is aborted at the time of clearing this bit The truncated memory signals in this case could lead to loss of data 11 bit Column Address The default memory addressing only supports 10 bit column address DRAMs An additional mode was added to support a 11 bit column address Since the total available address bits in the memory controller is constant 1 Gbyte max addressable the maximum number of DIMM pairs in this mode is cut in half See Chapter 7 Ultra PARC IIi Memory System DIMMPairPresent lt 3 0 gt Indicates the presence absence of DIMMS to enable performance degradation caused by refreshing unpopulated DIMMs to be eliminated One bit position corresponds to each DIMM bank
4. assertions 011 6 6 CPU clocks between CAS and RAS assertions 100 7 7 CPU clocks between CAS and RAS assertions 101 8 8 CPU clocks between CAS and RAS assertions 110 reserved 2 CPU clocks between CAS and RAS assertions 111 reserved reserved CASRW CAS assertion for read write cycles CASRW controls the minimum CAS assertion time for reads and writes Chapter 18 MCU Control and Status Registers 271 272 There were originally separate fields for CAS during reads and CAS during writes However memory timing is optimal if writes and reads use the same CAS width Additionally an erratum caused the read CAS width to be used in one part of the write control logic Both fields are now given the same name and must be programmed to the same value Results are undefined if they are different Table 18 11 CASRW Assertion Time Mem_Control1 lt 20 18 gt same settings at lt 5 3 gt Argument SME1040 SME1430 Timing 000 3 reserved clocks for which CAS is in low state 001 4 4 clocks for which CAS is in low state 010 5 5 clocks for which CAS is in low state 011 reserved 6 clocks for which CAS is in low state 100 111 reserved reserved RCD RAS to CAS Delay RCD controls the RAS to CAS delay during the initial part of the read or write memory cycle In the SME1430 the RCD operation is determined by the RCD and Trace Delay Mem Control1 27 values Table 18 12 RCD Delay Timing Mem Control1 17 15 SME1430 Argument SME
5. be used to delay the clock for heavily loaded DIMM populations Current simulations indicate that the ARDC value need not be varied for the supported range and combinations of DIMM configurations Table 18 9 ARDC Timing Arguments Mem_Control1 lt 30 gt 26 24 Argument SME1040 SME1430 Timing 0000 0 0 default DRAM Read data clocking based on CAS assertion time 0001 1 1 CPU clocks of sampling delay 0010 2 2 CPU clocks of sampling delay UltraSPARC II User s Manual Addendum June 1999 Table 18 9 ARDC Timing Arguments Mem_Control1 lt 30 gt 26 24 Continued Argument SME1040 SME1430 Timing 0011 3 3 CPU clocks of sampling delay 0100 4 4 CPU clocks of sampling advancement 0101 3 3 CPU clocks of sampling advancement 0110 2 2 CPU clocks of sampling advancement 0111 1 1 CPU clocks of sampling advancement 1000 reserved 8 CPU clocks of sampling advancement 1001 reserved 7 CPU clocks of sampling advancement 1010 reserved 6 CPU clocks of sampling advancement 1011 reserved 5 CPU clocks of sampling advancement 1100 1111 reserved reserved CSR CAS before RAS delay timing This Instruction controls the CAS assertion to RAS assertion delay for CAS before RAS CBR refresh cycles Table 18 10 CSR Delay Timing Mem_Control1 lt 23 21 gt Argument SME1040 SME1430 Timing 000 3 3 CPU clocks between CAS and RAS assertions 001 4 4 CPU clocks between CAS and RAS assertions 010 5 5 CPU clocks between CAS and RAS
6. for slower clock cycles advance or for later data clocking for fast clock cycles Delaying this clocking by a cycle relative to the recommended values may be useful if timing is critical but it reduces hold time margin Chapter 18 MCU Control and Status Registers 269 270 Table 18 8 AMDC Timing Arguments Mem_Control1 lt 31 gt lt 29 27 gt Argument SME1040 SME1430 Timing 0000 0 0 default MemData clocking 0001 1 1 CPU clocks of sampling delay 0010 2 2 CPU clocks of sampling delay 0011 3 3 CPU clocks of sampling delay 0100 4 4 CPU clocks of sampling advancement 0101 3 3 CPU clocks of sampling advancement 0110 2 2 CPU clocks of sampling advancement 0111 1 1 CPU clocks of sampling advancement 1000 1010 reserved reserved 1011 reserved 5 CPU clocks of sampling advancement 1100 1111 reserved reserved ARDC Advance Read Data Clock Maintaining a minimum EDO DRAM CAS cycle is difficult if the DIMM loading is widely variable Light loading on the CAS and DATA lines can make the data disappear before it is clocked and produce a hold time problem The system board reference design specifies buffering to make the RAS CAS WE delays independent of the number of DIMMs in circuit However the ADDR and DATA delays do vary with DIMM population If necessary this field can be used to advance the clock that latches read data in the transceivers This may be necessary when only one or two DIMM pairs are populated It can also
7. of the SRAM size or connections to the E tag 101 allows a 512 kilobyte E cache if the SRAMs used are sized appropriately Otherwise the E cache is the size allowed by the SRAMs 100 allows a 1 Mbyte E cache 011 allows a 2 Mbyte E cache the largest supported by UltraSPARC IIi Behavior for other encodings is Reserved PCON 7 0 Unused on UItraSPARC II Read as 0 MIDI4 0 Module processor ID register Read as 0 PCAP 16 0 Read as 0 on UItraSPARC II Resets are described more fully in Section 17 Chapter 18 MCU Control and Status Registers 277 278 UltraSPARC IIi User s Manual Addendum June 1999
8. 1040 Timing Trace Delayz1 Trace DelayzO 000 6 13 13 001 7 17 17 010 8 20 19 011 11 11 12 CPU clocks between RAS and CAS assertion 100 12 19 18 101 14 14 14 110 15 15 15 111 reserved reserved reserved UltraSPARC II User s Manual Addendum June 1999 CP CAS Precharge CP controls the CAS precharge time in between page cycles The argument in this field must equal the common argument in each CASRW field Mem_Control1 lt 20 18 gt and Mem_Control1 lt 5 3 gt Table 18 13 CP CAS Precharge Time Mem_Control1 lt 14 12 gt Argument SME1040 SME1430 Timing 000 3 reserved CPU clocks of CAS Precharge 001 4 4 CPU clocks of CAS Precharge 010 5 5 CPU clocks of CAS Precharge 011 reserved 6 100 111 reserved reserved RP RAS Precharge RP controls the RAS precharge time between memory cycles Table 18 14 RP Timing Mem_Control1 lt 11 9 gt Argument SME1040 SME1430 Timing 000 8 12 001 9 13 010 10 21 011 H 17 CPU clocks of RAS Precharge 100 12 19 101 14 14 110 15 15 111 reserved 16 RAS RAS is used to control the length of time that RAS is asserted during refresh cycles Chapter 18 MCU Control and Status Registers 273 Table 18 15 RAS Duration Time Mem_Control1 lt 8 6 gt Argument SME1040 SME1430 Timing 000 13 20 001 15 15 010 18 18 011 22 22 CPU clocks of RAS assertion 100 23 23 101 24 24 110 reserved 27 111 reserved 31 RSC RAS after CAS delay timing RSC controls time to deas
9. 17 15 14 12 11 9 8 6 5 3 2 0 POR State M oO gH N 4 N N O O O oc oc O 0 Description reserved Read as zero write 0 SME1430 Advance Memdata Clock SME1430 Advance Read Data Clock SME1040 reserved read as zero write 0 Advance Memdata Clock Advance Read Data Clock CAS to RAS delay for CBR refresh cycles CAS length for read write RAS to CAS Delay CAS Precharge RAS Precharge Length of RAS for Refresh Must be same as 20 18 RAS after CAS hold time Type RO R W R W RO R W R W R W R W R W R W R W R W R W R W 1 Bit definitions differ between SME1430 and SME1040 See bit definition sections that follow 2 Originally had separate fields for CAS during reads and CAS during writes However memory timing is op timal if writes and reads use the same CAS width Additionally an errata caused the read CAS width to be used in one part of the write control logic Both fields are now given the same name and must be programmed to the same value Results are undefined if they are different Even though many bits are set by reset it is good practice to have the boot PROM program all memory control register bits when initializing the system AMDC Advance Memdata Clock This instruction moves the relative timing between a transceiver clock transition and the point at which the processor latches read data driven by that transceiver using the MEMDATA bus This timing adjustment allows for earlier data clocking
10. UltraSPARC II User s Manual Addendum For Use with UltraSPARC IIi User s Manual 805 0087 01 4 Sun microsystems THE NETWORK IS THE COMPUTER Microelectronics 901 San Antonio Road Palo Alto CA 94303 USA 800 681 8845 http www sun com microelectronics June 1999 Copyright 1999 Sun Microsystems Inc All Rights reserved THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED AS IS WITHOUT ANY EXPRESS REPRESENTATIONS OR WARRANTIES IN ADDITION SUN MICROSYSTEMS INC DISCLAIMS ALL IMPLIED REPRESENTATIONS AND WARRANTIES INCLUDING ANY WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS This document contains proprietary information of Sun Microsystems Inc or under license from third parties No part of this document may be reproduced in any form or by any means or transferred to any third party without the prior written consent of Sun Microsystems Inc Sun Sun Microsystems and the Sun Logo are trademarks or registered trademarks of Sun Microsystems Inc in the United States and other countries All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International Inc in the United States and other countries Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems Inc The information contained in this document is not designed or intended for use in on line cont
11. fig Register O0x1FE 0000 F000 Field Bits Description Reset Type Reserved 63 28 0 RO SPROS 27 24 Slave P request queue size Initialize to max size 1 R W in 2 Cycle Packets of the corresponding slave request queue Reserved 23 15 0 RO Oneread 14 Always set to one UPA slave interface does 1 RO not support multiple outstanding reads Reserved 13 0 0 RO 264 UltraSPARC lIIi User s Manual Addendum June 1999 The Data Queue Size is not tracked separately and the UPA64S device must be able to receive 64 bytes per allowed outstanding request 18 2 Mem Control0 Register Table 18 3 Mem Control0 Register O0x1FE 0000 F010 Field Bits Description POR Type Reserved 63 32 0 RO RefEnable 31 Refresh enable 0 R W Reserved 30 29 0 RO ECCEnable 28 Enable all ECC functions 0 R W Trace Delay 27 SME1430 short trace enable 0 R W Reserved 27 SME1040 0 R W FFBwrToDRAMrdDly 26 25 SME1430 memdata bus 0 R W turnaround Reserved 24 13 SME1430 RO Reserved 26 13 SME1040 0 RO 11 bit Column Address 12 Enables 11 bit column address 0 R W mode DIMMPairPresent lt 3 0 gt 11 8 Determines which DIMM pairs to OxF R W refresh RefInterval lt 7 0 gt 7 0 Interval between refreshes Each 0x30 R W encoding is 32 processor clocks ECCEnable This instruction enables the MCU to perform single bit detect and correct and notification of single or multi bit errors to the ECU and PBM for possible logging and trap interrupt genera
12. frequency 1000 2048 32 DIMM pairs refValue This data is based on using 16 MB 2048 rows 32ms EDO drams only this configuration matches the composite DIMM specification See Table 18 6 Table 18 6 Refresh Period in 32x CPU clock periods as a Function of Frequency Total DIMM pairs 125 enabled 166 1 0x51 2 0x28 3 0x1B 4 0x14 CPU Frequency in MHz 167 201 225 251 271 301 331 361 401 441 451 200 224 250 270 300 330 360 400 440 450 480 0x61 0x6C Ox7A 0x83 0x92 OxA1 OxAF 0xC3 OxD6 OxDB OxEA 0x30 0x37 0x3D 0x41 0x49 0x50 0x57 0x61 Ox6B 0x6D 0x75 0x20 0x25 0x28 Ox2B 0x30 0x35 Ox3A 0x41 0x47 0x49 0x4E 0x18 Ox1D Ox1E 0x20 0x24 0x28 Ox2B 0x30 0x35 0x36 Ox3A 18 3 268 Mem_Control1 Register Memory Control Register 1 contains fields that control the read write and refresh timing for the DRAM DIMMs They allow software to optimize the memory access timing for a particular system frequency The contents of Memory Control Register 1 can be changed as required by an electrical tuning of memory timing often based on SPICE analysis The Mem_Control1 register bits are listed in Table 18 7 UltraSPARC II User s Manual Addendum June 1999 Table 18 7 Mem Control1 Register O0x1FE 0000 F018 Field Reserved AMDC lt 3 gt ARDC lt 3 gt Reserved AMDC lt 2 0 gt ARDC lt 2 0 gt CSR CASRW RCD CP RP RAS CASRW RSC Bits 63 32 31 30 31 30 29 27 26 24 23 21 20 18
13. odule for SME1430LGA sapphire red Both the SME1430LGA and the SME1040CGA UItraSPARC IIi processors are housed in the same LGA package The SME1430LGA CPU used in this module contains functional improvements This module also employs a heatsink of revised design but the overall dimensions remain as before UltraSPARC II User s Manual Addendum June 1999 Electrical and Thermal Differences Voltage Requirements CPU core supply voltage V pp cogs is reduced from 2 6 V to 1 9 V This change is achieved by implementing the appropriate resistor stuffing configuration in the module to set the VID 4 0 bits on the system board See the module datasheet listed in References Power Consumption Power consumption is reduced at a given frequency with an associated reduction in heat dissipation Temperature and Cooling The CPU runs at a reduced junction temperature Tj The module heatsink is changed to a straight fin design This requires airflow in line with the fin See the module datasheets for thermal information Functional Differences UPA Bus Frequency The UPA bus is clocked at 1 4 the CPU core frequency Memory Controller A number of timing template bits in Mem Control0 and Mem Controll registers have changed to support higher internal clock rates with the same DIMM timing For details refer to the Chapter 18 update in the succeeding pages of this addendum UltraSPARC Ili Enhancements iii References Datasheets
14. pecification It is possible that alternate values may give higher performance from 50 ns DRAM The minimum CAS cycle with this programming is 26 5 ns 13 25 ns CAS assertion at 300 Mhz Table 18 17 Mem_Controll hexadecimal values as a function of CPU frequency CPU Frequency in SME1040 SME1430 una 60 ns DRAM 50ns DRAM 60nsDRAM 50 ns DRAM 480 5E28 25D3 4E69 AF93 450 to 479 544E BIDA 4E69 A792 401 to 449 544C B9DD 410A AD54 361 to 400 0C4B 2794 0005 92CB 334 to 360 0C4A AB14 0645 9ACB 0C4A AB14 0645 9ACB 271 to 333 0645 9ACB 0645 9ACB 225 to 270 0626 168A 0626 168A 167 to 224 3800 8241 3800 8241 125 to 166 3E00 8000 3E00 8000 0 1 3D00 0000 5D00 0000 1 This programming is included for emulation The PLLs should be bypassed and an external means of supplying DRAM refresh should be provided 2 Excepting the 334 to 360 MHz range SME1040 programming for 50 and 60 ns DRAMs is currently the same Either DRAM rating can be used with the same performance 3 Speeds above 440 MHz have not been tested Chapter 18 MCU Control and Status Registers 275 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1110 9 8 7 6 5 4 383 2 1 Lu Des eee se e e s esse oe o E aroc s 210 Figure 18 1 Mem Control1 Register Bit Allocation Initialization of the Mem Control registers should be performed in accordance with the probing algorithm described in Section A 10 Memory Probing and Initiali
15. rol of aircraft air traffic aircraft navigation or aircraft communications or in the design construction operation or maintenance of any nuclear facility Sun disclaims any express or implied warranty of fitness for such uses UltraSPARC II Enhancements This addendum is meant to be used in conjunction with The UltraSPARC Ili User s Manual 805 0087 01 this addendum applies to It explains the additional features and differences between the original SME1040 UItraSPARC IIi Sabre CPU and the SME1430LGA Sapphire Red CPU This accounting of the changes is to appear in the forthcoming UltraSPARC IIi User s Manual 805 0087 02 updated version Following brief descriptions of the enhancements of the SME1430LGA product both at the chip and CPU module level this addendum includes the revised Chapter 18 MCU Control and Status Registers that is to appear integrated ino the User s Manual update Note that page numbers and cross references that appear in this section are aligned with pages in the forthcoming 02 update However most of the sections can be found on nearly corresponding pages in the current manual SME1430LGA CPU Enhancements Over the SME1040CGA CPU Both SME1430LGA and SME1040CGA UltraSPARC IIi CPU processors are housed in the same LGA package but the SME1430LGA chip contains functional improvements Electrical and Thermal Differences m Core supply voltage Vdd core is reduced from 2 6 V to 1 9 V m Power consump
16. sert RAS after CAS at the end of a memory cycle Table 18 16 RSC RAS Deassert Time Mem_Control1 lt 2 0 gt Argument SME1040 SME1430 Timing 000 4 4 CPU clocks RAS asserted after CAS 001 5 5 CPU clocks RAS asserted after CAS 010 6 6 CPU clocks RAS asserted after CAS 011 7 7 CPU clocks RAS asserted after CAS 100 8 8 CPU clocks RAS asserted after CAS 101 9 9 CPU clocks RAS asserted after CAS 110 reserved 10 CPU clocks RAS asserted after CAS 111 reserved reserved 18 4 Programming Mem Controll 274 Table 18 17 gives program values to support one two three or four DIMM pairs with one or two banks of DRAM on each DIMM These values are given as a function of the internal CPU operating frequency These tabulated values depend upon the conditions UltraSPARC II User s Manual Addendum June 1999 The system board meeting the min max delay specifications for RAS CAS MEMADDR DATA MEMDATA and all transceiver control and clock signals The design specifications for max skew between RAS CAS MEMADDR DATA being met The specified DIMMs being used buffered CAS WE ADDR Memory Control Register programming may also be used to utilize memory subsystems whose performance lies outside the suggested design specifications Because all skew and hold time relationships for the DRAMs are not programmable it is recommended that all designs meet the etch length specifications and employ DIMMs that meet the composite s
17. tion In general this should always be set to 1 unless DIMMs that do not support check bits are used There are further enables for ECC related trap and interrupt generation in the ECU and PBM See Section 16 6 1 E cache Error Enable Register on page 240 and DMA UE CE interrupt mapping registers in Partial Interrupt Mapping Registers on page 301 and ERRINT_EN in PCI Control Status Register on page 281 Chapter 18 MCU Control and Status Registers 265 266 Trace Delay SME1430 only Trace Delay is defined in mem control1 27 Set to 1 for SME1040 type timing Set to 0 for shorter trace delays This bit defaults to 0 at power up The impact on programming is shown in the Mem Controll Register RCD field see page 272 and the FFBwrToDRAMradDly section below FFBwrToDRAMrdDly SME1430 only FFBwrToDRAMrdDly is defined in mem_control1 lt 26 25 gt An FFB write operation followed by a DRAM read operation is optimized by using this 2 bit field This bit field value is adjusted according to CPU clock rate and DRAM speed FFBwrToDRAMrdDly value adjusts the delay in the initiation of a DRAM read after an FFB write operation so that there is no collision on the memory bus between data returning from DRAM and data written to the FFB The value 11 gives the smallest delay whereas the value 00 gives the largest delay Table 18 4 shows the use of FFBwrToDRAMrdDly for various configurations of processor frequency and setting of CASRW
18. tion ia reduced at a given frequency with an associated reduction in heat dissipation m The CPU runs at a reduced junction temperature Tj Functional Differences Synchronizer Stages Pin P03 has been redefined to SYNC 3TO1 MODE This function was added to allow for a third synchronizer stage should it prove necessary to ensure stability In fact this feature proved unnecessary and it is recommended that this pin be strapped to ground causing the processor to operate as the SME1040CGA in this regard The UltraSPARC Ili CPU has a time domain boundary between the CPU core and the PCI primary bus interface This pin controls the number of CPU clocks that the CPU waits for the synchronizers to settle If set to a 1 the CPU waits for 3 CPU clock cycles If set to a 0 the CPU waits two CPU clocks This pin has a weak internal pull down resistor that is enabled during RAMTEST and RESET modes CPU to UPA Clock Frequency Ratio The CPU to UPA clock ratio is fixed by design In the SME1040CGA the ratio is always 3 1 In SME1430LGA the ratio is 4 1 Memory Controller Bits A number of timing template bits and their definitions in Mem Control0 and Mem Control1 registers have changed to support higher internal clock rates with the same DIMM timing For details refer to the addendum to the UltraSPARC II User s Manual Enhancements in the SME543xPCI CPU Module Compared with the SME5421MCZ Version There are minor changes to the II CPU m
19. written regardless of the indicated write size Software must ensure that only the proper sized that is equal to the register size accesses are used No hardware checking is performed Block 64 byte access erroneously causes a UPA64S or PCI transaction with an undefined address Misaligned access due to not setting the E bit correctly in the TTE also yields unpredictable results 263 Note Register bits that are designated as read only RO are not affected by writes No errors are reported Fields with reserved definitions should not be used Some combinations of bits are not valid Disable refresh before changing memory control registers Compatibility Note Prior UltraSPARC based systems used other hardware and programming models to control the UPA and memory interfaces Reset Memory Control registers are reset to their initial values only during PowerOnReset POR POR is often generated by logic connected to the POWER OK signal from the power supply Refreshing operates continuously during and after other reset conditions The SYS RESET signal is asserted by the system POR condition The P RESET signal is asserted for many reasons and does not affect many of the memory control register bit values Table headings with POR mean the register is affected by SYS RESET only Table headings with Reset mean the register is affected by SYS RESET or P RESET 18 1 FFB Config Register Table 18 2 FFB Con
20. zation on page 381 Note The Mem Control register must be initialized before any memory operation including refresh Before modifying the register software must complete and inhibit all memory references and disable refresh Wait 100 clock periods after disabling refresh to guarantee completion of any refresh in progress 18 5 UPA Configuration Register The UPA CONFIG register can be accessed at ASI 0x4A VA 0 This is a 64 bit register non 64 bit aligned accesses cause a mem address not aligned trap Much of the UltraSPARC I and UltraSPARC II functionality in this register is removed UltraSPARC IIi uses a register in the Memory Control Unit to restrict the number of outstanding UP645 slave requests instead of this register The new ELIM field is copied from UltraSPARC II E TumT m we e SEY 63 3635 3332 22 21 17 16 0 Figure 18 2 UPA_CONFIG Register Format 276 JUIltraSPARC Il User s Manual Addendum June 1999 ELIM This field can be used to zero upper bits of the E cache tag address if more address pins are used on the tag RAM than necessary It can also be used to force the use of a smaller E cache size than is supplied with the UltraSPARC IIi system Resets to 000 Must be set to a size not bigger than the E cache data SRAMs provide otherwise incorrect E cache operation will result 000 has no effect on the E cache tag address 111 and 110 zero the 3 MSBs to create a 256 kilobyte E cache regardless
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