User Manual User Manual
Contents
1. Net Type FPGA Net Type FPGA E Pin E Pin 5 5 1 GND GND 60 5V PWR 2 IC_BB_L_IO_L20N_2_n75 IO Y14 59 5V PWR 3 IC_BB_L_IO_L20P_2_n75 IO W14 58 GND GND 4 GND GND 57 5V PWR 5 IC_BB_L_IO_L6N_2 IO 14 56 5V PWR 6 IC_BB_L_IO_L6P_2 IO 14 55 GND GND 7 GND GND 54 5V PWR 8 IC BB L IO I2IN 2 IO 15 53 5V PWR 9 IC_BB_L_IO_L21P_2 IO Y15 52 GND GND 10 GND GND 51 5V PWR 11 IC_BB_L_IO_L19N_2 IO AB16 50 5V PWR 12 IC_BB_L_IO_L19P_2 IO AA16 49 GND GND 13 GND GND 48 RFU 14 IC_BB_L_IO_L44N_2_n75 IO Y10 47 RFU 15 IC_BB_L_IO_L44P_2_n75 IO W10 46 GND GND 16 GND GND 45 RFU 17 IC_BB_L_IO_L42N_2_n75 IO wil 44 18 IC BB L IO LA42P 2 n75 IO 43 GND GND 19 GND GND 42 IC BB L IO L5N 2 n75 IO 18 20 BB L IO LA6N 2 175 IO 010 41 IC BB L IO 15 2 175 IO 17 21 IC L IO LA6P 2 n75 IO T10 40 GND GND 22 GND GND 39 IC BB L IO L71IN 1 n25 IO P18 23 IC BB L IO L59N 2 n75 IO R8 38 IC BB L IO L71P 1 n25 IO P17 24 IC BB L IO L59P 2 n75 IO R9 37 GND GND 25 GND GND 36 IC BB L IO L73N 1 n25 IO T18 26 IC BB L IO 1173 2 n75 IO WI5 35 IC BB L IO L73P 1 n25 IO T19 27 IC BB L IO 117 2 n75 IO Y16 34 GND GND 28 GND GND 33 IC BB L IO L58N 1 n25 IO N15 29 IC_BB_L_IO_L18N_2_n75 IO WI13 32 IC BB L IO L58P 1 n25 IO M16 30 IC_BB_L_IO_L18P_2_n75 IO V13 31 GND GND Tab 10 Bottom side expansion connector right signal connection2. V X7R MLCCs Net Type FPGA Net Type FPGA E Pin E Pin Sg 5 1 GND GND 80 BEXT L IO 0 HSDIO E5 2 BEXT L IO L58P 3 n25 HSDIO H4 79 BEXT L IO LAN 0 HSDIO E6 3 BEXT L IO L58N 3 n25 HSDIO G4 78 GND GND 4 GND GND TI BEXT L IO 12 0 HSDIO D4 3 BEXT L IO L82P 3 n25 HSDIO F5 76 BEXT L IO L2N 0 HSDIO D5 6 BEXT_L_IO_L82N_3_n25 HSDIO G6 75 GND GND 7 GND GND 74 BEXT L IO L7P 0 HSDIO F7 8 BEXT L IO L80P 3 n25 HSDIO H6 73 BEXT L IO L7N 0 HSDIO F8 9 BEXT L IO L80N 3 n25 HSDIO G7 72 GND GND 10 GND GND 71 L IO L32P 0 HSDIO G8 11 L IO L81P 3 n25 HSDIO J7 70 BEXT_L_IO_L32N_0 HSDIO F9 12 BEXT L IO L81N 3 n25 HSDIO H8 69 GND GND 13 GND GND 68 BEXT L IO L34P 0 GCLK G9 14 BEXT L IO L35P 0 GCLK H12 67 BEXT L IO L34N 0 GCLK F10 15 BEXT L IO L35N 0 GCLK G11 66 GND GND 16 GND GND 65 BEXT L IO L3P 0 HSDIO B2 17 BEXT L IO L33P 0 HSDIO H10 64 BEXT_L_IO_L3N_0 HSDIO A2 18 BEXT_L_IO_L33N_0 HSDIO Hil 63 GND GND 19 GND GND 62 BEXT L IO L5P 0 HSDIO B3 20 25 PWR 61 BEXT_L_IO_L5N_0 HSDIO A3 21 2 5 PWR 60 GND GND 22 GND GND 59 BEXT_L_IO_L6P_0 HSDIO C4 23 2 5 PWR 58 BEXT_L_IO_L6N_0 HSDIO A4 24 2 5 PWR 57 GND GND 25 GND GND 56 BEXT L IO L8P 0 HSDIO C5 26 3 3 V PWR 55 BEXT L IO L8N 0 HSDIO A5 27 3 3 V PWR 54 GND GND AUM AHED MB 23 User Manual AHED MB v2
3. AUM_AHED_MFB_MB 21 User Manual AHED MB v2 1 020414a 10 4 Side Expansion Connectors Two Hirose FX8 Series connectors connector capable of up to 3 125 Gbit s In principle stacking heights from 5 mm to 16 mm in standard configuration FX8C 80S SV5 10 11 12 14 or 16 mm The internal 2 5 V and 3 3 V supply rails are made available on each of the connectors to the external circuit 0 4 A max per contact Care should be taken when the XC6SLX25T or XC6SLX75T FPGAs are supposed to be used because several IOs are not available on these devices see Explanation of Signal Names Up to two MGT lanes with reference clock input are made available on each of the two connectors signals are routed as 100 Ohm differential pairs with tight length matching to allow for data rates up to the maximum of the respective FPGA pins 1080 Mbit s for general FPGA IOs 3 2 Gbit s for MGTs AUM AHED MFB MB 22 User Manual AHED MB v2 1 020414a 10 4 1 Left side as seen from the RJ 45 Jacks Upto 15 differential pairs gt 30 single ended IOs e jloutof 15 LVDS input and output capable 4 out of 15 only LVDS input capable due to FPGA bank 3 restrictions 2MGT lanes of FPGA Bank 101 e TL REFCLKIP C11 TL REFCLKIN D11 are connected to alow jitter differential 125 MHz on board clock signal e TL REFCLKOP TL REFCLKON are AC coupled via 100 nF 16
4. 1 DDR3 SDRAM Memory board features two 16 bit wide I Gbit 128 Mbyte DDR3 SDRAM memory chips These chips are connected to the dedicated Memory Controller Blocks MCBs within the FPGA accessible via bank 3 For detailed pinning information please refer to the constraint file ucf 3 2 Flash Memory This board is equipped with a 256 Mbit 32 Mbyte Quad SPI flash typically a S25FL256S device by Spansion In Quad Read DDR mode data transfer rates of up to 66 Mbyte s can be achieved request a sample bitstream and Windows application can be provided for writing bitstream and or processor code into the SPI flash via UDP connection from a Windows PC Net FPGA Signal Standard Description Pin SPI_CONFIG_CS AA3 LVCMOS33 Chip select signal active low SPI_CONFIG_CLK Y20 LVCMOS33 Clock signal from FPGA to SPI Flash SPI_CONFIG_MISO AA20 LVCMOS33 in mode from SPI Flash to FPGA SPI CONFIG MISO2 R13 LVCMOS33 WPn VPP DQ required for 4x interface SPI MISO3 T14 LVCMOS33 HOLDn DQ3 required for 4x interface SPI CONFIG MOSI AB20 LVCMOS33 DQO in 1x mode from FPGA to SPI flash Tab 2 SPI Flash signal connection AUM AHED MFB MB 9 User Manual AHED MB v2 1 020414a 3 3 Ethernet Interfaces 3 3 1 1000 Mbit s Implemented via a Marvell Alaska Ethernet PHY chip 88E1111 Attached in RGMII m
5. 1 020414a 28 GND GND 53 2 RFU 29 3 3 V PWR 52 RFU 30 33V PWR 51 GND GND 31 GND GND 50 MGT TL TXOP MGT B6 32 MGT TL RXOP MGT D7 49 MGT TL TXON MGT A6 33 MGT TL RXON MGT C7 48 GND GND 34 GND GND 47 MGT TL TXIP MGT B8 35 MGT TL RXIP MGT D9 46 MGT TL TXIN MGT 8 36 TL RXIN MGT C9 45 GND GND 37 GND GND 44 MGT TL REFCLKON MGT B10 38 RFU 43 MGT TL REFCLKOP MGT A10 39 42 GND GND 40 GND GND 41 RFU Tab 11 Top side expansion connector left signal connection AUM AHED MFB MB 24 User Manual AHED MB v2 1 020414a 10 4 2 Right side as seen from the RJ 45 Jacks Up to 15 differential pairs gt 30 single ended IOs e jloutof 15 LVDS input and output capable 4 out of 15 only LVDS input capable due to FPGA bank 1 restrictions 2 MGT lanes of FPGA Bank 123 e MGTs not available for XC6SLX25T e REFCLKOP REFCLKON are AC coupled via 100 nF 16 V X7R MLCCs Net Type FPGA Net Type FPGA E Pin E Pin Sg 5 1 GND GND 80 BEXT L IO L50N 0 HSDIO 17 2 IO 1213 1 n25 HSDIO K16 79 BEXT L IO L50P 0 HSDIO C17 3 BEXT IO L21P 1 n25 HSDIO 115 78 GND GND 4 GND GND 77 L IO L63N 0 HSDIO A18 2 BEXT IO L9N 1 n25 HSDIO H17 76 L IO L63P 0 HSDIO B18 6 BEXT R IO L9P 1 n
6. AHED AHMD RX left and DVI TX module AHED AHMD DRL TX right nere m r1 Fig 9 Top side view of camera module ADAPT EV76C560 CS connected to AHED MFB MB AUM AHED MFB MB 29 User Manual AHED MB v2 1 020414a A base board is recommended for the FPGA board AHED MP It features a robust wide range 12 V to 24 power input and can be equipped with communication module e g RS232 Fig 10 Top side view of AHED MFB BB LED SIO32X A Carrier board needed in case the top side expansion modules AHED AHMD DRL DVI RX AHED AHMD DRL DVI TX or AHMD MIC are supposed to be used on the FPGA board AHED MFB MB Fig 11 Top side view of carrier board AHED MFB MB CB AHMD DRL DVI RX module AHED AHMD AHED AHMD DRL DVI RX AUM AHED MFB MB 30 User Manual AHED MFB v2 1 020414a DVI TX module AHED AHMD DRL DVI TX Gigabit s Ethernet module AHED AHMD DRL MIC Camera headboard for the camera connector on the FPGA board MFB AUM AHED A Fig 13 Top side view of DVI TX module AHED AHMD DRL DVI TX Fig 14 Top side view of IGbit s Ethernet module AHED AHMD DRL EIG MIC Fig 15 Top side view of camera module AHED CAM ADAPT EV76C560 CS 31 User Manual AHED
7. expansion connectors allowing for serial high speed connectivity like PCI express SATA DisplayPort or High Speed ADCs DACs with JESD204 interface 1x 10 100 1000 Mbit s tri speed Gigabit Ethernet PHY Marvell 88E1111 magnetics and RJ45 Jack onboard 2x 10 100 Mbit s Ethernet PHY SMSC LAN8720A magnetics and RJ45 Jacks onboard 2x 16 bit wide 1Gbit 128 Mbyte DDR3 SDRAM 1x Quad SPI NOR Flash 256Mbit 32 Mbyte JTAG connector with included adapter compatible to standard Xilinx JTAG cable For XC6SLX75T XC6SLX100T or XC6SLX150T bitstream encryption AES256 with onboard battery for volatile key in SRAM Each Spartan 6 FPGA includes a unique 56 bit Device DNA for unambiguously identifying a board Apart from that the Spansion SPI flash features a One Time Programmable OTP array of 1024 bytes Bottom side expansion connectors 2x FX8C 60P SV6 e Hirose FX8 Series up to 3 125 Gbit s in principle stacking heights from 5 mm to 16 mm in standard configuration 11 mm or 16 mm AUM_AHED_MFB_MB 2 User Manual AHED MB v2 1 020414a Power can be supplied to the board via this connectors 5 V 5 abs max 5 5 V e The internal 3 3 V and 1 5 V supply rails are made available to any external HW e Upto 31 differential pairs or up to 62 single ended signals Top side expansion connectors 2x FX8C 80S SV5 The pinning of both connectors is almost identical to allow them to be used for two separate extension
8. 25 HSDIO H16 75 GND GND 7 GND GND 74 BEXT L IO L64N 0 HSDIO A19 8 BEXT IO 1103 1 n25 HSDIO B22 73 BEXT L IO L64P 0 HSDIO C19 9 BEXT IO LIOP 1 n25 HSDIO B21 72 GND GND 10 GND GND 71 BEXT L IO 1653 0 HSDIO A20 11 BEXT R IO L20N 1 HSDIO C22 70 BEXT_L_IO_L65P_0 HSDIO B20 12 BEXT_R_IO_L20P_1 HSDIO C20 69 GND GND 13 GND GND 68 BEXT L IO L37N 0 GCLK F16 14 BEXT L IO L36N 0 GCLK F15 67 BEXT L IO L37P 0 GCLK E16 15 BEXT L IO L36P 0 GCLK F14 66 GND GND 16 GND GND 65 BEXT_L_IO_L49N_0 HSDIO G15 17 BEXT_L_IO_L38N_0 HSDIO G13 64 BEXT_L_IO_L49P_0 HSDIO H14 18 BEXT L IO L38P 0 HSDIO H13 63 GND GND 19 GND GND 62 BEXT L IO L66N 0 HSDIO C18 20 2 5V PWR 61 BEXT L IO L66P 0 HSDIO D17 21 2 5V PWR 60 GND GND 22 GND GND 59 BEXT L IO L62N 0 HSDIO D19 23 2 5V PWR 58 BEXT L IO L62P 0 HSDIO D18 24 2 5V PWR 57 GND GND 25 GND GND 56 BEXT L IO L51N 0 HSDIO F17 26 3 3V PWR 55 BEXT L IO L51P 0 HSDIO G16 27 3 3V PWR 54 GND GND AUM AHED MB 25 User Manual AHED MB v2 1 020414a 28 GND GND 53 RFU 29 3 3 V PWR 52 RFU 30 33V PWR 51 GND GND 31 GND GND 50 MGT TR TXIP MGT B16 32 MGT TR RXIP MGT D15 49 MGT_TR_TXIN MGT A16 33 MGT_TR_RXIN MGT C15 48 GND GND 34 GND GND 47 MGT TR TXOP MGT 14 35 D13 46 MGT TR TXON MGT 14 36 45 GND GND 37 GND GND 44 MGT TR REFCLKON MG
9. 5 Jack and middle RJ45 Jack B Up on request a reference design netlist C code attaching the PHYs to MACs and via DMA to a MicroBlaze soft core processor can be provided Net FPGA Signal Standard Description Pin E100 INT n D21 LVCMOS33 Shared tnterrupt from both100 Mbit PHYs E100 RST n Y3 LVCMOS15 with HW reset for both 100 Mbit s PHYs external pull up to active low 3 3V E100_A_RX_CRS_DV N16 LVCMOS33 E100_A_RX_ER P16 LVCMOS33 E100_A_RX_Din 0 T20 LVCMOS33 E100_A_RX_Din 1 U19 LVCMOS33 E100 A Clkout 17 LVCMOS33 50 MHz RMII clock generated by FPGA E100 A TX EN W18 LVCMOS33 E100_A_TX_Dout 0 Y17 LVCMOS33 E100_A_TX_Dout 1 U19 LVCMOS33 E100 RX CRS DV J16 LVCMOS33 E100 B RX ER J17 LVCMOS33 E100 B RX Din 0 18 LVCMOS33 E100 B RX Din l M17 LVCMOS33 E100 B Clkout U13 LVCMOS33 50 MHz RMII clock generated by FPGA E100 B TX EN U14 LVCMOS33 AUM_AHED_MFB_MB 11 User Manual AHED _ MB v2 1 020414a E100 B TX Dout 0 18 LVCMOS33 E100 B TX Dout 1 18 LVCMOS33 Tab 4 LOOMbit s Ethernet signal connection 3 3 3 Extension Modules Up to2 additional 1000 Mbit s Ethernet interfaces can be added via the top side expansion connectors see Gbit s Ethernet module AHED AHMD DRL AUM AHED MFB MB 12 User Manual AHED MB v2 1 020414a 4 Clocking The
10. IO L70N 1 n25 IO R16 50 IC BB IO 2 n25 IO 016 12 IC BB IO L70P 1 125 IO R15 49 GND GND 13 GND GND 48 IC BB R IO L57N 2 n75 IO U8 14 IC_BB_R_IO_L25N_3_n25 IO P7 47 IC BB R IO L57P 2 n75 IO T8 15 IC_BB_R_IO_L25P_3_n25 IO P6 46 GND GND 16 GND GND 45 IC_BB_R_IO_L60N_2_n75 IO Y6 17 IC_BB_R_IO_L7N_3_n25 IO T5 44 IC R IO L60P 2 175 IO W6 18 IC BB R IO L7P 3 n25 IO T6 43 GND GND 19 GND GND 42 IC BB R IO L58N 2 n75 IO W8 20 IC_BB_R_IO_L8N_3_n25 IO 41 IC BB R IO L58P 2 n75 IO V7 21 IC_BB_R_IO_L8P_3_n25 IO V5 40 GND GND 22 GND GND 39 IC BB R IO L50N 2 n75 IO V9 23 IC BB R IO L24N 3 n25 IO T4 38 IC BB R IO L50P 2 n75 IO U9 24 IC BB R IO I24P 3 n25 IO U4 37 GND GND 25 GND GND 36 IC_BB_R_IO_L10N_3 IO 1 26 IC BB R IO L26N 3 n25 IO R4 35 IC BB R IO L10P 3 IO AA2 27 IC BB R IO L26P 3 n25 IO T3 34 GND GND 28 GND GND 33 IC BB R IO L9N 3 IO P4 29 IC BB R IO I23N 3 n25 IO 7 32 19 3 5 30 IC BB IO 123 3 125 IO N6 31 GND GND Tab 9 Bottom side expansion connector left signal connection AUM AHED MFB MB 20 User Manual AHED MFB MB v2 1 020414a 10 3 2 Right side as seen through the PCB from the RJ 45 Jacks Up to 14 differential pairs gt 28 single ended IOs 11 out of 14 LVDS input and output capable 3 out of 14 only LVDS input capable due to FPGA bank 1 restrictions
11. MB v2 1 020414a 19 Legal Notices 19 1 No Warranties The material contained in this document is provided asis andis subject to change at any time without notice AHED does not warrant the accuracy and completeness of the materials in this document To the maximum extent permitted by applicable law AHED disclaims any express or implied warranty of any kind with respect to this document and any information contained herein including but not limited to warranties of merchantability noninfringement of intellectual property or fitness for any particular purpose 19 2 Limitation of Liability Some states or countries do not allow the exclusion or limitation of implied warranties or the limitation of special incidental or consequential damages so these limitations and exclusions may be limited in their application to you The following limitations apply to the extent permitted by local law In no event will AHED be liable for any damages whatsoever including without limitation damages for loss of profits business interruption or loss of data arising out of the use of or inability to use or the results of use of this document any documents linked to this document or the materials or information contained at any or all such documents AHED shall not be liable for errors or for any special incidental or consequential damages arising out of or in connection with the furnishing use or performance of this document or of any information
12. T A12 38 MGT TR REFCLKIN MGT F12 43 MGT TR REFCLKOP MGT B12 39 MGT TR REFCLKIP MGT E12 42 GND GND 40 GND GND 41 RFU Tab 12 Top side expansion connector right signal connection AUM AHED MFB MB 26 User Manual AHED MB v2 1 020414a 11 Constraint File A constraint file AHED MFB summarizing the pinning information in this document is available 12 Thermal Behavior The thermal behaviour of this board does strongly vary depending on e which FPGA is used e which components on the board are actually used the specific FPGA design The power consumption can be as low as 2W and could go up to 15 W At 5 7W power consumption the board can be used at an ambient temperature of 25 without special cooling measures At higher power levels or higher ambient temperature cooling measures like forced convection and or a heat sink on the FPGA are required This must especially be considrd with respect to a top side expansion board see e g documentation for AHED MFB AHMD 13 Environmental Conditions junction temperature of no component on the module must exceed 85 C Usually C type FPGAs commercial grade are assembled however up on request I type industrial grade can be used as well AUM AHED MB 27 User Manual AHED MB v2 1 020414a 14 Errata None 15 Important Information 16 Installatio
13. User Manual AHED MB v2 1 020414a User Manual embedded hardware and software design AHED MFB MB www ah ed com info ah ed com Revision 2 1 Date 02 04 2014 HW Revision v1 1 Fig 1 Top side view of AHED MFB MB Overview AHED MFB MP is a board designed around a Xilinx Spartan 6 LXT device in FGG484 package It features one Gbit s Ethernet PHY two 100 Mbit s Ethernet PHYs two independent 16 bit wide DDR3 SDRAMs and a 32 Mbyte Quad SPI Flash In principle all densities of the Spartan 6 LXT FPGA beginning with the LXT25 up to the LXT150 can be assembled on the board Expansion connectors are provided at bottom and top side The top side expansion connectors include up to 4 lanes of the Multi Gigabit Transceivers MGTs for serial connectivity up to 3 2 Gbit s with 3 of the dedicated differential clock inputs made available as well There is an additional FFC connector for attaching an optional Megapixel CMOS image sensor board AHED ADAPT EV76C560 CS Up on request reference designs FPGA netlist C code for the on board components can be made available by AHED AUM AHED MFB MB 1 User Manual AHED MB v2 1 020414a Fig 2 Top side view next to bottom side view of AHED MFB MB Key Features Spartan 6 LXT FPGA XC6SLX25T XC6SLXAST XC6SLX75T XC6SLX100T or XC6SLX150T Two XC6SLX25T or four XC6SLX45T to XC6SLX150T MGT lanes made available via the top side
14. ace of the CMOS imager Camera MISO B23 LVCMOS18 Part of the SPI configuration interface of the CMOS imager Camera_TRIG_A All LVCMOS33 Trigger input for image acquisition Camera_Data_A 0 R19 LVCMOS18 Camera_Data_A 1 R20 LVCMOS18 Camera_Data_A 2 T18 LVCMOS18 Camera_Data_A 3 T19 LVCMOS18 Camera_Data_A 4 U19 LVCMOS18 Those signals with LVCMOS33 go through a lefte shifter before being routed to the FFC connector to match the 1 8 V requirement of the image sensor AUM_AHED_MFB_MB 14 User Manual AHED MFB MB v2 1 020414a Camera Data A 5 V20 LVCMOS18 Camera_Data_A 6 T20 LVCMOS18 Camera_Data_A 7 U20 LVCMOS18 Camera_Data_A 8 021 LVCMOSI8 Camera Data A 9 U22 LVCMOS18 Camera_FEN_A T22 LVCMOS18 Data interface Field enable signal Camera_LEN_A U23 LVCMOS18 Data interface Line enable signal Camera_FLO_A U17 LVCMOS18 Illumination control output from the CMOS imager Tab 6 Camera connector signal connection Fig 7 Showing camera module AHED CAM ADAPT EV76C560 CS with C Mount CS Mount lens holder attached to the FPGA board AUM AHED MFB MB 15 User Manual AHED MB v2 1 020414a 7 uSD Connector There is an optional uSD socket on the bottom side of this board The connector is optional in the sense that it shares IOs with the left bottom side expansion connector and is deactivated by means of missing 0 Ohm resistors by default in
15. contained herein If your use of the materials or information contained in this document results in the need for servicing repair or correction of equipment or data you assume all costs thereof 19 3 Copyright Notice AHED explicitly retains all property and intellectual property rights on this document Without our explicit consent the document or any part of it may not be reproduced in any form or by any means including electronic storage and retrieval or translation into a foreign language AUM AHED MB 32 User Manual AHED MB v2 1 020414a 19 4 Technology Licenses Hardware firmware and software described or emntioned in this document is furnished under a license and may only be used modified and copied in accordance with the terms of such a license AUM AHED MFB MB 23
16. eptacle FX8C gt S SV FX8C gt S SV5 Header FX8C gt P SV 5 10 FX8C gt P SV1 6mm 11 mm FX8C gt P SV2 7mm 12mm FX8C gt P SV4 9mm 14mm FX8C gt P SV6 11 mm 16 mm Tab 1 Expansion connector stacking height matrix AUM AHED MFB MB User Manual AHED MFB MB v2 1 020414a 2 On board Power Rails SV e external power supply rail e 4 5 96 abs max 5 5 V exceeding this even if only for short transients destroy the SMPS ICs e Needs external bulk capacitance e g Aluminium 470 uF gt 10 V close to the board e Can either be provided via the right bottom side expansion connector or via soldering a cable to two pads on the top side Internally generated via SMPS from 5V e e Supplies FPGA bank 0 routed primarily to expansion connectors top and bank 2 and FPGA Vccaux Internally generated via SMPS from 5 e Internally generated via SMPS 5 e e Supplies FPGA bank 1 and 3 DDR3 interface Internally generated via SMPS from 5V e 5A e Supplies FPGA core and Ethernet PHY cores 1 2 V MGT e Internally generated via SMPS from 5V with passive post filter e The given current is rated current of the individual SMPS circuit The allowed combined power supplied by all SMPS together might be significantly lower due to thermal limitations AUM AHED MFB MB 8 User Manual AHED MB v2 1 020414a 3 Components 3
17. favor of the bottom side expansion option Byadding eight 0402 0 Ohm resistors can be performed by AHED up on request the uSD socket can be made active SD socket cannot be used for the XC6SLX75T device since the required IOs are not available on this device Net FPGA Pin Signal Standard Description SD CLK W6 LVCMOS33 SD DATO W8 LVCMOS33 SD_DAT1 7 LVCMOS33 SD DAT2 U8 LVCMOS33 SD DAT3 T8 LVCMOS33 SD CMD Y6 LVCMOS33 10k pull up to 3 3 V SD_SW_A v9 LVCMOS33 uSD Connector switch A 10k pull down SD_SW_B 09 533 uSD Connector switch B 10k pull up to 3 3V Tab 7 uSD socket signal connection 8 Status LEDs Each RJ45 Jack has 2 LEDs for indicating the status of the respective Ethernet interface The specific behaviour depends on the configuration of the specific PHY further LED outputs of the Marvell 88E1111 Gigabit s Ethernet PHY are connected to red SMD LEDs on the board There are 3 LEDs indicating the status of the FPGA e Illuminates red while the FPGA is not configured e DONE Illuminates green when the FPGA is configured AWAKE AUM_AHED_MFB_MB 16 User Manual AHED MB v2 1 020414a 9 FPGA Bank Overview Bank 0 top bank e Vccio 3 3 V e True LVDS output capable LVCMOS 3 3 output capable e right bank e Vccio 1 5 V e LVCMOS output only at 1 5 V e LVCMOS input
18. hermal Behavi t E 27 Environmental 27 NEED 28 15 Important 28 Installati n 28 12 Default C onfigurati nS eee oiea 28 ES Enas 29 Accessories must be ordered separately gre ttn orit EN Rn bi px VE tip eti 29 Jesu a seca pcs ries DINER MR MM PE M 32 AUM AHED MFB 5 User Manual AHED MB v2 1 020414a 1 Dimensions Mechanics he actual board has a size of 100 x 60 mm RJ45 Jacks protrude 3 mm beyond the actual PCB edge With stacking heights of up to 16 mm the Hirose FX8 connectors allow for placing connectors like RJ45 D Sub BNC low profile DVI below this board and allow placing a top side expansion board directly above this PCB The board has 4 mounting holes with a nominal diameter of 3 2 mm Apart from the expansion connectors and RJ45 Jacks the highest component on the top side is 6 mm and 3 mm on the bottom side nominal board thickness of MFB is 1 6 mm Fig 5 Top side drawing of AHED MFB MB AUM AHED MFB MB 6 User Manual AHED MFB MB v2 1 020414a Fig 6 Bottom side drawing of AHED MFB MB MFB MB vi 1 35 0mm Rec
19. main clock source of this board is a low jitter PCI express clock generator providing 125 MHz differentially to the FPGA This clock signal is the basis for designs using the DDR3 SDRAM or the MGTs and be used to derive clocks for internal processing by means of the PLLs within the Spartan 6 FPGA as well There is a separate low jitter 25 MHz clock oscillator on board that provides a 25 MHz reference clock to the Gigabit Ethernet PHY the FPGA and the Camera FFC header A further low power MEMS 100 oscillator is present on the board as well Net FPGA Signal Standard Description Pin clk125 p T12 LVDS 33 clk125 n 012 LVDS 33 clk100 AB12 LVCMOS33 CLK 25FPGA AA12 LVCMOS33 Tab 5 FPGA clocking signal connection 5 JTAG Due to space constraints the boards itself does only have a proprietary 6 pin JTAG header that connects to the JTAG interface of the Spartan 6 FPGA However a small adapter PCB is provided with this board as can be seen e g on Fig 7 that makes the JTAG interface mechanically compatible with the standard 14 pin Xilinx download cable A soon as top side extension modules are installed the JTAG header might not be directly accessible anymore Up on request AHED can provide simple adapter PCBs that keep the JTAG interface accessible with top side extension modules installed The 88E1111 is not included in the JTAG chain on this board By changing two resistors on the board
20. n 17 Default Configurations AHED_MFB_MB_STD_LX45 2C e Spartan 6 XC6SLXAST speed grade 2 commercial grade 2x 128 Myte DDR3 SDRAM e 32 Mbyte SPI NOR flash e On board Gigabit Ethernet Interface e 45 Jacks assembled Bottom side expansion connectors 2 FX8C 60P SV6 Top side expansion connectors 2x FX8C 80S SV5 FFC camera connector assembled e uSD socket assembled but not activated AHED_MFB_MB_STD_LX100 3C e Spartan 6 65 100 speed grade 3 commercial grade 2x 128 DDR3 SDRAM e 32 Mbyte SPI NOR flash e On board Gigabit Ethernet Interface e 45 Jacks assembled Bottom side expansion connectors 2 FX8C 60P SV6 Top side expansion connectors 2x FX8C 80S SV5 e FFC camera connector assembled uSD socket assembled but not activated AUM AHED MB 28 User Manual AHED _ MB v2 1 020414a 18 Options up on request minimum order quantities do apply Different FPGA industrial grade speed grade Larger DDR3 SDRAM Without on board Gigabit Ethernet interface Noor other height for expansion connectors No FFC connector NouSD connector Accessories must be ordered separately Examples of systems build around the FPGA board MFB MB Fig 6 Front side view of FPGA board AHED MFB installed on baseboard AHED MFB LED SIO32X A with top side expansion carrier board AHED MFB CB AHMD and attached DVI RX module
21. ode PHY MII address 0b10000 Magnetics and RJ45 Jack on board gt ready to use accessible via left RJ45 Jack Upon request a reference design netlist C code attaching the PHY to a MAC and via DMA to a MicroBlaze soft core processor can be provided Net FPGA Pin Signal Standard Description ETHER Reset out M7 LVCMOSIS with HW reset for Gigabit Ethernet external pull up to 3 3V PHY active low MDC 19 LVCMOS33 MII interface shared for all 3 on board PHYs MDIO D3 LVCMOS33 MII interface shared for all 3 on board PHYs EtherA_INTin K7 LVCMOS33 Interrupt from Gigabit Ethernet PHY EtherA_Data_out 0 7 LVCMOS33 EtherA Data out 1 U6 LVCMOS33 EtherA Data out 2 W9 LVCMOS33 EtherA Data out 3 Y8 LVCMOS33 EtherA_Data_EN Y12 LVCMOS33 EtherA_CLK_out W12 LVCMOS33 RGMII TX clock EtherA Data in 0 D2 LVCMOS33 EtherA Data in 1 DI LVCMOS33 EtherA Data in 2 F3 LVCMOS33 EtherA Data in 3 4 LVCMOS33 EtherA DV LVCMOS33 EtherA CLK in Y13 LVCMOS33 RGMII RX clock Tab 3 Gigabit s Ethernet signal connection AUM AHED MB 10 User Manual AHED MB v2 1 020414a 3 3 2 100 Mbit s Two interfaces A and B Implemented via a SMSC Ethernet PHY chip LAN8720A Attached in RMII mode PHY address 0600000 0600001 Magnetics and RJ45 Jacks on board ready to use accessible via right RJ4
22. pable of up to 3 125 Gbit s In principle stacking heights from 5 mm to 16 mm in standard configuration FX8C 60P SV6 11 mm or 16 mm Power can be supplied to the board via this connectors 5 V 5 abs max 5 5 The internal 3 3 V and 1 5 V supply rails are made available to any external HW 0 4 A max per contact Care should be taken when the XC6SLX25T or XC6SLX75T FPGAs are supposed to be used because numerous IOs are not available on these devices see Explanation of Signal Names AUM AHED MB 19 User Manual AHED MFB MB v2 1 020414a 10 3 1 Left side as seen through the PCB from the RJ 45 Jacks Up to 17 differential pairs gt 34 single ended IOs 7 out of 14 LVDS input and output capable 7 out of 14 only LVDS input capable due to FPGA bank 1 3 restrictions Net Type FPGA Net Type FPGA E Pin E Pin 5 5 1 GND GND 60 1 5V PWR 2 3 3 V PWR 59 1 5V PWR 3 3 3 V PWR 58 GND GND 4 GND GND 57 IC BB R IO I22N 2 n25 n75 IO 5 3 3 PWR 56 IC BB IO 122 2 n25 175 IO R11 6 3 3 V PWR 55 GND GND 7 GND GND 54 IC_BB_R_IO_L23N_2_n25_n75 IO U15 8 IC BB R IO L72N 1 n25 IO T17 53 IC_BB_R_IO_L23P_2_n25_n75 IO 15 9 IC BB R IO L72P 1 125 IO R17 52 GND GND 10 GND GND 51 IC BB R IO IAN 2 n25 IO V15 11 IC BB R
23. pment Industrial Control Data Recorder Grabber High Speed ADCs Camera DVI gt DDR3 Ethernet Data Player DDR3 Ethernet gt High Speed DACs DVI Fig 3 Sample Application Video Processing DVI RX and DVI TX module attached Fig 4 Sample Application Camera Interface AUM AHED MFB MB 4 User Manual AHED MB v2 1 020414a Table of Contents uiis m 1 2 PA Po e 4 1 Dimensions Mechatics ues ies intera Suas 6 2 Mineo meh P wer CENE T m T 8 2 ME OVID OMS IIIS 9 SU PEE AECB ENSE 9 32 Flash Memory 9 SENSUS STET mr 10 WS co rc rcr 13 25 C e C I HP 13 ME G viec 14 bii MINER UNO 16 Pe re M 16 9 FPGA Bank Overview ERR Ru P pd SE uS E e p ERU 17 10 Exp sion ORC WOES ibis ute E nente Pado Ee 18 18 10 2 Explanation of Net 18 10 3 Bottom Side Expansion Connectors 19 10 4 Top Side Expansion COnnectors esesessesereeesesrrsrierersrsriserestesrrssresrestessresrensessresees 22 Constraint REC aE a E AAE EEE EE E Ie 27 12 T
24. s or jointly Hirose FX8 Series up to 3 125 Gbit s in principle stacking heights from 5 mm to 16 mm in standard configuration 10 11 12 14 or 16 mm The internal 2 5 V and 3 3 V supply rails are made available on each of the connectors to the external circuit e Upto two MGT lanes with reference clock input are made available on each of the two connectors e Up to 30 differential pairs or up to 60 single ended general purpose signals Clocking e The board features a low jitter 125 MHz PCI express clock generator a 25 MHz low jitter oscillator and a low power 100 MHz MEMS oscillator all accessible by the FPGA Dedicated camera connector e The board includes a 34 pin FFC connector for attaching AHED camera modules optional uSD socket Required Power Supply e 5V 1 5 abs max 5 5 V e Power consumption 2 15 W depending on the specific configuration FPGA design Optional DVI input up to 1920 x1200 60 Hz via top side extension module AHMD DRL DVI Optional DVI output up to 1920 x1200 60 Hz via top side extension module AUM AHED MFB MB 3 User Manual AHED v2 1 020414a AHED AHMD DRL DVI TX Optionally up to 2 additional 10 100 1000 Mbit s tri speed Gigabit Ethernet interfaces via top side extension modules AHMD DRL MIC Applications Video Image Processing Camera Interface Embedded System Design System on Chip SoC develo
25. this frequency could be changed to 25 MHz 100 MHz or 200 MHz AUM_AHED_MFB_MB 13 User Manual AHED MB v2 1 020414a 6 Camera Interface This board provides a dedicated interface for attaching camera modules by AHED This interface can be found at the right side of the board as seen from the RJ45 Jacks in form of a 34 pin FFC connector Most of the pins of this interface are shared with the right bottom side expansion connector So these are no longer available for general purpose use as soon as the camera interface is used means of the cable the actual camera module CMOS imager be separated from the FPGA board by dozens of centimeters as can be seen in Fig 7 Up on request a reference design netlist C code attaching AHED s camera module ADAPT EV76C560 CS featuring an E2V 1 3 Megasample image sensor via DMA to a MicroBlaze soft core processor working on the DDR3 memory can be provided Net FPGA Pin Signal Standard Description Camera Data clk A AB13 LVCMOS33 Camera CSN A C11 LVCMOS33 Chip select for the SPI configuration interface of the CMOS imager active low Camera_reset_n AF24 LVCMOS15 with HW reset to the camera chip active external pull up low to 1 8 V Camera MOSI B8 LVCMOS33 Part of the SPI configuration interface of the CMOS imager Camera SCK 8 LVCMOS33 Part of the SPI configuration interf
26. up to 3 3 V e bottom bank e Vecio 3 3 V e True LVDS output capable LVCMOS 3 3 output capable Bank 3 e left bank e Vccio 1 5 V e LVCMOS output only at 1 5 V e LVCMOS input up to 3 3 V AUM AHED MB 17 User Manual AHED MB v2 1 020414a 10 Expansion Connectors 10 1 Pin Types Type Description GND Ground pin PWR Power supply pin RFU Reserved for future use No assumption must be made on the connection of this pin IO General purpose input output pin HSDIO High Speed Differential IO Routed as differential pair closely length matched can be used as general purpose IO as well GCLK Global Clock input can be used as IO or possibly HSDIO as well Tab 8 Extension connector pin types 10 2 Explanation of Net Names E g IC BB R IO L72N 1 n25 BB R JO L7 IN 1 n25 Type of expansion connector InterConnect to Base Board Pin is Input Output capable L72 signal label taken from Xilinx documentation N gt negative pin of differential pair opposed to gt positive pin of differential pair Signal belonging to FPGA Bank 1 not available on LX25T FPGA device also possible _n75 and n25 n75 AUM AHED MFB MB 18 User Manual AHED MB v2 1 020414a 10 3 Bottom Side Expansion Connectors Two Hirose FX8 Series connectors connector ca
Download Pdf Manuals
Related Search