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NXP Semiconductors TDA8932B User's Manual

1. VPowERUP V Vi 100 mV RMS value fi 1 kHz Vengace gt 3 V Fig 24 Output voltage as a function of voltage on pin POWERUP 32 001aaf887 32 001aa 888 Po Po W channel W channel 24 HG 24 2 2 16 16 1 1 8 8 0 0 0 120 240 360 480 600 0 120 240 360 480 600 t s t s a RL22x4Q f 2 1 kHz 2 layer S032 application b RL 2x8Q f 1 kHz 2 layer S032 application board 55 mm x 45 mm without heat sink board 55 mm x 45 mm without heat sink 1 Vp 22V 1 Vp 30V 2 Vp 26V 2 Vp 34V 3 Vp 29V Fig 23 Output power per channel as a function of time 4 001aaf890 4 001aaf891 Vo Vo V V 3 operating B operating 2 2 1 1 r sleep i mute 0 0 5 1 1 5 2 2 5 3 0 0 5 1 1 5 2 2 5 3 Fig 25 VENGAGE V Vi 100 mV RMS value fi 1 kHz Veowerup gt 2 V Output voltage as a function of voltage on pin ENGAGE TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 32 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 14 10 BTL curves measured in reference design fi Hz a Vp 12V RL 4Q 1 Po 210W 2 Po 1W 102 001aad782 102 001aad783 THD N THD N 10 10 1 1 10 1 10 1 1
2. 001aad768 40 2a 40 001aad769 Po Po RL 42 W W RL 4Q 30 30 62 60 20 bn 20 80 10 10 0 0 10 20 30 40 10 20 30 40 Vp V Vp V a THD N 0 5 b THD N 10 96 Fig 8 SE output power as a function of supply voltage 001aad770 001aad771 80 80 Po Po RL 8Q W W RL 280 60 60 62 60 40 40 49 4Q 20 20 0 0 10 20 30 40 10 20 30 40 Vp V Vp V a THD N 0 5 b THD N 10 96 Fig 9 BTL output power as a function of supply voltage TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 23 of 48 NXP Semiconductors TDA8932 B 14 2 14 3 14 4 TDA8932B_3 Class D audio amplifier Output current limiting The peak output current lo max is internally limited above a level of 4 A minimum During normal operation the output current should not exceed this threshold level of 4 A otherwise the output signal is distorted The peak output current in SE or BTL configurations can be estimated using Equation 5 and Equation 6 SE configuration 05xVp m ae Ri Rpsont Rs t Rese BTL configuration Vp I lt Omax R 2X Rpson Ry lt 4A 6 Where Vp supply voltage Vppp Vssp1 V or Vopp2 Vsspe V R load impedance Q Rpson on resistance power switch Q Rs series resistance output inductor Q Resp eq
3. 1 Vp 12V RL 42 2 Vp 22V RL 82 Fig 33 Output power efficiency as a function of output power 1 Vp 12V 1 Vp 22V 2 Vp 13 5V 2 Vp 26V 3 Vp 15V 3 Vp 29V Fig 32 Output power as a function of time 100 001aae119 3 0 001aae120 Tipo 1 90 1 p W 80 e W 2 0 60 40 2 1 0 20 1 0 0 0 10 20 30 10 2 10 1 1 10 102 Po W Po W P f 1 kHz power dissipation in junction only p o Ne Wes NO rcm 1 Vp 12V RL 40 Vp 22 V R 82 Power dissipation as a function of output power TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 35 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier 6 001aaf904 7l P if W 7 7 y J L 1 4 7 7 n 72 7 7 A A ra 2 0 10 14 18 22 26 30 34 Vp V f 1 kHz power dissipation in junction only short time Po at THD N 10 96 dashed line will require heat sink for continuous time output power 1 RL 4Q 2 RL 8Q Fig 35 Power dissipation as a function of supply voltage TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 36 of 48 TDA8932B Class D audio amplifier NXP Semiconductor
4. Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION SOT549 1 MO 153 E pate Fig 41 Package outline SOT549 1 HTSSOP32 TDA8932B 3 Product data sheet Rev 03 21 June 2007 NXP B V 21 June 2007 All rights reserved 42 of 48 NXP Semiconductors TDA8932 B 17 Soldering 17 1 17 2 Class D audio amplifier This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from
5. and fi 1 kHz Vi cm 1 V RMS Po 15 W Vp 12 Vand R 240 Po 30 W Vp 22 Vand R 8Q continuous time output power RL 40 Vp 12V THD N 0 5 fi 1 kHz THD N 0 5 fi 100 Hz THD N 10 fi 1 kHz THD N 10 fi 100 Hz R 8 Q Vp 22 V THD N 0 5 fi 1 kHz THD N 0 5 fi 100 Hz THD N 10 fi 1 kHz THD N 10 fi 100 Hz short time output power RL 40 Vp 15V THD N 0 5 THD N 10 R 8 Q Vp 29 V THD N 0 5 THD N 10 4 4 5 Min 88 90 23 1 28 9 18 5 23 9 36 0 49 5 Typ 100 70 100 75 90 92 13 2 13 2 17 2 17 2 25 7 25 7 32 1 32 1 20 6 26 6 40 0 55 0 Max 150 100 Unit uV uV uV dB 2222 1 2 3 4 5 Rs is the series resistance of inductor and capacitor of low pass LC filter in the application THD N is measured in a bandwidth of 20 Hz to 20 kHz AES17 brick wall Maximum Vrippie 2 V p p Rs 0 Q B 20 Hz to 20 kHz AES17 brick wall Output power is measured indirectly based on Rpso measurement Two layer application board 55 mm x 45 mm 35 um copper FR4 base material in free air with natural convection TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 21 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier 14 Application information 14 1 Output power estimation
6. 0 5 3 RL 22x80 THD N 10 4 RL 2x8 Q THD N 0 5 Fig 19 Output power per channel as a function of supply voltage 001aaf889 6 0 10 14 18 22 26 30 34 38 Vp V f 1 kHz power dissipation in junction only short time Po at THD N 10 96 dashed line will require heat sink for continuous time output power 1 R 22x4Q 2 RL 2x82 Fig 20 Power dissipation as a function of supply 2xP ENO Sep En o 1 Vp 2 22V R 2x4Q 2 Vp 30V R 2x8Q Fig 21 Output power efficiency as a function of output power per channel voltage 100 001aad780 3 0 001aad781 2 po 96 1 P 80 W 2 0 60 2 40 1 1 0 20 0 0 0 5 10 15 20 10 2 1071 1 10 102 Po W channel Po W channel f 1 kHz power dissipation in junction only 1 Vp 22V RL 2x4Q 2 Vp 30V RL 2x8Q Fig 22 Power dissipation as a function of output power per channel two channels driven TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 31 of 48 NXP Semiconductors TDA8932B Class D audio amplifier
7. 001aad798 BOOT2 BOOT re d OUT1 OUT2 001aad799 OUT2 OUTI e VssP1 VSSP2 001aag027 STAB2 STAB1 VDDA AL 24 25 ru VssPt VSSP2 001aag028 OSCIO DREF AL 31 Rp Vssp 001aag029 TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 15 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 10 Limiting values Table 8 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vp supply voltage asymmetrical supply E 0 3 40 V Vx voltage on pin x IN1P IN1TN IN2P IN2N B 5 5 V OSCREF OSCIO TEST BI VgspiHw 0 3 5 V POWERUP ENGAGE Bl Vcogpp 0 3 6 V DIAG all other pins BI Vas 0 3 Vpp 0 3 V lorm repetitive peak output maximum output 6 4 A current current limiting Tj junction temperature 150 C T stg storage temperature 55 150 C Tamb ambient temperature 40 85 C P power dissipation 5 WwW Vesd electrostatic discharge HBM Ul 2000 2000 V voltage MM 8 200 4200 vV 1 Vp Vppe1 Vssp1 Vppr2 Vsspe 2 Measured with respect to pin INREF Vx lt Vpp 0 3 V 3 Measured with respect to pin Vssp Hw Vx lt Vpp 0 3 V 4 Measured with respect to pin CGND Vx lt Vpp 0 3 V 5 Vss Vsse1 Vssp2 Voo Vopp1 Vppe 6 Current limiting concept 7 Human Body Model HBM Rs 1500 Q C 100 pF For pins 2 3 11 14 and 15 V
8. 60 Hz f 3aB 40 Hz f 3ap 20 Hz 680 1000 2200 470 680 1500 8 330 470 1000 14 5 Gain reduction The gain of the TDA8932B is internally fixed at 30 dB for SE or 36 dB for BTL The gain can be reduced by a resistive voltage divider at the input see Figure 10 R1 470 nF A C 1 audio in D R2 R3 t 1 IH 470 nF 17 001aad762 Fig 10 Input configuration for reducing gain When applying a resistive divider the total closed loop gain Gy can be calculated by Equation 8 and Equation 9 TNNT E CE 8 v tot v cl g Rgo RI R2 Where Gw tot total closed loop voltage gain dB Gycl closed loop voltage gain fixed at 30 dB for SE dB Reg equivalent resistance R3 and Zi Q R1 series resistor Q R2 series resistor Q TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 25 of 48 NXP Semiconductors TDA8932 B 14 6 14 7 TDA8932B_3 Class D audio amplifier R3 XZ 9 EO R3 Z Where Reg equivalent resistance Q R3 parallel resistor Q Zi internal input impedance Q Example Substituting R1 R2 4 7 KQ Zi 100 kQ and R3 22 kQ in Equation 8 and Equation 9 results in a gain of Gyr 26 3 dB Device synchronization If two or more TDA8932B devices are used in one application it is recommended that all devices are synchronized running at the same switching frequency to
9. NXP Semiconductors TDA8932 B 14 8 TDA8932B_3 Class D audio amplifier The HTSSOP32 package has an exposed die pad that reduces significantly the overall Rih a Therefore it is required to solder the exposed die pad at Vssp level to a copper plane for cooling The HTSSOP package will have a low thermal resistance when used on a multi layer PCB with sufficient space for one or two thermal planes Increasing the area of the thermal plane the number of planes or the copper thickness can reduce further the thermal resistance Ri of both packages Typical thermal resistance Rinjj a of the SO32 package soldered at a small 2 layer application board 55 mm x 45 mm 35 um copper FR4 base material is 44 K W Typical thermal resistance Rinj a of the HTSSOP32 package soldered at a small 2 layer application board 55 mm x 40 mm 35 um copper FR4 base material is 48 K W Equation 10 shows the relation between the maximum allowable power dissipation P and the thermal resistance from junction to ambient T nag T amb 1 0 Raj a P Where Rth a thermal resistance from junction to ambient Titmax maximum junction temperature Tamb ambient temperature P power dissipation which is determined by the efficiency of the TDA8932B The power dissipation is shown in Figure 22 SE and Figure 34 BTL The thermal foldback will limit the maximum junction temperature to 140 C Pumping effects When the amplifier is use
10. Soldeting 2 rrr n Introduction to soldering founded by 29 33 37 40 40 41 43 43 Class D audio amplifier 17 2 Wave and reflow soldering 43 17 3 Wave soldering ee eee eee 43 17 4 Reflow soldering 00e0ee eee 44 18 Abbreviations essere 45 19 Revision history eee eee 46 20 Legal information 47 20 1 Data sheet statuS 00 47 20 2 Definitions 2 00000 cee eee 47 20 3 Disclaimers 0000000 eee eee 47 20 4 Trademarks 0000 0c eee eee 47 21 Contact information 47 22 Contents ree ro eR Rx 48 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 21 June 2007 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 21 June 2007 Document identifier TDA8932B 3
11. Vssa 001aad785 4 DIAG Vssa CGND 001aaf607 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 12 of 48 NXP Semiconductors TDA8932B Table 7 Internal circuitry Continued Class D audio amplifier Pin 5 TDA8932B_3 Symbol Equivalent circuit ENGAGE VDDA 28V A lref 50 pA 2kQ 20 5 3 t 3 gt A 100 ka 20 Vssa CGND 001aaf608 POWERUP VDDA 6 gt Vssa CGND 001aad788 CGND VDDA 7 Vssa 001aad789 Vppa 8 Vssa VssD 001aad790 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 200 7 13 of 48 NXP Semiconductors TDA8932B Class D audio amplifier Table 7 Internal circuitry Continued Pin Symbol Equivalent circuit 9 Vssa A VDDA Lf Vssp 001aad791 10 OSCREF VDDA Q lret 10 Vssa 001aad792 11 HVPREF VDDA 11 i Vssa O01aaf604 13 TEST VDDA VssA 001aad795 18 DREF VDD L 18 Vssp 001aag025 TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 14 of 48 NXP Semiconductors TDA8932B Table 7 Class D audio amplifier Internal circuitry Continued Pin 19 30 20 23 26 29 21 28 22 27 24 25 31 Symbol Equivalent circuit HVP2 HVP1 VODA VssA 001aag026 Vppp2 Vssp2 VssP1 VppP1 bacon
12. a standing wave of liquid solder The wave soldering process is suitable for the following Through hole components Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are Board specifications including the board finish solder masks and vias Package footprints including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead free soldering versus PbSn soldering 17 3 Wave soldering TDA8932B 3 Key characteristics in wave soldering are Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wave Solder bath specifications including temperature and impurities NXP B V 21 June 2007 All rights reserved
13. avoid beat tones Synchronization can be realized by connecting all OSCIO pins together and configure one of the TDA8932B devices as master while the other TDA8932B devices are configured as slaves see Figure 11 A device is configured as master when connecting a resistor between pins OSCREF and Vssp Hw Setting the carrier frequency Pin OSCIO of the master is then configured as an oscillator output for synchronization The OSCREF pins of the slave devices should be shorted to Vssp Hw configuring pin OSCIO as an input master slave IC1 IC2 TDA8932B TDA8932B OSCREF Vssp uw OSCIO OSCIO Vssp uw OSCREF Cosc 100 nF 001aaf600 Fig 11 Master slave concept in two chip application Thermal behavior printed circuit board considerations The TDA8932B is available in two different thermally enhanced packages TDA8932BT in a S032 SOT287 1 package for reflow and wave solder process TDA8932BTW in an HTSSOP32 SOT549 1 package for reflow solder process only The SO32 package has special thermal corner leads increasing the power capability reducing the overall Ria To benefit from the corner leads pins Vssp Hw pins 1 16 17 and 32 should be attached to a copper plane The SO package is very suitable for applications with limited space for a thermal plane in a single layer PCB design NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 26 of 48
14. description 0 2000 Functional description General 22elb RilRg ele bay ewes Mode selection and interfacing Pulse width modulation frequency Protection 2 atus rk Aedes x REUS Thermal Foldback TF OverTemperature Protection OTP OverCurrent Protection OCP Window Protection WP Supply voltage protection Diagnostic input and output Differential inputs 0 Output voltage buffers Internal circuitry 0 0 00 cece ee eee Limiting values esses Thermal characteristics Static characteristics Dynamic characteristics Application information Output power estimation Output current limiting Speaker configuration and impedance Single ended capacitor Gain reduction 00000 eee Device synchronization Thermal behavior printed circuit board considerations llle esses Pumping effects 20000 SE curves measured in reference design BTL curves measured in reference design Typical application schematics simplified Test information se Quality information 0005 Package outline Llusu
15. reserved Product data sheet Rev 03 21 June 2007 6 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier Vp POWERUP DREF HVPREF HVP1 HVP2 ENGAGE audio OUT1 OUT2 PWM DIAG OSCIO Fig 4 Start up sequence 2 0 V typical 1 2 V typical md gt e operating mute operating fault operating sleep 001aaf885 8 3 TDA8932B 3 Pulse width modulation frequency The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz Using a 2nd order low pass filter in the application results in an analog audio signal across the loudspeaker The PWM switching frequency can be set by an external resistor Rosc connected between pins OSCREF and Vssp uw The carrier frequency can be set between 300 kHz and 500 kHz Using an external resistor of 39 kO the carrier frequency is set to an optimized value of 320 kHz see Figure 5 If two or more TDA8932B devices are used in the same audio application it is recommended to synchronize the switching frequency of all devices This can be realized by connecting all pins OSCIO together and configure one of the TDA8932B in the application as clock master while the other TDA8932B devices are configured in slave mode Pin OSCIO is a 3 state input or output buffer Pin OSCIO is configured in master mode as oscillator output and in slave mode as osci
16. 0 2 10 2 10 3 10 3 10 2 10 1 1 10 102 10 2 10 1 1 10 102 Po W Po W a Vp 12V R 4Q0 b Vp 22V R 280 1 fi 2 6kHz 2 fi 1 kHz 3 fi 100 Hz Fig 26 Total harmonic distortion plus noise as a function of output power 102 001aae114 102 001aae115 THD N THD N 10 10 1 1 1071 107 10 2 10 2 1 2 1073 1073 10 10 103 104 105 10 102 103 104 105 Fig 27 Total harmonic distortion plus noise as a function of frequency fi Hz b Vp 22V R 82 TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 33 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 40 001aae116 0 001aae117 SVRR Gy dB dB E dB QW 20 30 40 60 20 1 80 2 10 100 10 10 103 104 105 10 102 103 104 105 fi Hz fi Hz Vi 100 mV RMS Rj 0 Q Vripple 500 mV RMS referenced to ground 1 Vp 12V R 42 Ri 0 Q shorted input 2 Vp 22V R 80 1 Bee VL ee 2 Vp 12V RL 42 Fig 28 Gain as a function of frequency Fi
17. D The reaction of the device to the different fault conditions differs per protection TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 8 of 48 NXP Semiconductors TDA8932 B 8 4 1 8 4 2 8 4 3 8 4 4 TDA8932B_3 Class D audio amplifier Thermal Foldback TF If the junction temperature of the TDA8932B exceeds the threshold level T gt 140 C the gain of the amplifier is decreased gradually to a level where the combination of dissipation P and the thermal resistance from junction to ambient Rthj a results in a junction temperature around the threshold level This means that the device will not completely switch off but remains operational at lower output power levels Especially with music output signals this feature enables high peak output power while still operating without any external heat sink other than the printed circuit board area If the junction temperature still increases due to external causes the OTP shuts down the amplifier completely OverTemperature Protection OTP If the junction temperature T gt 155 C then the power stage will shut down immediately OverCurrent Protection OCP When the loudspeaker terminals are short circuited or if one of the demodulated outputs of the amplifier is short circuited to one of the supply lines this will be detected by the OCP If the output current exceeds the maximum output current lo o
18. I 10 0 B CSN STAB2 T 470 pF mi zl d V Cstab SSP2 100 nF Clc OUT2 Llc l Cbo BOOT2 15nF Ren VppP2 VP 10s Cvddp wi CSN niis zn 100nF T 470 pF TH DREF V Cdref Chvp SSD HW I 100 nF 100 nF 17 001aaf602 Fig 37 Typical simplified application diagram for 1 x BTL asymmetrical supply TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 38 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier gt VDD Rvdda VDD gt VDDA ne 1 Cvdda a Gidip 220 1 100 nF 25 V GND Cvssa Cvssp rh 100 nF Se 220 WF Rvssa T 25 V VSS gt VSSA 100 gt VSS VSSD HW VSSA VSSA Cin IN1P Il 470 nF Cin IN1N E I 470 nF DIAG VDD Cvddp MUTE control ite ENGAGE T 100 nF Cen 717 T 470 nF POWERUP DOE SLEEP control oa 10 o m Vi S Cosc VDDA PDA U1 2Csn Ig V 7 470 pF T 100 nF VSSA SSA TDAU 71 4 R Cvssp VSSA OSC OSCREF ll E 17 39 kQ 100 nF HVPREF E INREF Cinref nen toonr TEST 100 l 1 Cin TH IN2N Cen L II 470 pF Tp Cle 470 nF Cin IN2P E I p rh 470nF Vssp Hw VSSA VSSA 001aaf603 Fig 38 Typical simplified application diagram for 2 x SE symmetrical supply TDA8932B 3 NXP B V 21 June 2007 All rig
19. P Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail 20 3 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitabl
20. Package outline S032 plastic small outline package 32 leads body width 7 5 mm SOT287 1 detail X 0 5 LL gg apo scale DIMENSIONS inch dimensions are derived from the original mm dimensions UNIT Ai A2 Ag bp c DUO EM e He 0 3 20 7 7 6 0 1 0 29 20 3 7 4 net 0 81 0 30 inches 0 01 0 80 0 29 0 05 Note 1 Plastic or metal protrusions of 0 15 mm 0 006 inch maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA PROJECTION SOT287 1 MO 119 Ey ee H ISSUE DATE Fig 40 Package outline SOT287 1 8032 TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 41 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier HTSSOP32 plastic thermal enhanced thin shrink small outline package 32 leads body width 6 1 mm lead pitch 0 65 mm exposed die pad SOT549 1 exposed die pad side pin 1 index detail X DIMENSIONS mm are the original dimensions UNIT Ay A2 Ag bp 0 25
21. Product data sheet Rev 03 21 June 2007 43 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier 17 4 Reflow soldering Key characteristics in reflow soldering are Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures see Figure 42 than a PbSn process thus reducing the process window Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17 Table 16 SnPb eutectic process from J STD 020C Package thickness mm Package reflow temperature C Volume mm lt 350 E 350 2 5 235 220 225 220 220 Table 17 Lead free process from J STD 020C Package thickness mm Package reflow temperature C Volume mm 350 350 to 2000 gt 2000 lt 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity p
22. S032 plastic small outline package 32 leads SOT287 1 body width 7 5 mm TDA8932BTW HTSSOP32 plastic thermal enhanced thin shrink small outline SOT549 1 package 32 leads body width 6 1 mm lead pitch 0 65 mm exposed die pad TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 2 of 48 NXP Semiconductors TDA8932B 6 Block diagram Class D audio amplifier IN1P IN1N OSCREF OSCIO gt INREF IN2P IN2N DIAG lt 10 31 OSCILLATOR Vssp PWM MODULATOR PWM MODULATOR PROTECTIONS OVP OCP OTP MANAGER CGND POWERUP VDDA ENGAGE TEST Fig 1 Block diagram TDA8932B 1 16 17 32 VSSA VssD HW gt BOOT1 El VoDP1 El OUT1 c V c SSP1 BOOT2 20 V Ld 22 _ oUT2 e 23 V e SSP2 VDDA r STABILIZER 11 V STAB1 VssP1 VDDA STABILIZER 11 V STAB2 VssP2 gt REGULATOR 5 V DREF VssD HVPREF HVP1 HVP2 HALF SUPPLY VOLTAGE 001aaf597 TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 3 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 7 Pinning information 7 1 Pinning VSSD HW IN1P IN1N DIAG ENGAGE POWERUP CGND VDDA V
23. TDA8932B Class D audio amplifier Rev 03 21 June 2007 Product data sheet 1 General description The TDA8932B is a high efficiency class D amplifier with low power dissipation The continuous time output power is 2 x 15 W in stereo half bridge application R 4 Q or 1 x 30 W in mono full bridge application RL 8 Q Due to the low power dissipation the device can be used without any external heat sink when playing music Due to the implementation of thermal foldback even for high supply voltages and or lower load impedances the device remains operating with considerable music output power without the need for an external heat sink The device has two full differential inputs driving two independent outputs It can be used as mono full bridge configuration BTL or as stereo half bridge configuration SE 2 Features Bi Operating voltage from 10 V to 36 V asymmetrical or 5 V to 18 V symmetrical B Mono bridged tied load full bridge or stereo single ended half bridge application B Application without heatsink using thermally enhanced small outline package B6 High efficiency and low power dissipation B Thermally protected and thermal foldback B Current limiting to avoid audio holes Bi Full short circuit proof across load and to supply lines using advanced current protection B Switchable internal or external oscillator master slave setting E No pop noise B Full differential inputs 3 Applications Flat pan
24. The output power P at THD N 0 5 just before clipping for the SE and BTL configuration can be estimated using Equation 2 and Equation 3 SE configuration ere EL X tyeminy X fose X 2 Rr Rpgo Rs t Resp P 9 54 B BEEN TT SN 2 BTL configuration R i v 2 X t ay xX x E EREET ems U 7 twemin X fosc f P o 0 5 2O e 3 Where Vp supply voltage Vppp1 Vssp1 V or Vppp2 Vssp2 V R load impedance Q Rpson on resistance power switch Q Rs series resistance output inductor Q Resp equivalent series resistance SE capacitor Q tw min Minimum pulse width s 80 ns typical fosc oscillator frequency Hz 320 kHz typical with Rosc 39 kQ The output power P at THD N 10 can be estimated by Poco 1 25 X Po 95 4 Figure 8 and Figure 9 show the estimated output power at THD N 0 5 and THD N 10 96 as a function of the supply voltage for SE and BTL configurations at different load impedances The output power is calculated with Rpson 0 15 Q at Tj 25 C Rs 0 05 Q Resp 0 05 Q and lO ocp 4 A minimum TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 22 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier
25. cp gt 4 A this current will be limited by the amplifier to 4 A while the amplifier outputs remain switching the amplifier is NOT shutdown completely This is called current limiting The amplifier can distinguish between an impedance drop of the loudspeaker and a low ohmic short circuit across the load or to one of the supply lines This impedance threshold depends on the supply voltage used e Incase of a short circuit across the load the audio amplifier is switched off completely and after approximately 100 ms it will try to restart again If the short circuit condition is still present after this time this cycle will be repeated The average dissipation will be low because of this low duty cycle e Incase of a short to one of the supply lines this will trigger the OCP and the amplifier will be shut down During restart the window protection will be activated As a result the amplifier will not start until 100 ms after the short to the supply lines is removed Incase of impedance drop e g due to dynamic behavior of the loudspeaker the same protection will be activated The maximum output current is again limited to 4 A but the amplifier will NOT switch off completely thus preventing audio holes from occurring The result will be a clipping output signal without any artifacts Window Protection WP The WP checks the PWM output voltage before switching from Sleep mode to Mute mode outputs switching and is activated Dur
26. ctivated see Table 6 0 8 V Operating mode 2 2 5 3 3 V Bias voltage for inputs pin INREF Votbias bias output voltage with respect to pin VssA 2 1 V Half supply voltage Pins HVP1 and HVP2 Vo output voltage half supply voltage to charge SE 0 5Vp 0 5Vp 0 5Vp V capacitor 0 2 0 2 lo output current Vuve1 Vo 1 V 50 mA Vuvp2 Vo 1 V Pin HVPREF Vo output voltage half supply reference voltage in 0 5Vp 0 5Vp 0 5Vp V Mute mode 0 2 0 2 Reference voltage for internal logic pin DREF Vo output voltage 4 5 4 8 5 1 V Amplifier outputs pins OUT1 and OUT2 IVo ottset output offset voltage SE with respect to pin HVPREF Mute mode 15 mV Operating mode 100 mV BTL Mute mode 20 mV Operating mode 150 mV Stabilizer output pins STAB1 and STAB2 Vo output voltage Mute mode and Operating mode 10 11 12 V with respect to pins Vssp and Vssp2 Voltage protection VP uvp undervoltage protection 8 0 9 2 9 9 V supply voltage VP ovp overvoltage protection 36 1 37 4 40 V supply voltage VP th ubp l low unbalance protection Vuverer 11 V 18 V threshold supply voltage Vp th ubpyh high unbalance protection Vuverer 11 V 29 V threshold supply voltage Current protection lo ocp overcurrent protection current limiting 4 5 5 A output current Temperature protection Tact th_prot thermal protection activation 155 160 C temperature TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 Jun
27. d in a SE configuration a so called pumping effect can occur During one switching interval energy is taken from one supply e g Vppp1 while a part of that energy is delivered back to the other supply line e g Vssp1 and visa versa When the power supply cannot sink energy the voltage across the output capacitors of that power supply will increase The voltage increase caused by the pumping effect depends on Speaker impedance Supply voltage Audio signal frequency e Value of decoupling capacitors on supply lines e Source and sink currents of other channels The pumping effect should not cause a malfunction of either the audio amplifier and or the power supply For instance this malfunction can be caused by triggering of the undervoltage or overvoltage protection of the amplifier Pumping effects in a SE configuration can be minimized by connecting audio inputs in anti phase and change the polarity of one speaker This is illustrated in Figure 12 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 27 of 48 NXP Semiconductors TDA8932B TDA8932B_3 Class D audio amplifier Fig 12 SE application for reducing pumping effects 001aad763 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 28 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 14 9 SE curves measured in reference desi
28. e 2007 18 of 48 NXP Semiconductors TDA8932B Table 10 Static characteristics Continued Vp 22 V fos 320 kHz Tamp 25 C unless otherwise specified Class D audio amplifier Symbol Parameter Conditions Min Typ Max Unit Tact th fold thermal foldback activation 140 150 C temperature Oscillator reference pin OSCIOP Vin HIGH level input voltage 4 0 z 5 V Vi LOW level input voltage 0 0 8 V Vou HIGH level output voltage 4 0 5 V VoL LOW level output voltage 0 0 8 V Nglave max maximum number of slaves driven by one master 12 3 1 Measured with respect to pin CGND 2 Measured with respect to pin Vssp Hw 13 Dynamic characteristics Table 11 Switching characteristics Vp 22 V Tamb 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Internal oscillator Toss oscillator frequency Rosc 39 kQ 320 kHz range 300 500 kHz Timing PWM output pins OUT1 and OUT2 tr rise time lo20A 10 ns tr fall time lo 0A 10 ns tw min minimum pulse width lo20A 80 ns Table 12 SE characteristics Vp 22 V B 2x 40 f 1 kHz fosc 320 kHz Rs lt 0 1 OL Tamp 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit THD N total harmonic Po 1W 2l distortion plus noise f 1 kHz 0 005 0 05 o fi 6 kHz 0 08 0 10 Gucl closed loop voltage gain Vi 100 mV no load 29 30 31 dB AGy voltage gain difference 0 5 1 dB Ocs channel separati
29. e for use in medical military aircraft space or life support equipment nor in applications where failure or 21 Contact information malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to warranty intellectual property rights infringement and lim
30. ed input 1 Vp230V R 22x80 2 Vp222V R 2x4Q Fig 16 Supply voltage ripple rejection as a function of Po W channel Ri 0 Q 20 kHz brick wall filter AES17 1 Vp222V RH 22x40 2 Vp230V RL 22x80 Fig 17 Signal to noise ratio as a function of output power per channel frequency 120 001aad778 0 001aad779 Ocs S N 2 dB dB f 20 80 40 60 40 80 1 M t 2 0 100 107 1071 1 10 102 10 102 103 104 105 fi Hz Po 1 W Cuvprer 47 uF 1 Vp 22V RL 2x4Q 2 Vp 30V RL 2x8Q Fig 18 Channel separation as a function of frequency TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 30 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 32 001aaf886 7 Po 1 W channel 4 4 24 Aut 2 v 4 4 i v 4 4 4 L 4 v 16 47718 4 4 8 0 10 14 18 22 26 30 34 38 Vp V f 1 kHz short time Po dashed line will require heat sink for continuous time output power RL 2x4Q THD N 10 RL 2x4 Q THD N
31. el television sets Flat panel monitor sets Multimedia systems Wireless speakers Mini and micro systems Home sound sets founded by Philips NXP Semiconductors TDA8932 B Class D audio amplifier 4 Quick reference data Table 1 Quick reference data Vp 22 V fosc 320 kHz Tamb 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supplies Vp supply voltage asymmetrical supply 10 22 36 V Ip supply current Sleep mode 0 6 1 0 mA latot total quiescent Operating mode no load no 40 50 mA current snubbers and no filter connected Stereo SE channel R lt 0 1 QU Poms RMS output power continuous time output power per channel THD N 10 96 f 1 kHz RL 4 9 Vp 22V 13 8 153 Ww RL 8 Q Vp 30 V 14 0 155 Ww short time output power per 2 channel THD N 10 fi 1 kHz RL 4 Q Vp 29V 23 8 265 Ww Mono BTL R lt 0 1 QU Porms RMS output power continuous time output power THD N 10 f 1 kHz RL 4Q9 Vp 12V 155 172 Ww RL 8 9 Vp 22V 28 9 321 w short time output power 2 THD N 10 96 fi 1 kHz RL 8 Q Vp 29V 49 5 55 0 Ww 1 Output power is measured indirectly based on Rpson measurement 2 Two layer application board 55 mm x 45 mm 35 um copper FR4 base material in free air with natural convection 5 Ordering information Table 2 Ordering information Type number Package Name Description Version TDA8932BT
32. ement is taken on the package 4 Two layer application board 55 mm x 40 mm 35 um copper FR4 base material in free air with natural convection 12 Static characteristics Table 10 Static characteristics Vp 22 V fos 320 kHz Tamp 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply Vp supply voltage asymmetrical supply 10 22 36 V symmetrical supply 5 11 18 V Ip supply current Sleep mode no load 0 6 1 0 mA la tot total quiescent current Operating mode no load no 40 50 mA snubbers and no filter connected Series resistance output power switches Rpson drain source on state Tj 225 C 150 mQ resistance Tj 125 C A 234 mo Power up input pin POWERUPI Vi input voltage 0 6 0 V li input current Vi 3V 1 20 uA Vit LOW level input voltage 0 8 V Vin HIGH level input voltage 6 0 V Engage input pin ENGAGEI Vo output voltage open pin 2 4 2 8 3 1 V Vi input voltage 0 6 0 V lo output current Vi20V 50 60 uA Vit LOW level input voltage 0 8 V Vin HIGH level input voltage 2 4 s 6 0 V TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 17 of 48 NXP Semiconductors TDA8932B Table 10 Static characteristics Continued Vp 22 V fos 320 kHz Tamp 25 C unless otherwise specified Class D audio amplifier Symbol Parameter Conditions Min Typ Max Unit Diagnostic output pin DIAGI Vo output voltage protection a
33. esg 1800 V B Machine Model MM Rs 0 2 C 200 pF L 0 75 uH 11 Thermal characteristics Table 9 Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit S032 package Rth a thermal resistance from junction free air natural convection to ambient JEDEC test board 0l 41 44 K W 2 layer application board B 44 K W Wj lead thermal characterization 30 K W parameter from junction to lead Yj top thermal characterization B 8 K W parameter from junction to top TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 16 of 48 NXP Semiconductors TDA8932B Table 9 Thermal characteristics Continued Class D audio amplifier Symbol Parameter Conditions Min Typ Max Unit HTSSOP32 package Rth a thermal resistance from junction free air natural convection to ambient JEDEC test board p 47 50 K W 2 layer application board 4 48 K W Wj lead thermal characterization 30 K W parameter from junction to lead Yi top thermal characterization B 2 K W parameter from junction to top Rih c thermal resistance from junction free air natural convection 4 0 K W to case 1 Measured on a JEDEC high K factor test board standard EIA JESD 51 7 in free air with natural convection 2 Two layer application board 55 mm x 45 mm 35 um copper FR4 base material in free air with natural convection 3 Strongly depends on where the measur
34. g 29 Supply voltage ripple rejection as a function of frequency 120 001aae118 70 001aaf893 Po W ye S N 60 7 dB 2 x 4 50 80 2 A F o7 40 7 4 A 4 4 4 4 Ps 30 742 st Jt P 4 40 t 20 ae 10 0 0 1072 1071 1 10 10 10 14 18 22 26 30 34 Po W Vp V Ri 0 Q 20 kHz brick wall filter AES17 f 1 kHz short time Po dashed line will require 1 RL249 Vp 12V heat sink for continuous time output power 2 RL 8Q Vp 22V 1 RL 24 Q THD N 10 2 R 4 Q THD N 0 5 96 3 RL 289 THD N 10 96 4 RL28 Q THD N 0 5 96 Fig 30 Signal to noise ratio as a function of output Fig 31 Output power as a function of supply voltage power TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 34 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 32 001aaf896 Po Ww 3 A E a a 2 16 1 8 0 0 120 240 360 480 600 t s a R 4 Q fi 1 kHz 2 layer S032 application board 55 mm x 45 mm without heat sink 30 20 10 001aaf899 60 0 120 240 360 480 600 R 8 Q fi 1 kHz 2 layer SO32 application board 55 mm x 45 mm without heat sink
35. gn 001aad772 102 THD N 10 1 10 2 1073 10 2 10 1 1 10 102 Po W channel a Vp 2 22V BL 22x4Q 1 fj 6kHz 2 f 100Hz 3 fi 1kHz Fig 13 Total harmonic distortion plus noise as a function of output power per channel 001aad773 10 THD N 10 10 1 10 2 1073 10 2 10 1 1 10 102 Po W channel b Vp 30V R 222x890 102 001aad774 THD N 10 1 10 2 1073 10 102 103 104 105 f Hz a Vp2 22V RI 22x40 1 P 2 10W 2 Po 1W Fig 14 Total harmonic distortion plus noise as a function of frequency 102 001aad775 THD N 10 10 2 1073 10 10 103 104 105 fi Hz b Vp 30V RH 22x89 TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 29 of 48 NXP Semiconductors TDA8932B Class D audio amplifier 001aad776 40 dB 30 20 10 102 103 104 105 fi Hz Vi 100 mV RMS Ri 0 Q Cse 1000 pF 1 Vp 30V Rp 2x8Q 2 Vp 22V R 2x4Q Fig 15 Gain as a function of frequency 001aad777 100 10 102 103 104 10 fi Hz Vrippie 500 mV RMS referenced to ground Ri 0 Q short
36. hts reserved Product data sheet Rev 03 21 June 2007 39 of 48 NXP Semiconductors TDA8932B Class D audio amplifier gt VDD Rvdda VDD E I VDDA 100 Cvdd Cvdda t p 220 uF 100 nF 25 V GND Cvssa Ovssp m 100 nF Fr 220 pF Rvssa I 25 V VSS gt VSSA 102 gt VSS VssD HW VssD HW VSSA VSSA B IN1P OSCIO I r id INN HVP1 TuF DIAG Vopp1 7 m Cvddp Mise I ENGAGE BOOT cy control Cen m 15nF rH I OE POWERUP OUT1 dp AN VssP1 SLEEP SEND 3 vss Rsn T1 control VDDA STAB1 Cvssp TU ET Cosc VDDA U1 100 nF Csn t V 470 pF ME VSSA ssa TDA8932B STAB2 cue Y d Ll m Rosc Vssp2 100 nF Cvssp l VSSA OSCREF I Il Cic 39 kQ 100 nF HVPREF OUT2 He INREF BOOT2 Cbo 15nF Bs Cinref V ioonF TEST eure VDD m v7 IN2N HVP2 Cvddp Csn pi To 470 pF IN2P DREF Cdref T VssD HW VSSD HW 100 nF VSSA VSSA 001aaf606 Fig 39 Typical simplified application diagram for 1 x BTL symmetrical supply 15 Test information 15 1 Quality information The General Quality Specification for Integrated Circuits SNW FQ 61 1 is applicable TDA8932B 3 Product data sheet NXP B V 21 June 2007 All rights reserved 40 of 48 Rev 03 21 June 2007 NXP Semiconductors TDA8932 B Class D audio amplifier 16
37. ier using class D technology The audio input signal is converted into a Pulse Width Modulated PWM signal via an analog input stage and PWM modulator To enable the output power Diffusion Metal Oxide Semiconductor DMOS transistors to be driven this digital PWM signal is applied to a control and handshake block and driver circuits for both the high side and low side A 2nd order low pass filter converts the PWM signal to an analog audio signal across the loudspeakers The TDA8932B contains two independent half bridges with full differential input stages The loudspeakers can be connected in the following configurations Mono full bridge Bridge Tied Load BTL Stereo half bridge Single Ended SE The TDA8932B contains common circuits to both channels such as the oscillator all reference sources the mode functionality and a digital timing manager The following protections are built in thermal foldback temperature current and voltage protections NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 5 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier 8 2 Mode selection and interfacing The TDA8932B can be switched in three operating modes using pins POWERUP and ENGAGE Sleep mode with low supply current Mute mode the amplifiers are switching idle 50 96 duty cycle but the audio signal at the output is suppressed by disabling the Vl converter input stages The ca
38. ing the start up sequence when pin POWERUP is switched from Sleep mode to Mute mode In the event of a short circuit at one of the output terminals to Vppp1 Vssp1 Vppp2 Or Vsspo the start up procedure is interrupted and the TDA8932B waits for open circuit outputs Because the check is done before enabling the power stages no large currents will flow in the event of a short circuit NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 9 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier When the amplifier is completely shut down due to activation of the OCP because a short circuit to one of the supply lines is made then during restart after 100 ms the window protection will be activated As a result the amplifier will not start until the short circuit to the supply lines is removed 8 4 5 Supply voltage protection TDA8932B_3 If the supply voltage drops below 10 V the UnderVoltage Protection UVP circuit is activated and the system will shut down directly This switch off will be silent and without pop noise When the supply voltage rises above the threshold level the system is restarted again after 100 ms If the supply voltage exceeds 36 V the OverVoltage Protection OVP circuit is activated and the power stages will shut down It is re enabled as soon as the supply voltage drops below the threshold level The system is restarted again after 100 ms It should be noted
39. itation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights 20 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners For additional information please visit http www nxp com For sales office addresses send an email to salesaddresses nxp com TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 47 of 48 NXP Semiconductors TDA8932B 22 Contents Noo fh WOD 7 1 7 2 8 8 1 8 2 8 3 8 4 8 4 1 8 4 2 8 4 3 8 4 4 8 4 5 8 5 8 6 8 7 9 10 11 12 13 14 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 14 10 14 11 15 15 1 16 17 17 1 General description Features 22 2223 rb eI SER Applications leseeeeeenne Quick reference data L Ordering information lise Block diagram 2i uS Pinning information lesse PINNING ec PX Pin
40. llator input Master mode is enabled by applying a resistor while slave mode is entered by connecting pin OSCREF directly to pin Vssp uw without any resistor The value of the resistor also sets the frequency of the carrier which can be estimated by the following formula NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 7 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier 9 12 45 x 10 Juge ene 1 Rosc Where fosc oscillator frequency Hz Rosc oscillator resistor on pin OSCREF Q 001aad758 550 aa fosc kHz 450 350 250 25 30 35 40 45 Rosc kQ Fig 5 Oscillation frequency as a function of resistor Rosc Table 5 summarizes how to configure the TDA8932B in master or slave configuration For device synchronization see Section 14 6 Device synchronization Table 5 Master or slave configuration Configuration Pin OSCREF OSCIO Master Rosc gt 25 kQ to Vssp Hw output Slave Rosc 0 Q shorted to Vssp Hw input 8 4 Protection The following protection is included in the TDA8932B Thermal Foldback TF OverTemperature Protection OTP OverCurrent Protection OCP Window Protection WP Supply voltage protection UnderVoltage Protection UVP OverVoltage Protection OVP UnBalance Protection UBP ElectroStatic Discharge ES
41. on Po 1 W fi 1 kHz 70 80 dB SVRR supply voltage ripple rejection Operating mode Il fi 100 Hz 60 dB fi 1 kHz 40 50 dB IZil input impedance differential 70 100 kQ Vn o noise output voltage Operating mode Rs 0 Q a 100 150 uV Mute mode E 70 100 uV Voimute mute output voltage Mute mode V 1 V RMS and 100 uV fi 1 kHz TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 19 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier Table 12 SE characteristics Continued Vp 22 V Ry 2x AQ fis 1 kHz fosc 320 kHz Rg lt 0 1 QL Tamp 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit CMRR common mode rejection ratio Vi cm 1 V RMS 75 dB Npo output power efficiency Po 15W Vp 22V RL 42 90 92 Vp 30V R_ 82 91 93 Po RMS RMS output power continuous time output power per SI channel RL 4 Q Vp 22V THD N 0 5 fi 1 kHz 10 9 12 1 W THD N 0 5 f 100 Hz 12 1 W THD N 10 fi 1 kHz 13 8 15 3 W THD N 10 926 fi 100 Hz 15 3 W R 8 Q Vp 30 V THD N 0 5 fi 1 kHz 11 1 12 3 W THD N 0 5 fi 100 Hz 12 3 W THD N 10 fi 1 kHz 14 0 15 5 W THD N 10 926 fi 100 Hz 15 5 W short time output power per channel E RL 4 Q Vp 29V THD N 0 5 19 0 21 1 W THD N 10 23 8 26 5 S W 1 Rs is the series resistance of inducto
42. p HW 17 negative digital supply voltage and handle wafer connection DREF 18 decoupling of internal reference 5 V regulator for logic supply NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 4 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier Table 3 Pin description Continued Symbol Pin Description HVP2 19 half supply output voltage 2 for charging single ended capacitor for channel 2 Vppp2 20 positive power supply voltage for channel 2 BOOT2 21 bootstrap high side driver channel 2 OUT2 22 PWM output channel 2 Vssp2 23 negative power supply voltage for channel 2 STAB2 24 decoupling of internal 11 V regulator for channel 2 drivers STAB1 25 decoupling of internal 11 V regulator for channel 1 drivers Vsspt 26 negative power supply voltage for channel 1 OUT1 27 PWM output channel 1 BOOT1 28 bootstrap high side driver channel 1 VppP1 29 positive power supply voltage for channel 1 HVP1 30 half supply output voltage 1 for charging single ended capacitor for channel 1 OSCIO 31 oscillator input in slave configuration or oscillator output in master configuration Vssp HW 32 negative digital supply voltage and handle wafer connection Exposed die HTSSOP32 package only pad 1 The exposed die pad has to be connected to Vssp uw 8 Functional description TDA8932B_3 8 1 General The TDA8932B is a mono full bridge or stereo half bridge audio power amplif
43. pacitors on pins HVP1 and HVP2 have been charged to half the supply voltage asymmetrical supply only Operating mode the amplifiers are fully operational with output signal Fault mode Both pins POWERUP and ENGAGE refer to pin CGND Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins Table 4 Mode selection Mode Pin POWERUP ENGAGE DIAG Sleep 0 8V 0 8V don t care Mute 2 V to 6 0 VEI lt 0 8 VI 22V Operating 2 V to 6 0 VEI 2 4 V to 6 0 VIN 22V Fault 2 V to 6 0 VEI don t care lt 0 8V 1 In case of symmetrical supply conditions the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage VppA Vppp1 Or Vppp If the transition between Mute mode and Operating mode is controlled via a time constant the start up will be pop free since the DC output offset voltage is applied gradually to the output between Mute mode and Operating mode The bias current setting of the Vl converters is related to the voltage on pin ENGAGE e Mute mode the bias current setting of the Vl converters is zero Vl converters disabled Operating mode the bias current is at maximum The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a decoupling capacitor on pin ENGAGE The value of the capacitor on pin ENGAGE should be 470 nF TDA8932B 3 NXP B V 21 June 2007 All rights
44. r and capacitor of low pass LC filter in the application 2 THD N is measured in a bandwidth of 20 Hz to 20 kHz AES17 brick wall 3 Maximum Vippie 2 V p p Rs 0 Q 4 B 20Hzto 20 kHz AES17 brick wall 5 Output power is measured indirectly based on Rpson measurement Two layer application board 55 mm x 45 mm 35 um copper FR4 base material in free air with natural convection Table 13 BTL characteristics Vp 22 V R 8 Q fi 1 kHz fosc 320 kHz Rs lt 0 1 QL Tamb 25 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit THD N total harmonic Po 1W 2l distortion plus noise f 1 kHz z 0 007 0 1 f 6 kHz z 0 05 0 1 Gye closed loop voltage gain 35 36 37 dB SVRR supply voltage ripple rejection Operating mode Il fi 100 Hz 75 dB fi 1000 Hz 70 75 dB sleep f 100 Hz B 80 dB IZil input impedance differential 35 50 kQ TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 20 of 48 NXP Semiconductors TDA8932B Vp 22 V R 8 Q fi 1 kHz fosc 320 kHz Rs lt 0 1 QL Tamp 25 C unless otherwise specified Class D audio amplifier Table 13 BTL characteristics Continued Symbol Parameter Vn o noise output voltage Vo mue mute output voltage CMRR common mode rejection ratio Npo output power efficiency Pos RMS output power Conditions R 02 Operating mode Mute mode Mute mode V 1 V RMS
45. recautions as indicated on the packing must be respected at all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 42 TDA8932B_3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 44 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier maximum peak temperature MSL limit damage level temperature minimum peak temperature minimum soldering temperature peak temperature time 001aac844 MSL Moisture Sensitivity Level Fig 42 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description 18 Abbreviations Table 18 Abbreviations Acronym Description BTL Bridge Tied Load DMOS Double diffused Metal Oxide Semiconductor ESD ElectroStatic Discharge OCP OverCurrent Protection OTP OverTemperature Protection OVP OverVoltage Protection PWM Pulse Width Modulation SE Single Ended TF Thermal Foldback UBP UnBalance Protection UVP UnderVoltage Protection WP Window Protection TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 45 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier 19 Revision history Table 19 Revision history Document ID Release date Data sheet statu
46. s 14 11 Typical application schematics simplified gt VP Rvdda VP VPA 19s I Cvdda TL Ovddp 100 nF 220 uF I 85 V GND Vssp HW Cin T 470 nF Cin I 470 nF VP i Cvddp Chvp 100 nF 100 nF MUTE control xps T I Cen Lic I 470 nF m SLEEP control Rsn mi 100 Gosc U1 Csn ole L C TDA8932B 470 pF vse 100 nF Cstab 77 g Rosc 100 nF T n 39 kQ ITI Lic TL Chvpref Jr Chvp E T 47 uF 25 V 100 nF Rsn ed 0n Ci I ee HT cen Cle t Cse in V 470pF ll ven 100 nF BE eq 470 nF Cin IN2P td ITT j Cdref Chvp 470nF Vssp HW T 100nF 100 nF 77 ITI 001aaf601 Fig 36 Typical simplified application diagram for 2 x SE asymmetrical supply TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 37 of 48 NXP Semiconductors TDA8932B Class D audio amplifier gt VP Rvdda VP 100 VPA I Cvdda V Ovddp 100 nF 220 uF 85 V GND VSSD HW IN1P MUTE ININ control SLEEP control VSSD HW VSSD HW U1 TDA8932B 2 Rhvp Rhvp OSCIO 4702 470Q HVP1 VDDP1 ii A Cvddp Chvp BOOT1 pi M 100 nF T 100 nF 15 nF mI OUT Llc VssP1 Rsn Clc STAB
47. s Change notice Supersedes TDA8932B 3 20070621 Product data sheet TDA8932B 2 Modifications Status upgraded to Product data sheet TDA8932B 2 20070329 Preliminary data sheet z TDA8932B_1 TDA8932B 1 20070214 Objective data sheet TDA8932B 3 NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 46 of 48 NXP Semiconductors TDA8932B 20 Legal information 20 1 Data sheet status Class D audio amplifier Document status I2 Product status Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 20 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NX
48. ssa OSCREF HVPREF INREF TEST IN2N IN2P VssD HW VSSD HW VSSD HW VSSD HW OSCIO IN1P OSCIO HVP1 IN1N HVP1 VppP1 DIAG VpDpP1 BOOT1 ENGAGE BOOT1 OUT1 POWERUP OUT1 VssP1 CGND VssP1 STAB1 VDDA STAB1 TDA8932BT TDA8932BTW STAB2 Vssa STAB2 Vssp2 OSCREF Vssp2 OUT2 HVPREF OUT2 BOOT2 INREF BOOT2 VppP2 TEST VppP2 HVP2 IN2N HVP2 DREF IN2P DREF VSSD HW VSSD HW VSSD HW 001aaf598 001aaf599 Fig 3 Pin configuration HTSSOP32 Fig 2 Pin configuration S032 TDA8932B_3 7 2 Pin description Table 3 Pin description Symbol Pin Description VssD HW 1 negative digital supply voltage and handle wafer connection IN1P 2 positive audio input for channel 1 IN1N 3 negative audio input for channel 1 DIAG 4 diagnostic output open drain ENGAGE 5 engage input to switch between Mute mode and Operating mode POWERUP 6 power up input to switch between Sleep mode and Mute mode CGND 7 control ground reference for POWERUP ENGAGE and DIAG Vppa 8 positive analog supply voltage Vssa 9 negative analog supply voltage OSCREF 10 input internal oscillator setting only master setting HVPREF 11 decoupling of internal half supply voltage reference INREF 12 decoupling for input reference voltage TEST 13 test signal input for testing purpose only IN2N 14 negative audio input for channel 2 IN2P 15 positive audio input for channel 2 Vssp HW 16 negative digital supply voltage and handle wafer connection Vss
49. that supply voltages 40 V may damage the TDA8932B Two conditions should be distinguished 1 If the supply voltage is pumped to higher values by the TDA8932B application itself see also Section 14 3 the OVP is triggered and the TDA8932B is shut down The supply voltage will decrease and the TDA8932B is protected against any overstress 2 If a supply voltage gt 40 V is caused by other or external causes then the TDA8932B will shut down but the device can still be damaged since the supply voltage will remain 40 V in this case The OVP protection is not a supply voltage clamp An additional UnBalance Protection UBP circuit compares the positive analog supply voltage Vppa and the negative analog supply voltage VssA and is triggered if the voltage difference between them exceeds a certain level This level depends on the sum of both supply voltages The unbalance threshold levels can be defined as follows e LOW level threshold VP th ubp l 95 X VHVPREF HIGH level threshold VP th ubp h gt 95 X VuyPREF In a symmetrical supply the UBP is released when the unbalance of the supply voltage is within 6 96 of its starting value Table 6 shows an overview of all protection and the effect on the output signal Table 6 Protection overview Protection Restart When fault is removed Every 100 ms OTP no yes OCP yes no WP yes no UVP no yes OVP no yes UBP no yes NXP B V 21 June 2007 All rights reser
50. tion 14 8 4 audio input p 001aad760 Fig 7 Input configuration for mono BTL application Output voltage buffers When pin POWERUP is set HIGH the half supply output voltage buffers are switched on in asymmetrical supply configuration The start up will be pop free since the device starts switching when the capacitor on pin HVPREF and the SE capacitors are completely charged Output voltage buffers NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 11 of 48 NXP Semiconductors TDA8932B 9 Internal circuitry Class D audio amplifier Pins HVP1 and HVP2 The time required for charging the SE capacitor depends on its value The half supply voltage output is disabled when the TDA8932B is used in a symmetrical supply application Pin HVPREF This output voltage reference buffer charges the capacitor on pin HVPREF Pin INREF This output voltage reference buffer charges the input reference capacitor on pin INREF Pin INREF applies the bias voltage for the inputs TDA8932B 3 Table 7 Internal circuitry Pin Symbol Equivalent circuit 1 Vssp HW 1 16 V 16 Vssb HwW 17 32 zx 17 Vssp HW 32 Vssp HW VSSA 001aad784 2 IN1P Vi 3 IN1N PDA 12 INREF 20 2 15 A 14 IN2N 15 IN2P asko A Y AN Y 12 t 1 P gt HVPREF 48 KQ A Y t 2096 2kQ A Y t 2096 3 14 gt
51. uivalent series resistance SE capacitor Q Example A 4 Q speaker in the BTL configuration can be used up to a supply voltage of 18 V without running into current limiting Current limiting clipping will avoid audio holes but it causes a comparable distortion like voltage clipping Speaker configuration and impedance For a flat frequency response second order Butterworth filter it is necessary to change the low pass filter components Llc and Clc according to the speaker configuration and impedance Table 14 shows the practical required values Table 14 Filter component values Configuration Ri Q Lic uH Cic nF SE 4 22 680 6 33 470 8 47 330 BTL 4 10 1500 6 15 1000 8 22 680 Single ended capacitor The SE capacitor forms a high pass filter with the speaker impedance So the frequency response will roll off with 20 dB per decade below f 3gp 3 dB cut off frequency NXP B V 21 June 2007 All rights reserved Product data sheet Rev 03 21 June 2007 24 of 48 NXP Semiconductors TDA8932 B Class D audio amplifier The 3 dB cut off frequency is equal to 1 f 3aB 2n x R X Cse Where f 3ag 3 dB cut off frequency Hz R load impedance Q Cse single ended capacitance F see Figure 36 Table 15 shows an overview of the required SE capacitor values in case of 60 Hz 40 Hz or 20 Hz 3 dB cut off frequency Table 15 SE capacitor values Impedance Q Cse uF f 3ag
52. ved Product data sheet Rev 03 21 June 2007 10 of 48 NXP Semiconductors TDA8932 B TDA8932B_3 8 5 8 6 8 7 Class D audio amplifier Diagnostic input and output Whenever a protection is triggered except for TF pin DIAG is activated to LOW level see Table 6 An internal reference supply will pull up the open drain DIAG output to approximately 2 4 V This internal reference supply can deliver approximately 50 uA Pin DIAG refers to pin CGND The diagnostic output signal during different short conditions is illustrated in Figure 6 Using pin DIAG as input a voltage 0 8 V will put the device into Fault mode Vo 2 4 V amplifier restart no restart 0v 50 ms 50 ms short to shorted load supply line 001aad759 0v Fig 6 Diagnostic output for different short circuit conditions Differential inputs For a high common mode rejection ratio and a maximum of flexibility in the application the audio inputs are fully differential By connecting the inputs anti parallel the phase of one of the two channels can be inverted so that the amplifier can operate as a mono BTL amplifier The input configuration for a mono BTL application is illustrated in Figure 7 In SE configuration it is also recommended to connect the two differential inputs in anti phase This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping see also Sec

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