Cypress CY7C1344H User's Manual
Contents
1. i DDZZ l ALL INPUTS DESELECT or READ Only except ZZ High Z 2 DON T CARE Notes 20 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DGs are in High Z when exiting ZZ sleep mode Document 001 00211 Rev B Page 13 of 15 CYPRESS CY7C1344H Feedback CYPRESS PERFORM Ordering Information CY7C1344H Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 133 CY7C1344H 133AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C4344H 133AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial 100 CY7C1344H 100AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1344H 100AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial Package Diagram 100 pin 14 x 20 x 1 4 mm 51 85050 16 00 0 20 j 14 00 0 10 100 81 i RRERRRERRRRRRRRERRRR ko ES ES D 0 30 0 08 5 E 3 4 E2. o D S ET 0 65 TYP oS FB 51 Y HEHEHHEHHEHHEHHEHHHE 31 50 R 0 08 MIN 0 20 m 0 MIN STAND OFF 0 05 MIN 0 25 H 0 15 MAX GAUGE PLANE 1 N i v RO 08 MIN 0 20 MAX 0 60 0 15 020 MIN 1 00 REF DETAIL Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation All product and company names 1 40 0 05 SEE DETAIL A L gt 0 20 MAX 160MAX SEATING PLANE 2 1 STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 10 NOTE 51 85050 B mentioned in this document may be the trademarks of their respective holders Document 001 00211 Rev B Page 14 of 15 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applicatio
3. DQPs ian 5 I AMPS mee N BYTE aan WRITE REGISTER gt A DQPc T1 Qj WRITE REGISTER 1 DQPp eo DQa DQa 20 BWA N BYTE WRITE REGISTER 9 8 7 Ld WRITE REGISTER aw INPUT 2 ENABLE REGISTERS 25 124 REGISTER 77 J a SLEEP Note CONTROL 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation Document 001 00211 Rev B 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised April 26 2006 Feedback CY7C1344H PERFORM Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 0 ns Maximum Operating Current 225
4. tapvs ADVH 77 ADV su uspendsburs cet Data Data Out 0 I BURSTREAD l Single WRITE EI Note 17 Full width Write can High Z be initiated by either GW LOW or by GW HIGH BWE LOW and LOW D A Fm D A2 CEE CEE CE D A3 pua uybus a y Document 001 00211 Rev B 17 vont care UNDEFINED Page 11 of 15 BURST WRITE Mies Extended BURST WRITE CY7C1344H Timing Diagrams continued Read Write Timing 18 19 a GEL VEU UM Mu uuu mu omes O S CS T BWE BW A D 17 YU ces D 10 MD 47777 L ips 4 5 0817 Data In 0 High Z D A3 D A5 D A6 D 9 ez 2A lt CDV Data Out 0 oan W oaz b PE Back to Back READs Single WRITE BURST READ al Badio WRITES EN UNDEFINED Notes 22 01025222 18 The data bus Q remains in High Z following a Write cycle unless an ADSP ADSC or ADV cycle is performed 19 GW is HIGH Document 001 00211 Rev B Page 12 of 15 Feedback PERFORM Timing Diagrams continued ZZ Mode Timing 21 77 tZZREC z
5. B CY7C1344H active 2 ADSC is asserted LOW 3 ADSP is deasserted HIGH and 4 the Write input signals GW BWE and BW A D indicate a write access ADSC is ignored if ADSP is active LOW The addresses presented are loaded into the address register and the burst counter control logic and delivered to the memory core The information presented to DQ D A will be written into the specified address location Byte Writes are allowed During byte writes BWA controls DQA BWB controls BWC controls BWD controls DQD All I Os are tri stated when a Write is detected even a Byte Write Since this is common device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated_once a Write cycle is detected regardless of the state of OE Burst Sequences The CY7C1344H provides an on chip two bit wraparound burst counter inside the SRAM The burst counter is fed by A 1 0 and can follow either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE will select a linear burst sequence A HIGH on MODE will select an interleaved burst order Leaving MODE unconnected will cause the device to default to a inter leaved burst sequence Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power cons
6. 5 2 0 ns taps ADSP ADSC Set up before CLK Rise 1 5 2 0 ns tapvs ADV Set up before CLK Rise 1 5 2 0 ns twes GW BWE Set up before CLK Rise 1 5 2 0 ns tps Data Input Set up before CLK Rise 1 5 2 0 ns icES Chip Enable Set up 1 5 2 0 ns Hold Times Address Hold after CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns twEH GW BWE Hold after CLK Rise 0 5 0 5 ns ADV Hold after CLK Rise 0 5 0 5 ns toy Data Input Hold after CLK Rise 0 5 0 5 ns Chip Enable Hold after CLK Rise 0 5 0 5 ns Notes 10 Timing reference level is 1 5V when Vppq 3 3V and 1 25V when Vppg 2 5V 11 Test conditions shown in a of AC Test Loads unless otherwise noted 12 This part has a voltage regulator internally tpgwer is the time that the power needs to be supplied above Vpp minimum initially before a Read or Write operation can be initiated 13 toyz tci 7 toeLz and are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 14 At any given voltage and temperature togpz is less than tog and is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 15 This pa
7. ADSC is active LOW and CE and CE are sampled active feed the 2 bit counter BWA Input Byte Write Select Inputs active LOW Qualified with BWE to conduct Byte Writes to the SRAM BWg Synchronous Sampled on the rising edge of CLK BWc BWp GW Input Global Write Enable Input active LOW When asserted LOW on the rising edge of CLK a global Synchronous Write is conducted ALL bytes are written regardless of the values on and BWE BWE Input Byte Write Enable Input active LOW Sampled on the rising edge of CLK This signal must be asserted Synchronous LOW to conduct a Byte Write CLK Input Clock Clock Input Used to capture all synchronous inputs to the device Also used to increment the burst counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and CEs to select deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with CE Synchronous and to select deselect the device CE is sampled only when a new external address is loaded CEs Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with CE Synchronous and to select deselect the device CE3 is sampled only when a new exte
8. 205 mA Maximum Standby Current 40 40 mA Pin Configurations 100 pin TQFP Pinout LLI 0 n 2 2 lt E ula B gt lt lt 22468588 lt lt o Q sS CO 0 TON e 0000 CO CO CO CO cO DQPc 1 80 DQPg DQcL 12 79 DQc 3 78 DQg 4 77 VssaL 5 76 Vsso DQc 6 75 DQg 7 74 8 73 9 72 DQg 10 7i Vssa Vppa 11 70 DQc 12 69 DQg L DQc 13 68 DQg 14 67 Vss n CY7C1344H 16 65 Vpp Vss 17 64 77 m DQp 18 63 DQp L 34 19 62 DQ 20 61 21 60 DQp 22 59 BYTED DQp 23 58 DO BYTEA DQp 24 57 DQp 25 56 Vssa 26 55 Vsso 27 54 DQp 28 53 DQp 29 52 DQPp 30 51 DAP T QN s 1 QN CO 0 000 C0 CO CO CO 0 SF sb F oS 2 5 gt lt lt lt lt lt lt 5 OF z z 22 2 Document 8 001 00211 Rev B Page 2 of 15 Feedback CYPRESS CY7C1344H PERFORM Pin Definitions Name Description AO A1 Input Address Inputs used to select one of the 64K address locations Sampled at the rising edge of the A Synchronous CLK if ADSP or
9. 211 Rev B Page 15 of 15 Feedback
10. Features CY7C1344H 64K x 36 common 3 3V core power supply 3 3V 2 5V supply Fast clock to output times 6 5 ns 133 MHz version 8 0 ns 100 MHz version PERFORM 2 Mbit 64K x 36 Flow Through Sync SRAM Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences package 22 Sleep Mode option Separate processor and controller address strobes Synchronous self timed write Asynchronous output enable Offered in JEDEC standard lead free 100 Functional Description The CY7C1344H is a 64K x 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic Maximum access delay from clock rise is 6 5 ns 133 MHz version A 2 bit on chip counter captures the first address in a burst and increments the address automati cally for the rest of the burst access All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE depth expansion Chip Enables and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BWr4 pj and BWE and Global Write GW Asynchronous impute include the Output Enable OE and the ZZ pin The CY7C1344H allows either interleaved or linear burst sequences selected by the MODE
11. ax 1 10 ns cycle 100 MHz 205 mA Automatic CE Power Down Vpp Device Deselected 7 5 ns cycle 133 MHz 90 mA Current TTL Inputs VIN 2 Vin VIN lt Vi f fax 10 ns cycle 100 MHz 80 mA inputs switching Automatic Power Down Vpp Device Deselected All speeds 40 mA Current CMOS Inputs Vin gt Vpp 0 3V or Vin x 0 3V f 0 inputs static Automatic CE Power Down Max Vpp Device Deselected 7 5 ns cycle 133 MHz 75 mA f fmax inputs switching 15 Automatic CE Power Down Vpp Device Deselected All speeds 45 mA Current TTL Inputs Vin gt Vpp 0 3V or lt 0 3V f 0 inputs static Notes 7 Overshoot lt Vpp 1 5V Pulse width less than 2 undershoot Vi AC gt 2V Pulse width less than 2 8 Tpower up Assumes a linear ramp from Ov to Vpp min within 200 ms During this time lt Vpp and lt Document 001 00211 Rev B Page 7 of 15 Feedback CYPRESS CY7C1344H PERFORM Capacitance 100 TQFP Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 5 pF Clock Input Capacitance M DD 2 5 pF Cio Input Output Capacitance 5 pF Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test 30 32 C W Ju
12. e burst counter control logic and presented to the memory core If the OE input is asserted LOW the requested data will be available at the data outputs a maximum to after clock rise ADSP is ignored if CE is HIGH Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise 1 CE are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW BWE and BW A D are ignored during this first clock cycle If the write inputs are asserted active see Write Cycle Descriptions table for appropriate states that indicate a Write on the next clock rise the appropriate data will be latched and written into the device Byte Writes are allowed During Byte Writes BWA controls and BWB controls BWC controls and BWD controls All I Os are tri stated during a Byte Write Since this is a common device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated once a Write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise 1 CE4 CE2 and are all asserted Document 001 00211 Rev
13. ence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte Write operations are qualified with the Byte Write Enable BWE and Byte Write Select BW A D inputs A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes All Writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Selects CE CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise 1 and CE are all asserted active and 2 ADSP or ADSC is asserted LOW if the access is initiated by ADSC the write inputs must be deasserted during this first cycle The address presented to the address inputs is latched into the address register and th
14. ervation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CEs ADSP and ADSC must remain inactive for the duration of tzzggc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND First Second Third Fourth Address Address Address Address A4 Ag Ay Ao A1 Ao A1 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Page 4 of 15 Feedback CYPRESS CY7C1344H PERFORM ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 40 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcvc ns tzzREC ZZ recovery time ZZ lt 0 2N 2tcyc ns tzzi ZZ Active to sleep current This parameter is sampled 2 ns tnzzi ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 3 5 6 Addr
15. ess Cycle Description Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle None H X X L X L X X X L H Tri State Power down1 Deselected Cycle None L L X L L X X X X L H Tri State Power down Deselected Cycle None L X H L L X X X X L H Tri State Power down Deselected Cycle None L L X L H L X X X L H Tri State Power down Deselected Cycle None X X X L H L X X X L H Tri State Power down Sleep Mode Power down None X X X H X X X X X X Tri State Read Cycle Begin Burst External L H L L L X X X L L H Q Read Cycle Begin Burst External L H L L L X X X H L H Tri State Write Cycle Begin Burst External L H L L H L X L X L H D Read Cycle Begin Burst External L H L L H L X H L L H Q Read Cycle Begin Burst External L H L L H L X H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H L L H Q Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Wr
16. input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs Address advancement is controlled by the Address Advancement ADV input Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV The CY7C1344H operates from a 3 3V core power supply while all outputs may operate with either a 3 3V 2 5V supply All inputs and outputs are JEDEC standard JESD8 5 compatible Logic Block Diagram ADDRESS REGISTER e MODE 1 1 uu Rn COUNTER AND LOGIC EN aR D TI ADSC ADSP D 7 1 DQ pare Bw N K um DS La WRITE REGISTER 3 WRITE REGISTER 4 4 DQc DQPc Lo sid La T D cL warEmegsTER MEMORY OUTPUT DQs a 11 HTD ev ARRAY SENSE BUFFERS deb
17. ite Bytes B A Write Byte C DQPc Write Bytes A Write Bytes B DQPg Write Bytes C B A Write Byte D DQPp Write Bytes D A DQPp Write Bytes D B DQPp Write Bytes D A DQPp Write Bytes D B DQPp DQPp Write Bytes D B A DQPp DQPc Write Bytes D C A DQPp DQPp DQPa Write All Bytes Write All Bytes lt 00 W 111 1111 xz x x x l 00 11 10 1111 x 8 W 1 11115 51111 8 Document 001 00211 Rev B Page 6 of 15 Feedback CYPRESS PERFORM Maximum Ratings DC Input Voltage CY7C1344H i LOW 20 mA Above which the useful life may be impaired For user guide Curent inte Cupit EOW om lines not tested Static Discharge 2001V MIL STD Meth 1 Storage Temperature 65 to 150 3015 Latch u
18. ite Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Current H X X L X H H L X L H D Notes 2 X Don t Care Logic HIGH L Logic LOW 3 WRITE L when any one or more Byte Write Enable signals BWa BWc BWp and BWE L or GW L WRITE when all Byte Write Enable signals BWg BWc BWp BWE GW 22 m 4 The pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 5 The SRAM always initiates a Read cycle when ADSP is asserted regardless of the state of GW BWE or BW a pj Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the don t care for the remainder of the Write cycle 6 OE is asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a Read cycle all data bits are Tri State when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 001 00211 Rev B rite cycle to allow the outputs to tri state OE is a Page 5 of 15 Feedback CYPRESS PERFORM Truth Table for Read Write 31 CY7C1344H Function 00 m 9 gt Read Read Write Byte A Write Byte B Wr
19. n chip data register that is triggered by the DQPA Synchronous rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle The direction of the pins is DQPc controlled by OE When is asserted LOW the pins behave as outputs When HIGH DQs and DQPp DQPry p are placed in a tri state condition Vpp Power Power supply inputs to the core of the device Supply Vss Ground Ground for the core of the device VDDQ Power Power supply for the I O circuitry Supply Ground Ground for the I O circuitry MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left floating Static selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode pin has an internal pull up NC No Connects Not Internally connected to the die 4M 9M 1 8M 72M 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Document 001 00211 Rev B Page 3 of 15 Feedback CYPRESS PERFORM Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock Maximum access delay from the clock rise is 6 5 ns 133 MHz device The CY7C1344H supports secondary cache in systems utilizing either a linear or interleaved burst sequ
20. nction to Ambient methods and procedures for measuring Oje Thermal Resistance thermal impedance per EIA JESD51 6 85 C W Junction to Case AC Test Loads and Waveforms 3 3V I O Test Load R 3170 OUTPUT 3 3V OUTPUT 500 5 L 1 3510 1 5V INCLUDING JIGAND C a SCOPE b c 2 5V I O Test Load R 16670 OUTPUT xd OUTPUT 500 S 15380 Vr 1 25V INCLUDING 7 JGAND L L SCOPE Note 9 Tested initially and after any design or process change that may affect these parameters Document 001 00211 Rev B Page 8 of 15 Feedback 234 ue CYPRESS CY7C1344H PERFORM Switching Characteristics Over the Operating Range 10 11 133 MHz 100 MHz Parameter Description Min Max Min Max Unit POWER Vpp Typical to the First Access l 1 1 ms Clock Clock Cycle Time 7 5 10 ns tcu Clock HIGH 2 5 4 0 ns teL Clock LOW 2 5 4 0 ns Output Times tepv Data Output Valid after CLK Rise 6 5 8 0 ns Data Output Hold after CLK Rise 2 0 2 0 ns telz Clock to Low z 3 14 15 0 0 ns 2 Clock to 213 14 15 3 5 3 5 ns toEv OE LOW to Output Valid 3 5 3 5 ns toELz OE LOW to Output 2113 14 15 0 0 ns 7 OE HIGH to Output 2113 14 15 3 5 3 5 ns Set up Times tas Address Set up before CLK Rise 1
21. ns unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PER FQ RM Document History Page CY7C1344H Document Title CY7C1344H 2 Mbit 64K x 36 Flow Through Sync SRAM Document Number 001 00211 REV ECN NO Issue Date Orig of Change Description of Change 347377 428408 PCI NXR New Data Sheet Changed address of Cypress Semiconductor Corporation on Page 1 from 8901 North First Street to 198 Champion Court Changed Three State to Tri State Modified Input Load to Input Leakage Current except ZZ and in the Electrical Characteristics Table Modified test condition from lt Vpp to Vin lt Vpp Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51 85050 from A to B 459347 See ECN NXR Converted from Preliminary to Final Included 2 5V I O option Updated the Ordering Information table Document 001 00
22. p Current sene gt 200 Ambient Temperature with Power 55 to 125 C Operating Range Supply Voltage on Vpp Relative to 0 5V to 4 6V B 4 V Supply Voltage on Relative to GND 0 5V to Vpp angs Commercial 0 C to 70 3 3V 5 10 2 5V 596 DC Voltage Applied to Outputs to V NEC MOM 0 5V to Vppq 0 5V Industrial 40 C to 85 Electrical Characteristics Over the Operating Range 8 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ I O Supply Voltage for 3 3V 3 135 Vpp V for 2 5V I O 2 375 2 625 V Output HIGH Voltage for 3 3V I O 4 0 mA 2 4 V for 2 5V I O 1 0 mA 2 0 VoL Output LOW Voltage for 3 3V lg 8 0 mA 0 4 V for 2 5V I O Io 1 0 mA 0 4 Input HIGH Voltage for 3 3V I O 2 0 Vpp 0 3 V for 2 5V I O 1 7 Vpp 0 3V Vi Input LOW Voltage for 3 3V 0 3 0 8 V for 2 5V I O 0 3 0 7 Ix Input Leakage Current GND lt Vi lt Vppa 5 5 except ZZ MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 pA Input Vpp 30 uA loz Output Leakage Current GND lt V x Vppq Output Disabled 5 5 Ipp Vpp Operating Supply Vpp Max lout 0 mA 7 5 ns cycle 133 MHz 225 mA Current f fm
23. rameter is sampled and not 100 tested Document 001 00211 Rev B Page 9 of 15 Feedback CY7C1344H 7 PACT An rb ww www V Oe Wk MMM A 22777777 ak A Oni Highz 0 qu2 2 0002430 022 12217220 Burst wraps around BURST to its initial state E READ DON T CARE UNDEFINED Note 16 On this diagram when CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or CE is LOW or CE is HIGH Single READ Document 001 00211 Rev B Page 10 of 15 Feedback 0 lii PERF ORM Timing Diagrams continued Write Cycle Timing 16 17 CY7C1344H Lf taps ADH gt lt gt WW WW Y i t ADSC extends burst ADS ADH gt taps ADH lt lt gt 77 ADDRESS WES ME ND DA E BWE BWIA D 15 ADS initiates burst 7 V M Byte write donalsere ign red for first when 2777 WES gt GW 7 17777777 tces qa t WEH 17 17 0 17777 Oi V Ls Nn
24. rnal address is loaded OE Input Output Enable asynchronous input active LOW Controls the direction of the pins When LOW Asynchronous the I O pins behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance Input signal sampled on the rising edge of CLK When asserted it automatically incre Synchronous ments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK active LOW When asserted Synchronous LOW addresses presented to the device are captured in the address registers are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSG Input Address Strobe from Controller sampled on the rising edge of CLK active LOW When asserted Synchronous LOW addresses presented to the device are captured in the address registers 1 0 are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized 22 Input ZZ sleep Input active HIGH When asserted HIGH places the device in a non time critical sleep Asynchronous condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQs Bidirectional Data I O lines As inputs they feed into an o
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