Transcend 512MB SDRAM PC133 Unbuffer Non-ECC Memory
Contents
1. PCB 09 7309 Transcend information Inc TS64MLS64V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Pin Identification Dimensions Symbol Function Side Millimeters Inches A 133 35 0 40 5 250 0 016 Adan BAG Bal Address put z 65 67 2 585 DQ0 DQ63 Data Input Output C 23 49 0 925 D 8 89 0 350 CLKO CLK3 Clock Input E 3 00 0 118 CKEO CKE1 Clock Enable Input F 29 21 0 20 1 150 0 008 G 19 80 0 788 ICS0 CS3 Chip Select Input H 15 80 0 622 l 1 27 0 10 0 050 0 004 RAS Row Address Strobe Refer Placement ICAS Column Address Strobe IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend infor2. 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS64MLS64V6F Serial Presence Detect Specification 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Serial Presence Detect Byte No Function Described s oo a ee Vendor Part pecification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 0D 4 of Column Addresses on this Assembly 10 0A 5 of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC Non parity 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width None 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 3 06 19
3. CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 f 4 Prec All Auto Prec 22 SDRAM Device Attributes General R W Burst 0E 23 SDRAM Cycle Time an highest CL 10ns AO 24 SDRAM Access from Clock Or highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 1row of 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 C3 Transcend information Inc TS64MLS64V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 36 34 4D 4C 73 90 Manufacturers Part Number TS64MLS64V6F 53 36 34 56 36 46 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufactory Variable 95 98 Assembly Serial Number By Manufactory Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Suppor
4. Power H L x L Vv V V x Down Exit S L H x x x x x Precharge Power Entry H x x x Down Mode H L x L H H H X E nl e al ae L H X L V V V DQM H X V X 7 No Operation Command H x x x H X X X L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst
5. operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time RESIN 2 ve 1 tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to Active delay tDAL 2CLK tRP Last data in to new col address delay tCDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data CAS latency 3 2 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 168PIN PC133 Unbuffered DIMM TS64MLS64V6F 512MB With 32Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max Unit Note CAS latency 3 7 5 CLK cycle time tcc 1000 ns 1 CAS latency 2 CLK to valid CAS latency 3 5 4 output delay tSAG ns Ae CAS latency 2 Output data CAS latency 3 3 hold time 10H ng 2 CAS latency 2 CLK high pulse width tCH 2 5 ns 3 CLK lo
6. standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 TS64MLS64V6F ABSOLUTE MAXIMUM RATINGS 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 16 W Short circuit current los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current Inputs liL 10 10
7. 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend information Inc 3 TS64MLS64V6F Block Diagram 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 AO0 A12 A0 A12 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 BAO BA1 DQO0 DQ63 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQO0 DQ7 RAS o RAS RAS RAS 32Mx8 32Mx8 32Mx8 ICAS o CAS SDRAM ICAS SDRAM ICAS CAS SDRAM IWE o IWE IWE IWE IWE CSO ICS ICS ICS CS CKEO CKE 3 2 CKE 5 x CKE aI rm g O a A O DQMO DQM1 CS2 A0 A12 IAO A12 A0 A12 BAO BA1 BAO BA1 BAO BAI BAO BA1 a DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 IRAS sous IRAS og IRAS og aki ICAS SDRAM ICAS SDRAM ICAS SDRAM o ANNE IWE WE ICS ICS CS lt x CKE O z CKE O CKE ej a a a DQM4 DQM6 DQM7 CLKO Q DQM5 CLK2 A0 A12 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 g DQ0 DQ7 DQ0 DQ7 DQO0 DQ7 IRAS yang MIRAS some IRAS sone e ICAS SDRAM CAS SDRAM ICAS SDRAM o WE MWE INE CS1 CS x ICS x CS x CKE1 CKE O g CKE 9 g CKE 8 g CS3 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 IRAS aame IRAS 32Mx8 IRAS amg ICAS SDRAM CAS SDRAM ICAS SDRAM IWE WE IWE ICS ICS ICS CKE a x CKE a x CKE 5 a g o a O A O CLK1 DQM4 DQM5 CLK3 Serial EEPROM SCL SCL SDA SDA A0 A1 A2 SA0 SA1 SA2 This technical information is based on industry
8. TS64MLS64V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Description The TS64MLS64V6F is a 64M bit x 64 Synchronous Dynamic RAM high density for PC 133 The TS64MLS64V6F consists of 16pcs CMOS 32Mx8 bits Synchronous DRAMs in TSOP II 400mil packages anda 2048 bits serial EEPROM on a 168 pin printed circuit board The TS64MLS64V6F is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e Performance Range PC 133 e Conformed to JEDEC Standard 4 clocks e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Placement
9. mation Inc 168PIN PC133 Unbuffered DIMM TS64MLS64V6F 512MB With 32Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 DQ1 45 ICS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM 7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 WE 69 DQ24 111 ICAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 1CS1 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 AS 161 DQ63 36 A6 78 Vss 120 AT 162 Vss 37 A8 79 CLK2 121 A9 163 CLK3 38 A10 AP 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1
10. t CL 2 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend information Inc 11
11. uA 3 Input leakage current I O pins liL uA Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV lt VOUT lt VDDQ Transcend information Inc 168PIN PC133 Unbuffered DIMM TS64MLS64V6F CAPACITANCE VDD 3 3V TA 23 C f 1MHz VREF 1 4V 200 mV 512MB With 32Mx8 CL3 Parameter Symbol Min Max Unit Input capacitance Ao A12 BAo BA CIN1 80 100 pF Input capacitance RAS CAS WE CIN2 80 100 pF Input capacitance CKEO CKE1 CIN3 50 60 pF Input capacitance CLKO CLK3 CIN4 40 45 pF Input capacitance CSO CS3 CIN5 25 35 pF Input capacitance DQM0 DQM 7 CIN6 15 20 pF Data input output capacitance DQ0 DQ63 COUT1 10 15 pF DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to70 C Parameter Symbol Test Condition CAS Latency Value Typ Unit Note Operating Current Burst Length 1 Icc1 6 A 1 One Bank Active tRC tRC min or e loL OmA Precharge Standby Current Icc2P CKE lt ViL max tcc 10ns 32 mA in power down mode Icc2PS CKE amp CLK lt VIL max tCC 32 Icc2N CKE gt VIH min CS2 gt VIH min tcc 10ns 320 Precharge Standb
12. w pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output CAS latency 3 tSHZ 5 4 Ae in Hi Z CAS latency 2 Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC133 Unbuffered DIMM TS64MLS64V6F 512MB With 32Mx8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn cs RAS ICAS WE Dam Baoa AwiAP Note Register Mode Register Set H x L L L L x OP CODE 4 2 Refresh Auto Refresh H 3 Self Entry H L L S L H x 3 Refresh Exit L H H H 3 L BY ag a ae oT ae X x 3 Bank Active Sow Addr H x L L H H x v Row Address Read amp Auto Precharge Disable L Column 4 Column Address Auto Precharge Enable H X H L H x V mae 4 5 Write amp Auto Precharge Disable L Column 4 Column Address H X L H L L X V Address Auto Precharge Enable H Ao A9 4 5 Burst Stop H X L H H L X X 6 Precharge Bank Selection V L Both Banks X 5 L A L s X H i Clock Suspend or Entry H x x x Active
13. y Current Input signals are changed one time during 20ns mA in non power down mode icc2NS CKE2VIH min CLK lt ViL max tcc lt 160 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 10ns 96 mA in power down mode Icc3PS CKE amp CLK lt VIL max tcc lt 96 Icc3N Active Standby Current emake ee AR 480 in non power down mode nput signals are changea one time during ns mA One Banificive ICc3NS SKE gt ViH min CLK lt ViL max tcc 400 Input signals are stable Operating Current Icc4 loL 0 mA 1 Bust Mode Page Burst 1 120 mA tceco 2CLKs Refresh Current ICC5 tRC tRC min 1 840 mA 2 Self Refresh Current ICC6 C 48 CKE lt 0 2V mA L 24 Note 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS VIH VIL VDDQ Vssa Transcend information Inc 1 Measured with outputs open TS64MLS64V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 O A T Vou DOJO AV loc2mA TT Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC
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