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V850E/CA2 JUPITER 32-/16-bit Romless Microcontroller Hardware

1. 150 Chapter6 Instruction Cache 0 0 cece e eee eee eee nn 155 6 1 Features 2 2 cease idee Oona gee e eae oe Pee aed RE RE nee I 155 6 2 Configuration uel deed et ene te eine 156 6 2 1 Four Kbytes 2 way set associative Instruction Cache 157 6 3 Control Registers 0 00 0 cece 158 6 4 Instruction Cache 160 6 5 Instruction Cache 1 166 6 6 Operating lt 167 Chapter 7 DMA Functions DMA 169 TD 2 Eeat fes ool cov le E Re 169 7 2 Control Registers cou Re Rer RR Rr ee mes 170 7 2 1 DMA source address registers to DSAHO to DSAH3 170 7 2 2 DMA destination address registers to DDAHO to 172 7 2 3 DMA transfer count registers 0 to 3 DBCO to 174 7 2 4 DMA addressing control registers 0 to DADCO to DADC3 175 7 2 5 DMA channel control registers 0 to DCHCO to 177 7 2 6 disable status register 0015 178 7 2 7 DMA restart register 5 178 7 2 8 DMA trigge
2. a nnne 230 Restore Processing from Exception Trap esse 231 Debug Trap Pros SIS essen nennen nennen enne 232 Restore Processing from Debug 233 Pipeline Operation at Interrupt Request Acknowledgment Outline 236 Block Diagram of the Clock Generator sss 240 Clock Control Register 1 2 241 Clock Generator Status Register CGSTAT sss 243 Watchdog Timer Clock Control Register WOO 244 Processor Clock Control Register 1 2 sse 245 Reset Source Monitor Register RSM 247 SSCG Frequency Modulation Control Register 248 SSCG Frequency Control Register 0 SCFCO sse 249 SSCG Frequency Control Register 1 SCFC1 sese 250 Power Save Mode State Transition Diagram 252 Preliminary User s Manual U15839EE1VOUMOO Figure 9 11 Figure 9 12 Figure 9 13 Figure 9 14 Figure 9 15 Figure 9 16 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 Figure 10 10 Figure 10 11 Figure 10 12 Figure 10 13 Figu
3. 388 Maximum and Minimum Allowable Baud Rate Error 390 Baud Rate Generator Setting Data 426 Configuration of the CAN Message Buffer Section 430 CAN Message Buffer Registers Layout 431 Relative Addresses of CAN Interrupt Pending Registers 432 Relative Addresses of CAN Common Registers sss 433 Relative Addresses of CAN Module 1 Registers 434 Relative Addresses of CAN Module 2 Registers 435 Relative Addresses of CAN Module 3 efe Registers 436 Preliminary Users Manual U15839EE1VOUMOO 21 Table 14 8 Table 14 9 Table 14 10 Table 14 11 Table 14 12 Table 14 13 Table 14 14 Table 14 15 Table 14 16 Table 14 17 Table 15 1 Table 15 2 Table 16 1 Table 16 2 Table 17 1 Table 17 2 Table A 1 Table A 2 Table A 3 Table A 4 Table A 5 Table A 6 22 Relative Addresses of CAN Module 4 Registers 437 Transmitted Data On the CAN Bus ATS 1 442 Example for Automatic Transmission Priority
4. 189 Transfererid uc coca eee ee ea e beeen ded Pat a AC s ee 197 transie modes esl Bae ee ea ee EEE eni ER ee beads Eus 187 Transter object ade ace ce jad Seen eR e e t ees oe iva ice ce ha ee 193 Transfer start faCtOES doe Pew te Pela EAR UE DUE Gb aoe tae Babe 194 Transfer types uera em re ev eget dhe ee ee a ee deir as e edet 193 Two cycle transfer ves ed evista tis Rios SES SENSE See Xu Be ee ek Pe SIS 193 DMA destination address registers 172 173 DMA disable status 178 DMA restart register llle hn 178 DMA source address registers lilii 170 171 DMA transfer count registers 174 DMA trigger factor registers 1 3 179 180 181 182 DMAG d eure e vee Dub ce Mete hae Volpe X esed L beet RR Pare ads 169 DN s utu deni ats LED Ed Lt VA OE 446 447 451 464 475 477 481 482 489 512 alic P III he ed Ran 178 Brie ETE 170 DSAHZ ea ba Rer Bae ed rei bee e ue o Rule e us RS t iae 170 DSALO eed ox ute Me te tue di eue LM EI add Stated M ten d Mese ty Ce 171 DSA bs anctor ueste La Deu Uu nuu be pL ica cepi er e Em 171 DTFROTODTERS une dre feeder aed ee Dae ee ILS IU tree DE RD RSS 179 180 181
5. 538 15 6 A D Converter Precautions 541 15 7 How to read the A D Converter Characteristics 542 Chapter 16 Port Functions R9 Rb ERE REX ER 545 1671 Feat fes liene E E iei duse 545 16 2 Port Configuration n n nnn 546 16 3 Pin Functions of Each Port 556 16 91 oot maie ot Rt haa earls heec tig as rb mtd 556 16 922 PIE 2 5 oz est bod tears tener n earns bea iu hn eR 559 16 3 3 cM 562 PC o EE 564 NOSIS POM bn ise i ati s en e e 566 10 9 6 SOM 6 6 rer ere dre e ppt 569 10 9 7 BO U 2 ree wx oud ack PERS reed a ease yeni gia RUSSE NUS Eee bod de 572 10 9 9 3POft 18 eic Tuch ett ree acte Wie De eum t pute fece 573 Preliminary Users Manual U15839EE1VOUMOO 11 16 3 9 FONS esie dele uid erue eer Seagate vaut e uius e 574 16 310 Port union arte abe ende o ND ase 575 16 3 t TPOrE GS tb eub eet VLA Ee us 577 16 3 42 POT GT p HERR DUEB elu eal MEAE EE 579 16 3 S POI OM cie irt ee Rb e i Wace lath MIA Fas e Bs ira qui end 581 Chapter 17 RESET eso ua RI I IRRERERREREARERRIEREREREREERG M 583 17 1 Reset Overview DAR E eee ee ee 583 17 2 Features 1 uo nl a AS ee 583 17 3
6. TiGn2 Noise Elimination GCCne 16 bit TO Edge Detection capture compare Control INTCCGn3 TIGn3 Noise Elimination GCCn3 16 bit g TO TO Edge Detection capture compare Control INTCCGn4 Noise Elimination GCCn4 16 bit TO To Edge Detection capture compare Control INTCCGn5 Noise Elimination GCOCn5 16 bit TENSO Edge Detection capture compare fecu 2 gt INTTMGn1 PCLI COUNT1 5 lear feor fae gt TMGni 16 bit fecik 32 64 128 Remark fpc Internal peripheral clock 16 MHz Note TMGnO TMGn 1 are cleared by GCCn0 GCCn5 register compare match 308 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 3 3 Basic configuration The basic configuration is shown below Table 10 4 Timer Gn Configuration List INTTMGnO 2 INTTMGn1 fpcuk 4 INTCCGnO fck 8 Be INTCCGn1 Timer Gn fpcik 16 fPeLK 32 INTCCGn2 fPciK 64 INTCCGn3 128 INTCCGn4 INTCCGn5 Remarks 1 Internal peripheral clock 2 nz0 1 Preliminary User s Manual U15839EE1VOUMOO 309 Chapter 10 Timer 1 Timer Gn 16 bit counter registers TMGn0 TMGn1 The features of the 2 counters TMGnO and TMGn1 are listed below Free running counter that enables counter clearing by compare match of registers GCCn0 GCCn5 Counter clear can be set by software
7. 310 Timer Gn Counter 1 Value Registers TMG ssssssssseeeee 310 Timer Gn counter TMGnO assigned Capture Compare Register 311 Timer Gn counter TMGn1 assigned Capture Compare Register GCOn5 311 Timer Gn free assignable Capture Compare Registers GCCnm m 1 to 4 312 Timer Gn Mode Register TMGMn 1 2 313 Timer Gn Mode Register Low TMGMnL 315 Timer Gn Mode Register Low TMGMnH sse 315 Timer Gn Channel Mode Register TMGOMn sse 316 Timer Gn Channel Mode Register TMGOMnL sss 317 Timer Gn Channel Mode Register TMGOCMnH sss 317 Timer Gn Output Control Register 318 Timer Gn Output Control Register Low OCTLGnL sse 319 Timer Gn Output Control Register High OCTLGnH sse 319 Timer Gn Status Register TMGSTn sese 320 Timing of Output delay operation 321 Timing when both edges of TIGnO are valid free 326 Timing of capture trigger edge detection free run 327 Timing of starting capture trigger edge detection 328 Timing of compare mode free run
8. 528 A D converter register 530 A D trigger node ee eme epu ERU ERE Ua ns 523 ADGRUSs ra LAU iE ULL Ree te Bee Cen d t is 525 531 address set up wait states 137 address setup wait control register 132 8 ve dee cce Bee SLS RES Ba ae ges E EEREN 65 address wait control register 1 eee 132 ADM ine ant a aAa EL a ONENE INL AG AAEREN ANEA PE E 528 ADS foes tot dod oa a A Rus 530 analog delay s dere pe A FRED ST Sete ee A E Am Ba A RTR ME 583 Analog inputs ei ete RENE qox tet ddr eq e ede ge xo de 523 ANIOO AG ANI iic d creen nes tees eR UR HERE Sax Uaa v de Gane Bw en TUR EU ED 49 Dl 132 ASIFOXASIF A 2 LEE tut tL LL PLURA AM LSU CM E 371 ASIMO zi ases ee DH mei e ser 367 DI nMECTT m 367 ASISO to ASIS2 oe A eee nee euer Oe P ES vn thes ba dg 370 Asynclironous eset i5 oo A ais wa RE BN EHE E ES 275 Asynchronous serial interface mode registers 367 Asynchronous serial interface status registers
9. 352 11 4 2 Control of the watch 353 11 4 3 Operation as 1 354 Chapter 12 Watchdog Timer 357 12 1 FuhncHOns nol RES UAE EARLIER AI IRIS 357 12 2 Configurationz llle DEA lieu e te Arken 358 12 3 Watchdog Timer Control 359 124 Operation dA i wig reu Sea Sea SE ae suis Eins 362 12 4 1 Operating as watchdog 362 Chapter 13 Serial Interface 363 13 1 Fe tUres EA MAL LA A ou LUE 363 13 2 Asynchronous Serial Interfaces UART5n UART50 UART51 364 13 241 Features caseo toed PREIS 364 13 2 2 Configuration ba eia i h aiai n 365 19 22 32 Control registers ous ees ewe p Ta xa ep eee ei e Ree 367 13 2 4 Interrupt requests ss i us a SES nes 374 1372 5 Operation Ed eren dus eed ecards bern CE dan x Dada 375 13 2 6 Dedicated baud rate generators BRG of UART5n 0 1 384 10 Preliminary User s Manual U15839EE1VOUMOO 19 27 PRECAUTIONS os ccce ER net eR p Sie niche be EUER ELE 391 13 3 Clocked Serial Interfaces CSI00 to 5 02
10. P83 ANI11 P83 Input ANI 1 P90 P90 Input mode P91 P91 Input mode P92 P92 Input mode P93 P93 Input mode P94 P94 Input mode P95 P95 Input mode P96 P96 Input mode P97 P97 Input mode 16 A16 Address output mode PAH1 A17 A17 Address output mode PAH2 A18 A18 Address output mode PAH3 A19 A19 Address output mode Port AH PAH4 A20 A20 Address output mode PAH5 A21 A21 Address output mode PAH6 A22 A22 Address output mode PAH7 A23 A23 Address output mode PCSO CSO CSO Chip select output mode Port CS PCS3 CS3 PCS3 Input mode PCS4 CS4 PCS4 Input mode CAN module CAN module 4 are available in the derivatives PD703129 A and uPD703129 A1 only Preliminary User s Manual U15839EE1VOUMOO 549 Chapter 16 Port Functions Table 16 2 Port Pin Functions 3 3 Port Name Pin Name Pin Function after Reset PCTO LWR PCTO Input mode Port CT PCT1 UWR PCT1 Input mode PCT4 RD RD Read strobe signal output mode Mode Setting Register Port CM PCMO WAIT WAIT Wait insertion signal input mode 550 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 3 Port block diagram Figure 16 2 Type A Block Diagram Na WR Puc Nn O PMC Nn WR Pm Nn o 2 E 2 E
11. Sa Gg 48 Port functions tec ds E a vale Rod NIU ERR DID eR Re EN FORET M UE PIE FEN 545 POM PINS cuu eive VUES LP ea e ates dues re xu He RELEASE ELE Ei 33 Power save control register 0 2 2 0 ARNEE hn 268 Power save mode register 270 Power save modes x REEF hue Sa Tae ie C ER DATI AERE 239 Power saving functions eu usd reu ride oU PEDE peed T DR ee ae ea aM 251 ens Uk EUR e ea bb ec eed acr n e bra de dis 586 powersup auccm EP ue ed Ra RR DA M RUE Goble 583 PRO sss ce tar aren age Marcus tes tcc NIE dE baat eps yee yaks 149 PRGMDJ dme trit tec RD HIVE tania ale uda uss edat etapas 104 Precautions 606 Preliminary User s Manual U15839EE1VOUMOO Appendix B Index DMA controller DMAC lsssslsesseee mr 198 Prescaler compare registers 0 1 425 Prescaler mode registers 0 1 424 Program counter ed oe ER Sie ended qe De RE PE ESSE 56 57 program tegistel Rees oe eal etu RE a Yate READ 56 program runaway Ne
12. 392 T3 9 1 Features eh te oe tele tes eR EIS ee Sede es Sere eee es 392 13 3 2 Configuration 393 18 3 8 Control registers 0 0 0 ees 395 19 3 4 Operation ox dee i d Sei ER Tien 408 19 3 5 Output PINS E eR X Fe andy E vid qi ine 422 13 3 6 Dedicated baud rate generators 0 1 1 423 Chapter 14 FCAN Interface Function 00 enes eee eee kk kreere ren 427 14 4 Feat res ER Rel cag 427 14 2 Outline of the FCAN System 428 14 2 Generals 2 oe ete e eb tdt pra depu E us 428 14 2 2 CAN memory and register 429 14 2 3 Clock structure 0 0 hn 438 14 2 4 Interrupt handling 0 0 eee ae 439 1425 Time stamp 2 55 2682 2 ja as ies Se S 441 14 2 6 Message handling 0 0 cece eae 443 14 2 7 Mask handling ee eae 448 14 2 8 Remote frame handling 449 14 3 Control and Data 452 14 3 1 Bit set clear function llli 452 14 3 2 Common registers 454 14 3 3 CAN interrupt pending 5
13. 59 Interval timer llle IIIA 271 290 304 306 329 337 349 Inclina 296 lu Pm 223 edo e dee P De ERE genre DE ds 224 lir c 225 aad fed tpe RU Dy e eed anya veo e d 226 INTSERO b ONES DI RISE EE 374 INTSERT ea detecte ati ed ar Reb oe teu vous d eyed ata 374 INTSRO oue iore teret UR ERI are han PS ERAS eee MS Pee D Roe 374 INTSRT EIQUE EAS ER Eee etu per e de UR docet ui dg rand 374 ei cee xc 374 T a tages 374 te oS ANG fet LA S meena 220 L Least Recently Used 155 LINK POMEL roe Dee Re ete ipee Cee INIRE VA Ug dg ale 57 Load store instructions with long short format 24 LOCKO 165 low power systems 4 9 2 e nn 251 LRU algorithm 155 M malf nctlon x e Ped Re DEEP DRESDEN CAP EG E RE sad tet 583 Maskable interrupt status flag 0 RR Ih 220 Maskable interrupts 2 1 net ett Reb ute eh ure xa uri Bi eu 209 PNOMHES leanna P rU 212 Match and clear mode 2e E ERR ee wee Pte deg a HERE 335 match and clearmode iili db X ei ws WCET ERE RE Dee e te X Renan 322 MODES n a RR ester ne reg 6
14. 70 List of Peripheral I O 76 List of programmable peripheral I O registers 85 The Values of VSWC Register depending on System Clock 108 Number of Bus Access Clocks sssssssssssssssseeseeenene nnne 116 Bus Priority Order te ta een egeo ae e D Du eee 135 Relationship Between Transfer Type and Transfer 193 Interrupt Exception Source 5 200 Addresses and Bits of Interrupt Control Registers 217 Interrupt Response TIMES oa e ER nennen nennen nennen nennen einen nennen 237 Power Saving Modes Overview 251 Power Saving Mode Functions ssssssssssssseseeeeeeneen ener nnne nene 254 Power Saving Mode Functions sssssssssssssseeeee ener enne nnne neni 255 Operating states in HALT mode sse eene 256 Operation after HALT mode release by interrupt request 257 Operating States in IDLE Mode 258 Operating States in WATCH Mode sse nennt nnns 259 Operation after WATCH mode release
15. Instruction 1 IF ID EX MEM WB Instruction 2 IFX IDX Interrupt acknowledgement operation INT1 J INT2 INT3 INT4 Instruction first instruction of IF ID EX interrupt service routine Remark INT1 to INT4 Interrupt acknowledgement processing IFx Invalid instruction fetch IDx Invalid instruction decode 236 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function Table 8 3 Interrupt Response Time Interrupt Response Time Internal System Clocks Condit ondition Internal Interrupt External interrupt Minimum 5 analog delay time The following cases are exceptions n IDLE software STOP mode External bit access 11 analog delay time Two or more interrupt request non sample instructions are executed Access to interrupt control register 8 9 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed However no interrupt will be acknowledged between an interrupt non sample instruction and the next instruction The interrupt request non sampling instructions are as follows El instruction DI instruction LDSR reg2 0x5 instruction for PSW The store instruction for the interrupt control register PICn in service priority register ISPR and command register PRCMD Preliminary User s Manual U15839EE1VOUMOO 237 MEMO 238 Prelimi
16. the Gantt este oh Ne UE Mt oe tg len eee Ret ig 318 Odd parity 4 22 etae See de cae be edd ye eb ters 368 of Dage epo LU ULIS SL UM 145 Oll pagen d e eeu USERS EEG dec eer ED CPI X ai Pras eed am ae e Po p ELE 145 Operation mode euim ce p teque ks eed pe o REIR esI D ke Siren ea ketene RECS d 63 Oscillation stabilization time illis RI Hue 587 oscillator stabilization time s seek p e de p I 3 586 Output delay operation s sasaaa 321 Overal Erro RE 542 OVEMMIOW oaii EE 284 OVA EOT 2 45 runs DLE ne SNR NO 364 P Piirien Pam Le edi eter 556 559 562 564 566 569 574 575 577 579 581 Page ROM configuration 5 149 eA 375 CHECK a ea wes eed ware ERE VERSEHEN 365 saat ss phe eter wale bead di 364 PO cos pear M LM I cR hoi c 56 57 period measurement 325 335 Peripheral area selection control register BPC 114 Peripheral rette edie ane ond ge uei Sex alone dete ane APER peek d 76 peripheral W O ERR ts em br Eb hs ent ewe tants nathan dence 74 Peripheral Status sos doe b
17. Remark Enabling the global operation does not automatically enable any CAN module Each CAN module must be initialised and enabled separately Preliminary User s Manual U15839EE1VOUMOO 515 Chapter 14 FCAN Interface Function Example for C routine 516 int CAN Globallnit void unsigned char i if GOM flag is already set amp 0x01 disable all CAN modules for i 0 i lt CAN MODULES i CAN_ModuleStop i clear GOM flag CGST 0x0001 CGST clear all flags of CGST CGIE OxOOFF disable global interrupts CGCS 0x0000 define internal clock CGTSC 0 0000 clear CAN global time system counter CGTEN 0 0000 disable all timer events clear all message buffers for i20 czCAN MESSAGES i CAN ClearMessage i set bit CGST 0x0100 return 0 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 2 Initialisation sequence for a CAN Module Each CAN module must be initialised by the sequence according to Figure 14 47 Figure 14 47 Initialisation Sequence for a CAN module om CAN Init the module registers CXCTRL but do not clear the INIT flag CXDEF CxIE CXBRP CXSYNC Define Masks Clear INIT flag register CXCTRL END Remark 1 to 4 for the derivatives uPD703129 A uPD703129 A1 x
18. 313 315 Timer Gn output control register 318 TMGGOO rri aa eiae IRR X eT UR OUR LAC dre oops ERROR E 278 MG GO aa da a uae whee EARP AURA 280 EMG DN s noe aite t Ro E eer a n ded eedem de hh ed nae et ahaa 301 TMDI s tubas Lt vod iE Ad LA M E dsl pA EM ML EAD E 298 TMGNMT ex Pipe EH E RE VIR RR ER RESP 313 Ine Pr 315 TMGMAL 5 EE REEL RE eee dh Bee eene P be S efte abo dee Pe has 315 TMGnOr du 310 ae Bett ay bites Gig id DERE gn Is ss 310 Mc Em 320 TraristerTate nas a cederent deett Vr dr e dota deed e ie e d T 364 Transmission buffer 373 Transmission completion interrupt 374 TABQ TXB 373 V Valid edge selection register 282 Melde EE 208 MDDS a uite i Ref ieu ate batt ite Aho alae ett he esta 50 hence Ta pl rir I E STEGE Dott LLL GAMME LM 49 Voltage comparator sae EU LEER ER Hee eR ERR REOR EX RR REA 524 Voltage comparator mode 208 VSS Saar tese De te aon ap tende E dett tia
19. Bit Units Address Function Register Name for Manipulation Via 1 bit 8 bit 16 bit FFFF F1FA In service Priority register 00H FFFF F1FC Command register undefined FFFF F1FE Power Save Control register 00H FFFF F200 A D converter mode register 00H FFFF F201 A D Select Register 00H FFFF F202 A D Conversion Result Register undefined FFFF F203 A D Conversion Result Register H undefined FFFF F400 Port 1 undefined FFFF F402 Port 2 undefined FFFF F404 Port undefined FFFF F406 Port 4 undefined FFFF F408 Port 5 undefined FFFF F40A Port 6 undefined FFFF F40C Port 7 undefined FFFF F40C Port 7 Port 8 undefined FFFF F40E Port 9 undefined FFFF F420 Port 1 mode FFH FFFF F422 Port 2 mode PM2 RW x x FFH FFFF F424 Port 3 mode PM3 RW x x 3FH FFFF F426 Port 4 mode PM4 RW x x 3FH FFFF F428 Port 5 mode PM5 RW x x 7FH FFFF F42A Port 6 mode PM6 RW x x FFH FFFF F42E Port 9 mode PM9 RW x x FFH FFFF F440 Port 1 mode control PMC1 HW x x 00H FFFF F442 Port 2 mode control PMC2 HW x x 00H FFFF F444 Port 3 mode control PMC3 HW x x 00H FFFF F446 Port 4 mode control PMC4 HW x x 00H FFFF F448 Port 5 mode control PMC5 RW x x 00H FFFF F44A Port 6 mode control PMC6 HW x x 00H FFFF F480 MEMC Bus Cycle Type Control register O R W x 8888H FFFF F482 MEMC Bus Cycle Type Control register 1 BCT1 R W x 8888H FFFF F484 MEMC Data Wait Control register 0 DWCO R W x 7777H FFFF F486 MEMC
20. 444 Example for Transmit Buffer Allocation When More Than 5 Buffers Linked to CAN Module ssssssssesssssssesee eene nennen nnne enne nennen sinn 445 Storage Priority for Reception of Data Frames sss 446 Storage priority for Reception of Remote 446 Inner Storage Priority Within a Priority Class eene 447 Remote Frame Handling upon Reception into a Transmit Message Buffer 451 CAN Message Processing by and RDY Bits 476 Address Offsets of the CAN 1 to 4 Mask Registers 486 A D Converter Configuration sess nnns nnne 524 Register format of A D Converter Control Register 527 Functions of each paoe 547 Port Pin EUletiols uii 548 Operation Status of each pin during Reset period 584 Initial Values of CPU and Internal RAM After Reset 588 Symbols in Operand Description 590 Symbols Used for Op Code 590 Symbols Used for Ope
21. sssssssseeeeeeenneeeen eene 329 Timing when GCCn_1 is rewritten during operation free 330 Timing of PWM operation free run sssssessseeeeenn eee eene 332 Timing when OOOOH is set in GCOCnm free run sse 333 Timing when FFFFH is set in GCOnm free 333 Timing when GCCnm is rewritten during operation free 334 Timing when both edges of TIGm are valid match and 336 Timing of compare operation match and 338 Timing when GCCnm is rewritten during operation match and clear 339 Preliminary Users Manual U15839EE1VOUMOO 15 Figure 10 53 Figure 10 54 Figure 10 55 Figure 10 56 Figure 10 57 Figure 10 58 Figure 11 1 Figure 11 2 Figure 11 3 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 Figure 13 9 Figure 13 10 Figure 13 11 Figure 13 12 Figure 13 13 Figure 13 14 Figure 13 15 Figure 13 16 Figure 13 17 Figure 13 18 Figure 13 19 Figure 13 20 Figure 13 21 Figure 13 22 Figure 13 23 Figure 13 24 Figure 13 25 Figure 13 26 Figure 13 27 Figure 13 28 Figure 13 29 Figure
22. 370 Asynchronous serial interface transmission status registers 371 Autofill Function 165 autofill function 155 AVDD Lett e p DETULIT CE DUI FIR DE f eed us 50 525 AN REF EBERT EE IM d e dS 50 525 PN SS rer ene SE eR Re ee uae Big Wee eee UE P meen sd Sere 50 525 B Baud rate generator control registers 386 BCG rude tte A bleues apte nels gin NE NF SE Rob EE ER pete eee ES 134 BGTO 1 D se dcr peu rs adequate C dedo p 115 BG T une Tu Ie ete heen EN Sadat Tn ae D 115 BEG fat eee qol eo ena ode d b ev D o ede ive qot Ss 117 BAG IS NI Xue eru led uer DEM Mist te pre rg Lt 118 Bit manipulation instructions 24 Bootloader MEL 24 Boot Loader ue eee tet e e eel ae een e et Sa Axe beet doe ds ice don 62 d eate Mi LC ig d eget Coda Mts DR tod ifs 84 114 BRGO BRGdT u ze Reda Haee do WERDE Reden pe eoe tee Rei RS 423 BRGGO BRGGOT a ciety an bester haan Oe tunes Oe Site Pee Ang OUR NS den Gia RUE EN 386 Sher perde innare Uere ha giv roi ee ed tete c deleted oa 116 Bus cycle configuration registers 0 1 BCTO BCT1 115 Bus cycle control register 0 a tee 134 Bus size
23. Preliminary User s Manual V850E CA2 JUPITER 32 16 bit Romless Microcontroller Hardware PD703128 0703129 Documen t No U15839EE1VOUMOO Date Published August 2003 NEC Corporation 2003 Printed in Germany NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar
24. WTM1 Controls Operation of 5 bit Counter 9 Clears after operation stops WTMO Enables Operation of Watch Timer 0 Stops operation clears both prescaler and timer 1 Enables operation Remark fw Watch timer clock frequency Preliminary User s Manual U15839EE1VOUMOO 351 Chapter 11 Watch Timer 11 4 Operations 11 4 1 Selection of the Watch Timer Clock With the settings of the clock generator different clocks can be assigned to the Watch Timer With the WTSELn bits n 0 1 of the register 6 different clocks can be switched as the Watch Timer clock Table 11 2 Selection of the Watch Timer Clock CKC Register WTM Register WDTSEL1 WDTSELO WTM7 0 31250 Hz 39063 Hz 0 fy 128 1 7813 Hz 9766 Hz X 0 977 Hz 1221 Hz 0 32000 Hz 1 fxr 1 8000 Hz X 0 1000 Hz Note WTSEL1 bit of CKC register Remark X don t care 352 Preliminary User s Manual U15839EE1VOUMOO Chapter 11 Watch Timer 11 4 2 Control of the watch timer The watch timer operates with time intervals from 500 us to 16 4 s The watch timer generates at its overflow the INTWT interrupt request at fixed time intervals With the WTM1 bit and the WTMO bit the watch timer function can be started With the WTM 1 bit the watch timer function can be stopped independently from the interval timer function For synchronous watch and interval timer function operation The count operation of the watch
25. 508 Sequential CAN Data Read by CPU 512 State Transition Diagram for CAN Modules sees 514 Preliminary Users Manual U15839EE1VOUMOO 17 Figure 14 46 Figure 14 47 Figure 14 48 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 15 10 Figure 15 11 Figure 15 12 Figure 15 13 Figure 15 14 Figure 15 15 Figure 15 16 Figure 15 17 Figure 15 18 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 9 Figure 16 10 Figure 16 11 Figure 16 12 Figure 16 13 Figure 16 14 Figure 16 15 Figure 16 16 Figure 16 17 Figure 16 18 Figure 16 19 Figure 16 20 Figure 16 21 Figure 16 22 Figure 16 23 Figure 16 24 Figure 16 25 Figure 16 26 Figure 16 27 Figure 16 28 Figure 16 29 Figure 16 30 Figure 16 31 Figure 16 32 Figure 16 33 Figure 16 34 Figure 16 35 Figure 16 36 18 General Initialisation Sequence for the CAN 515 Initialisation Sequence for a CAN module sse 517 Setting CAN Module into Initialisation State 519 Block Diagram of A D Converter cccceecceceeeeeeeeeeeeeeaeeeeeeesecaeeesaaaeeteneeeseaeeesaeeseaes 526 A D Converter Mode Register ADM ccccceeeeeee
26. eene enne nnne nnn 551 Typa B Block Digg reins inem feed ee eet 552 Type C Block Diagram oor ced a ducet p dv edt dede e era A vou 553 Type D Block 554 Type E Block Diagr m 555 E Ty e e aee m ee eed ees 556 Port 1 Mode Register PM1 557 Port 1 Mode Control Register PMC1 M1 W M u sssseeeee reen erne nerne 558 2 2 p 559 Port 2 Mode Register PM2 560 Port 2 Mode Control Register PMC2 sssssssssesseeneeeen enne 561 wenig 562 Port Mode Register nnne 563 Port 3 Mode Control Register PMC3 sssssssseseeeeeeen 563 Pon APAI e nee pvc eia dr deo 564 Port 4 Mode Register 35 22 565 Port 4 Mode Control Register PMCA sssssssssseeeeseneneeen nennen 565 wen sdixo decr 566 Port 5 Mode Register ennemis 567 Port 5 Mode Control Register PMC5 22 568 Porte PE 569 Port 6 Mode Register PM6 570 Port 6 Mode Control Regist
27. 156 Configuration of 4 KB 2 Way Set Associative Instruction Cache 157 Instruction Cache Control Register ICC 158 Instruction Cache Data Configuration Register 1 159 Instruction Cache Initial Register 1 159 Operation on Instruction Cache Hit ssessssssseseseeeeeeenn enne 160 Operation on Instruction Cache Miss sss 161 Refill Sequence to Instruction Cache 16 bit Data 162 iCache Area Setting Example ssssssssssssesesss essent 168 DMA Source Address Registers to DSAH3 DSAHO to DSAH3 170 DMA Source Address Registers DSALO to DSAL3 DSALO to DSAL3 171 DMA Destination Address Registers OH to DDAOH to DDA3H 172 DMA Destination Address Registers LO to L3 DDALO to DDALS 173 DMA Transfer Count Registers 0 to DBCO to 174 DMA Addressing Control Registers 0 to DADCO to DADC3 1 2 175 DMA Channel Control Registers 0 to 3 DCHCO to 177 DMA Disable Status Register 00 15 178 DMA Restart Register DRST ssssssssssssssseeeee eene nenne
28. 2 0 2 B5 B5tz5 5 8 8 8822282 2650z22 KSER I 2250655 Sm lt ilr Loo c eza lt lt conu Pan aa Note FCRXD3 FCTXD3 FCRXD4 and FCTXD4 are available only in the derivatives uPD703129 A and 0703129 A1 Preliminary User s Manual U15839EE1VOUMOO 27 Pin Identification to A23 DO to D15 ANIOO to ANI 1 AVpp AVREF AVss FCRXD1 to FCRXD4 FCTXD1 to FCTXD4 CVpp GND39 to GND3g GNDsg to GND52 INTPO to INTP5 INTPnO INTPn5 INTP2n MODEO to MODE2 NMI P10 to P17 P20 to P27 P30 to P35 P40 to P45 P50 to P56 P60 to P67 P70 to P77 P80 to P83 P90 to P97 Chapter 1 Address Bus Data Bus Analog Input Analog Power Supply Analog Reference Voltage Analog Ground CAN Receive Line Input CAN Transmit Line Output Clock Generator Power Supply Clock Generator Ground Ground for 3 V Power Supply Ground for 5 V Power Supply External interrupt request _ Interrupt Request from Peripherals Mode Inputs Non Maskable Interrupt Request Port 1 Port 2 Port Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Introduction PAHO to PAH7 PCMO PCSO0 PCS3 PCS4 PCTO PCT1 PCT4 RESET RESOUT RXD50 to RXD51 SCKO00 5 SCK02 5100 SIO1 S102 5000 SO01 S002 TIGOO to TIGOS TIG10 to TIGOS TICOO TICO1 to TOG04 TOG11 to TOG14 TXD50 to TXD51
29. 386 Allowable Baud Rate Range During Reception see 389 Transfer Rate During Continuous Transmission 391 Block Diagram of Clocked Serial 1 394 Clocked Serial Interface Mode Registers CSIMO to 2 395 Clocked Serial Interface Clock Selection Registers CSICO to CSIC2 1 2 396 Clocked Serial Interface Reception Buffer Registers SIRBO to SIRB2 398 Clocked Serial Interface Reception Buffer Registers Low SIRBLO to SIRBL2 399 Clocked Serial Interface Read Only Reception Buffer Registers 5 51 2 iiit eos maf i eee nie 400 Clocked Serial Interface Read Only Reception Buffer Registers Low SIRBELO to SIBBELT iiri E EE Fn hich ee Eee Pared 401 Clocked Serial Interface Transmission Buffer Registers SOTBO to SOTB2 402 Clocked Serial Interface Transmission Buffer Registers Low SOIBLO to SOTBE2 errare oce acri aede da ee to eee eet ae dens 403 Clocked Serial Interface Initial Transmission Buffer Registers SOTBEO to SOTBE2 A sep e Ee EL E HE die 404 Clocked Serial Interface Initial Transmission Buffer Registers Low SOTBEEO to SOTBFE2 SEE ue DI det due fe oe els 405 Serial I O Shift Registers 5100 to SIO2 sse 406 Serial I O Shift Regis
30. GCCn1 is used to compare its value with the counter TMGn0 TMGn1 If the values match than an interrupt is generated and the counter is cleared Than the counter starts up counting again 1 Capture operation match ad clear Basic settings m 1 to 4 CCSGOn match and CCSG5n clear mode SWFGm disable TOGnm Capture mode for GCCnm CCSGm assign counter for GCCnm 0 TMGnO 1 TMGn1 a Example Pulse width measurement or period measurement of the TIGm input signal Setting method When using one of TOGn1 to TOGn4 pin select the corresponding counter with the TBGm bit When CCSGOn 1 TIO cannot be used When CCSG5n 1 TIGn5 cannot be used Select a count clock cycle with the CSE12 to CSE10 TMGn1 bits or CSE02 to CSE00 TMGn0 bits Select a valid TlGm edge with the IEGm1 and bit A rising edge falling edge or both edges can be selected Set an upper limit on the value of the counter in GCCn0 or GCCn5 Start timer operation by setting POWER bit and TMGOE bit or 1 bit Operation When a specified edge is detected the value of the counter is stored in GCCnm and an edge detection interrupt INTCCGnm is output When the value of GCCn0 or GCCn5 matches the value of the counter INTCCGn0 INTCCGn5 is output and the counter is cleared This operation is referred to as match and clear If a match and clear event has occurred between capture operations the CCFGy fl
31. 0 0 0 0 0 0 1 1 1 1 530 Preliminary User s Manual U15839EE1VOUMOO Chapter 15 A D Converter 3 A D conversion result register ADCR The ADCR registers is the A D conversion result register that holds the result of the A D conver sion When reading 10 bits of data of an A D conversion result from the ADCR register only the higher 10 bits are valid and the lower 6 bits are always read O This register can be read in 16 bit units Figure 15 4 A D Conversion Result Register ADCR ood d 1 0 9 8 7 6 5 4 3 2 1 0 Address tal value FEED T 3 T 3 Ue P2 une ADCR 151016 ui The bits ADCR15 to ADCR6 hold the 10 bit result of the A D conversion 4 A D conversion result register L ADCRL The ADCRL register is the A D conversion result register that holds the lower 2 bit result of the A D conversion The ADCRL register is the same as the lower byte of the ADCR register When reading all 8 bits of data of an A D conversion result from the ADCRL register only the higher 2 bits are valid and the lower 6 bits are always read 0 This register can be read in 1 bit or 8 bit units Figure 15 5 A D Conversion Result Register ADCRL 7 6 5 4 3 2 1 0 Address Initial value Ce The bits ADCR1 to ADCRO hold the lower 2 bits result of the A D conversion Preliminary User s Manual U15839EE1VOUMOO 531 Chapter 15 A D Converter 5 A D conversion result register ADCRH The ADCRH reg
32. Chip select signal output Caution In case that a port pin CSO CS3 or CS4 operates as a chip select output port it is rec ommended to plug in an external pull up resistor to that pin Preliminary User s Manual U15839EE1VOUMOO 577 Chapter 16 Port Functions 2 Setting in input output mode and control mode Port CS is set in input output mode using the port CS mode register PMCS In control mode it is set using the port CS mode control register PMCS a Port CS mode register PMCS This register can be read or written in 8 bit or 1 bit units Figure 16 33 Port CS Mode Register PMCS Address At Reset 7 6 5 4 3 2 1 0 Specifies input output mode of PCS4 pin 0 Output mode Output buffer on 1 Input mode Output buffer off Specifies input output mode of PCS3 pin 0 Output mode Output buffer on 1 Input mode Output buffer off Specifies input output mode of PCSO pin 0 Output mode Output buffer on 1 Input mode Output buffer off b Port CS mode control register PMCCS This register can be read or written in 8 bit or 1 bit units Figure 16 34 Port CS Mode Control Register PMCCS Address At Reset 7 6 5 4 3 2 1 0 Specifies operation mode of PMCCS4 pin PMCCS4 0 Input output port mode 1 CS4 Chip select output Specifies operation mode of PMCCS3 pin PMCCS4 0 Input output port mode 1 CS3 Chip select output Specifies operation mode of PMCCSO pin PMCCS4 0 Inpu
33. P5IF 5 P5PR2 P5PR1 P5PRO FFFFF124H TMGOOIC TMGOOIF TMGOOMK TMGOOPR2 TMGOOPR1 TMGOOPRO FFFFF126H TMG011C TMGO011F TMGO1MK TMGO01PR2 TMGO1PR1 TMGO01PRO FFFFF128H GCCOOIC GCCOOIF GCCOOMK GCCOOPR2 GCCOOPR1 GCCOOPRO FFFFF12AH GCCO01IC GCCO1IF GCCO1MK GCC01PR2 GCCO01PR1 GCCO01PRO FFFFF12CH GCCO2IC GCCO2IF GCCO2MK GCC02PR2 GCCO02PR1 GCCO2PRO FFFFF12EH FFFFF130H GCCOSIC GCCO0AIC GCCOSIF GCCOAIF GCCOSMK GCC0OAMK GCCOSPR2 GCCO4PR2 GCC03PR1 GCC04PR1 GCCOSPRO GCC04PRO FFFFF132H GCCO5IC GCCOSIF GCCO5MK GCCO5PR2 GCCOSPR1 GCCO5PRO FFFFF134H TMG10IC TMG10IF TMG10MK TMG10PR2 TMG10PR1 TMG10PRO FFFFF136H TMG111C TMG11IF TMG11MK TMG11PR2 TMG11PR1 TMG11PRO FFFFF138H GCC10IC GCC10IF GCC10MK GCC10PR2 GCC10PR1 GCC10PRO FFFFF13AH GCC111C GCC11IF GCC11MK GCC11PR2 GCC11PR1 GCC11PRO FFFFF13CH GCC121C GCC12IF GCC12MK GCC12PR2 GCC12PR1 GCC12PRO FFFFF13EH GCC13IC GCC13IF GCC13MK GCC13PR2 GCC13PR1 GCC13PRO FFFFF140H GCC14IC GCC14IF GCC14MK GCC14PR2 GCC14PR1 GCC14PRO FFFFF142H GCC15IC GCC15IF GCC15MK GCC15PR2 GCC15PR1 GCC15PRO FFFFF144H TMCOIC TMCOIF TMCOMK TMCOPR2 TMCOPR1 TMCOPRO FFFFF146H
34. 2 RXD1 TXD1 Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register P1 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 3 CAN module is available in the derivatives uPD703129 A and PD703129 A1 only 556 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 2 Setting in input output mode and control mode Port 1 is set in input output mode using the port 1 mode register PM1 In control mode it is set using the port 1 mode control register PMC1 a Port 1 mode register PM1 This register can be read or written in 8 bit or 1 bit units Figure 16 8 Port 1 Mode Register PM1 0 Address At Reset 7 6 5 4 3 2 1 PMin Specifies input output mode of P1n pin 7t00 n 7 to 0 0 Output mode Output buffer on E 1 Input mode Output buffer off Preliminary User s Manual U15839EE1VOUMOO 557 Chapter 16 Port Functions b Port 1 mode control register PMC1 This register can be read or written in 8 bit or 1 bit units Figure 16 9 Port 1 Mode Control Register PMC1 3 2 1 0 Address 7 6 5 4 ii FFFFF440H Bit Position Bit Name Function Specifies operation mode of P17 pin 0 Input
35. 271 Successive approximation 523 Successive approximation register 524 SYNCHIONIZE LC 328 System MalfUnCtloni uu ikea bee ERE ET ERE Ee Meg S m er RR 583 system reglster oer ekle qe ase egeret pede he iege e 56 System registers 0 0 hh hne 56 58 SYSTEM OSC La C EU PEE 583 T tag clear function 155 TextipOInter 2 uev tei ob tenet en do eR tn e ce aed E ak ee en v ed 57 Time base status 320 Hnlgom uc 271 Timer C control register O 278 Timer C control register 1 liiis rn 280 Timer D counter Register 0 00 cece m ne 298 Timer Dn compare register 299 Timer Dn control register lt resi oera 301 Timer G capture compare registers with external PWW output function 312 Timer Gn 16 bit counter registers 310 Timer Gn capture compare registers of the 2 counters 311 Timer Gn Channel Mode Register 316 Timer Gn Mode Register
36. 8 levels of priority order are specified for each interrupt Interrupt Priority Specification Bit Specifies level 0 highest Specifies level 1 Specifies level 2 xxPR2 to xxPRO Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 lowest Remark Identification name of each peripheral unit WT TMD TMG GCC AD MAC FC CSI UART DMA The address and bit of each interrupt control register are shown in the following Table 8 2 Addresses and Bits of Interrupt Control Registers on page 217 216 Preliminary User s Manual U15839EE1VOUMOO Address FFFFF110H Table 8 2 Register WTIC Chapter 8 Interrupt Exception Processing Function w Addresses and Bits of Interrupt Control Registers 1 2 WTIF WTMK WTPR2 WTPR 1 WTPRO FFFFF112H TMDOIC TMDOIF TMDOMK TMDOPR2 TMDOPR1 TMDOPRO FFFFF114H TMD1IC TMD1IF TMD1MK TMD1PR2 TMD1PR1 TMD1PRO FFFFF116H WTIIC WTIIF WTIMK WTIPR2 WTIPR1 WTIPRO FFFFF118H POIC POIF POMK POPR2 POPR1 POPRO FFFFF11AH P1IC P1IF P1MK P1PR2 P1PR1 P1PRO FFFFF11CH P2IC P2IF P2MK P2PR2 P2PR1 P2PRO FFFFF11EH PSIF PSMK P3PR2 P3PR1 PSPRO FFFFF120H P4IC P4IF PAMK PAPR2 1 P4PRO FFFFF122H
37. P20 P21 P22 P23 P24 P25 P26 P27 510 500 SCKO Port 2 SH 8 bit input output port 501 SCK1 RXDO TXDO P30 P31 P32 P33 P34 P35 TIGOO INTPOO TIGO1 TOGO1 Port 3 TIGO2 TOGO2 6 bit input output port TIGOS TOGOS TIGO4 TOGO04 TIGO5 INTPO5 P40 P41 P42 P43 P44 P45 Note CAN module and CAN module 4 are available in the derivatives PD703129 A and TIG10 INTP10 TIG11 TOG11 Port 4 TIG12 TOG12 6 bit input output port TIG13 TOG13 TIG14 TOG14 uPD703129 A1 only TIG15 INTP15 Preliminary Users Manual U15839EE1VOUMOO 33 34 Chapter 2 Pin Functions Table 2 1 Port Pins 2 3 Function Port 5 7 bit input output port Alternate FCRXD4Note FCTXD4Note INTP4 INTP5 TIO INTP20 TH INTP21 TOO Port 6 8 bit input output port NMI INTPO INTP1 INTP2 INTP3 512 502 SCK2 Port 7 8 bit input port ANIO ANI2 ANI4 ANI5 ANI6 ANI7 P80 P81 P82 P83 Port 8 4 bit input port ANI8 9 ANI10 ANI 1 P90 P91 P92 P93 P94 P95 P96 P97 Note uPD703129 A1 only Port 9 8 bit input output port CAN module and CAN module 4 are available in the derivatives PD703129 A and Prelimi
38. PCT4 PCT1 PCTO HOLD HOLD HOLD HOLD operate operate PCMO HOLD HOLD HOLD HOLD operate Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Remarks 1 N A This configuration is not available 2 Input data is not sampled 3 1 During output input 4 Hi Z High Impedance Preliminary User s Manual U15839EE1VOUMOO 39 Chapter 2 Pin Functions 2 2 Description of Pin Functions 1 P10 to P17 Port 1 Input output Port 1 is an 8 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in control mode P10 to P17 operate as the serial interface UART1 FCAN1 FCAN2 FCAN3NOTE input output An operation mode of port or control mode can be selected for each bit and specified by the port 1 mode control register PMC1 a Port mode P10 to P17 can be set to input or output in 1 bit units using the port 1 mode register PM1 b Control mode P10 to P17 can be set to port or control mode in 1 bit units using PMC1 c CTXD1 CTXD2 CTXD3 Transmit data for controller area network Output This pin outputs FCAN serial transmit data d CRXD1 CRXD2 CRXD3 Receive data for controller area network Input This pin inputs FCAN serial receive data e TXD1 Transmit data Output This pin output serial transmit data of UAR
39. PMOn Specifies input output mode of P9n pin 7100 n 7to0 0 Output mode Output buffer on i 1 Input mode Output buffer off 574 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 10 Port AH Port AH is an 8 bit input output port in which input or output can be specified in 1 bit units After reset the port AH pins operate as an address bus to address external memories respectively peripherals Each port bit can be independently configured to port input port output or peripheral functionete 1 This register can be read in 1 bit and 8 bit units Figure 16 29 Port AH PAH Address At Reset PAHn n 7 to 0 Input output port Remark In Input Mode When the PAH register is read the pin levels at that time are read Writing to the PAH register writes the values to that register This does not affect the input pins In Output Mode When the PAH register is read the values of PAH are read Writing to the PAH register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as an address bus Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register PAH is 00H Due to the input mode of the port aft
40. SOTB2 507815 807814807813 507812 507811 507810 8089 SOTB 0 7 SOTB6 SOTBS SOTB4 SOTB3 80782 80781 SOTBO FFFF FD84H 0000H SOTB15 to Cautions 1 Access the SOTBn register only when the 16 bit data length is set CCL bit of CSIMn register 1 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOT bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guaranteed 402 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 8 Clocked serial interface transmission buffer registers Low SOTBLO to SOTBL2 The SOTBLn register is an 8 bit buffer register that stores transmit data n 0 to 2 When the transmission reception mode is set TRMD bit of CSIMn register 1 the transmission operation is started by writing data to the SOTBLn register These registers can be read written in 8 bit units The SOTBLn register is the same as the lower bytes of the SOTBn register Figure 13 29 Clocked Serial Interface Transmission Buffer Registers Low SOTBLO to SOTBL2 Initial value SOTBLO SOTB7 SOTBO FFFFFDO4H 7 6 5 4 3 2 1 0 Address SOTB7 to SOTBO Store transmit data Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 per
41. be specified by data wait control registers 0 and 1 DWCO DWC1 in programming Just after system reset all blocks have 7 data wait states inserted These registers can be read written in 16 bit units 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Wn DWCO DW32 DW31 DW30 DWz2 DW21 DW20 DW12 DW11 DWo DWO01 DWOO FFFFF484H 7777H CS3 CS2 CS1 50 15 14 13 12 11 10 9 7 6 5 4 3 2 1 Address is DWC1 FFFFF486H 7777H o o pep L L L L CS7 CS6 CS5 CS4 14 12 Data Wait 10 to 8 Specifies the number of wait states inserted in the CSn area 6 to 4 54570 Number of Wait States Inserted in CSn Space No wait states inserted Cautions 1 The internal Cache and the internal RAM area are not subject to programmable waits and ordinarily wait access is carried out The internal peripheral I O area is also not subject to programmable wait states with wait control performed only by each peripheral function 2 Inthe following cases the settings of registers DWCO and DWC1 are invalid wait control is performed by each memory controller Page ROM on page access 3 Write to the DWCO and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than that for this ini tialization routine u
42. 12 channels wo 10 TONO x10 o0 z gt 22 lt lt gegee2gggegeg o oooooooooc z 4 CO DOD 2 Bootstrap Loader Sub Oscillator XT1 XT2 Oscillator and Clock Generator xi with Spread 2 Spectrum PLL RESET PLL RESOUT Watch Timer Watchdog Timer CSI02 Zw JE BRG1 FCRXD3 FCTXD3 FCRXD4 FCTXD4 are available only in the derivatives uPD703129 A and UPD703129 A1 Preliminary User s Manual U15839EE1VOUMOO 29 Chapter 1 Introduction 1 6 1 On chip units 1 2 3 4 5 6 7 30 CPU The CPU uses five stage pipeline control to enable single clock execution of address calculations arithmetic logic operations data transfers and almost all other instruction processing Other dedicated on chip hardware such as the multiplier 16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits and the barrel shifter 32 bits help accelerate processing of complex instructions Bus control unit BCU BCU starts a required external bus cycle based on the physical address obtained by the CPU When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request the BCU generates a prefetch address and prefetches the instruction code The prefetched instruction code is stored in an instructi
43. 3 Overrun INTSER5n BRG Remark 0 1 366 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 2 3 Control registers 1 Asynchronous serial interface mode registers ASIMO ASIM1 The ASIMn register is an 8 bit register that controls the UART5n transfer operation This register can be read written in 8 bit or 1 bit units n O 1 Figure 13 2 Asynchronous Serial Interface Mode Registers ASIMO ASIM1 1 3 Initial value 7 6 5 4 3 2 1 0 Address Enables disables clock operation 0 Disable clock operation reset internal circuit asynchronously 1 Enable clock operation UART5n operation clock control and asynchronous reset of the internal circuit are performed with the Power bit When the Power bit is set to 0 the UART5n 7 Power operation clock stops fixed to low level and an asynchronous reset is applied to internal UART5n latch The TXDn pin output is low level when the Power bit 0 and high level when the Power bit 1 Therefore perform Power setting in combination with port mode regis ter PM1 PM2 PM6 so as to avoid malfunction on the other side at start up Set the port to the output mode after setting the Power bit to 1 Input from the RXDn pin is fixed to high level with Power bit 0 Enables disables transfer 0 Disable transfer Perform synchronized reset of transfer circuit 1 Enable transfer Cautions 1 Set the TXE bit to 1 after settin
44. 426 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 1 Features Active support of extended format ISO 11898 former CAN specification version 2 0B active sup porting transmission and reception of standard and extended frame format messages 2 or 4Note CAN modules CAN bus speed up to 1 Mbit per second Direct message storage for minimum CPU burden Configurable number of message buffers per CAN module 32 message buffers in total Mask option for receive messages BasicCAN channels 4 masks per CAN module each mask can be assigned to each message Buffered reception FIFO Message buffers can be redefined in normal operation mode FCAN interface and CPU share common RAM area Interrupt on receive transmit and error condition Time stamp and global time system function Two power save modes SLEEP mode wake up at CAN bus activity STOP mode no wake up at CAN bus activity Diagnostic features Readable error counters CAN bus status information register Receive only mode e g used for automatic bit rate detection Bus error cause information Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Preliminary User s Manual U15839EE1VOUMOO 427 Chapter 14 FCAN Interface Function 14 2 Outline of the FCAN System 14 2 1 General The FCAN Full CAN system of the V850E CA2 supports 2 or 4Nete independent CAN modules CAN mod
45. Clock V V RXD5n In Q Internal signal A In Q Internal signal B Match detect Figure 13 15 Timing of RXD5n Signal Judged as Noise Clock RXD5n input A A A A Match Mismatch Match Mismatch judged as noise judged as noise Remark 0 1 Preliminary User s Manual U15839EE1VOUMOO 383 Chapter 13 Serial Interface Function 13 2 6 Dedicated baud rate generators BRG of UART5n n 0 1 A dedicated baud rate generator which consists of a source clock selector and an 8 bit programmable counter generates serial clocks during transmission reception at UART5n n 0 1 The dedicated baud rate generator output can be selected as the serial clock for each channel Separate 8 bit counters exist for transmission and for reception 1 Baud rate generator configuration Figure 13 16 Baud Rate Generator BRG Configuration of UART5n n 0 1 CAE O fecu 2 08 7 fecuc 4 fpc 8 feci 16 9 fpc 32 fecu 64 0 fpc 128 5 7 fpc 256 CAE and TXE or RXE 8 bit counter Selector fei fecu 512 f A024 PERS Match detector Baud rate fecix 2048 CKSR5n TPS3 to TPSO BRGC5n MDL7 to MDLO Remark 0 1 Basic clock Clock When Power bit 1 in the ASIMn register the clock selected according to the TPS3 to TPSO bits of the CKSRm register is supplied to the transmission reception unit This c
46. Output This is a strobe signal that shows that the executing bus cycle is a read cycle for SRAM external ROM or external peripheral I O It is inactive in an idle state TI PCMO Port CM Input output Port CM is a 1 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in control mode it operates as control signal output when memory is accessed externally An operation mode of port or control mode can be selected for each bit and specified by the port CM code control register PMCCM a Port mode PCMO can be set to input or output in 1 bit units using the port CM mode register PMCM b Control mode PCMO can be used as WAIT by using PMCCM c WAIT Wait Input This control signal input pin which inserts a data wait in a bus cycle If the setup or hold time is not secured in the sampling timing wait insertion may not be performed Preliminary User s Manual U15839EE1VOUMOO 13 14 15 16 17 18 19 20 21 22 Chapter 2 Pin Functions ANIOO to ANI11 Analog input Input These are analog input pins to the A D converter MODEO to MODE2 Mode Input These are the input pins that specify the operation mode Operation modes are broadly divided into normal operation modes and flash memory programming mode The operation mode is deter mined by sampling the status of each of pins MODEO to MODE2 on a reset Fix the
47. Specifies the bit sampling 0 Sample receive data one time at sampling point 1 Sample receive data three times and take majority decision at sampling point Specifies the synchronization jump width Synchronization Jump Width Specifies the sampling point position Sampling Point Position SPTR3 SPTR2 SPTRO SPTR p 1 TQ Setting prohibited SPTR4 to SPTRO 0 0 0 Other than above Setting prohibited Note The register address is calculated according to the following formula effective address PP BASE address offset 506 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 42 CAN 1 to 4 Synchronization Control Registers C1SYNC to C4SYNC 2 2 Specifies the number of TQ per bit Data Bit Time DBTR4 DBTR3 DBTR2 DBTR1 DBTRO DBTR q 1 TQ 0 0 0 0 0 Setting prohibited DBTR4 to DBTRO 1 0 0 Other than above Setting prohibited Remarks 1 CPU can read the CxSYNC register at any time x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A Writing to the register is only possible when the CAN module is set to INIT mode For setting the DBTR and SPTR bits some rules must be observed otherwise the CAN module will malfunction for details refer to chapter 14 4 Operating Consi
48. sse 188 Single Transfer Example 4 nnne 188 Single Step Transfer Example 1 189 Single Step Transfer Example 2 ssssssssssssseeeeee 189 Line Transfer Example 1 190 Line Transfer Example DELLE KAEA REII 190 Line Transfer Example 191 Line Transfer Example 4 sese enemies 191 Block Transfer Example sessi 192 Example of Forcible Interruption of DMA 195 DMA Transfer Forcible Termination Example 1 196 DMA Transfer Forcible Termination Example 2 197 Example of Non Maskable Interrupt Request Acknowledgement Operation 1 2 204 Processing Configuration of Non Maskable 206 RETI Instruction Processing eene nennen 207 Non maskable Interrupt Status Flag 208 Interrupt Mode Register 1 nnne 208 Maskable Interrupt Processing seen nennen 210 RETI Instruction Processing a iniia a
49. 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 8 25 illustrates the restore processing from an exception trap Figure 8 25 Restore Processing from Exception Trap DBRET instruction Jump to address of restored PC Preliminary User s Manual U15839EE1VOUMOO 231 Chapter 8 Interrupt Exception Processing Function 8 6 2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction When the debug trap is generated the CPU performs the following processing 1 Operation When the debug trap is generated the CPU performs the following processing transfers control to the debug monitor routine and shifts to debug mode Saves the restored PC to DBPC 1 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the debug trap to the PC and transfers control Figure 8 26 illustrates the processing of the debug trap Figure 8 26 Debug Trap Processing DBTRAP instruction restored PC PSW 1 CPU processing 1 00000060H Exception processing 232 Preliminary User s Manual U15839EE1VOUMOO 2 Chapter8 Interrupt Exception Processing Function Restore Recovery from a debug trap is carried out by the DBRET instruction By executing the DBRET instruction the
50. C3DINF 0000H 101 Address xxxxn10DEH Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 18 18 Function Register Name Note 2 CANS synchronization control register C3SYNC Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value 0218H xxxxn1 100H CANA address mask register LO Note 2 C4MASKLO Undefined xxxxn11C2H CANA address mask register Note 2 C4MASKHO Undefined xxxxn11C4H CANA address mask register L1 Note 2 C4MASKL1 Undefined xxxxn11C6H address mask register H1 Note 2 C4MASKH1 Undefined xxxxn11C8H CAN4 address mask register L2 Note 2 C4MASKL2 Undefined xxxxn11CAH CAN4 address mask register H2 Note 2 C4MASKH2 Undefined xxxxn11CCH CANA address mask register L3 Nete 2 C4MASKL3 Undefined xxxxn11CEH CANA address mask register Note 2 C4MASKH3 Undefined xxxxn11DOH CANA control register Note 1 2 C4CTRL 0101H xxxxn11D2H definition register Note 1 2 C4DEF 0000H xxxxn11D4H information register Note 2 C4LAST 00FFH xxxxn11D6H CAN4 error counter register Note 2 C4ERC 0000H xxxxn11D8H interrupt enable register Note 1 2 CAIE 0000H xxxxn11DAH CAN4 bus active register Note 2 C4BA 00FFH xxxxn11DCH CANA bit rate prescaler r
51. Counter stop can be set by software These registers can be read in 16 bit units Figure 10 25 Timer Gn Counter 0 Value Registers TMGnO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addes dial value Figure 10 26 Timer Gn Counter 1 Value Registers TMGn1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address dial value 310 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 2 Timer Gn capture compare registers of the 2 counters GCCn0 GCCn5 The GCCn0 GCCn5 registers are 16 bit capture compare registers of Timer Gn These registers are fixed assigned to the counter registers TMGn0 and TMGn 1 In the capture register mode GCCn0 GCCn5 captures the TMGnO TMGn1 count value if an edge is detected at Pin TIGnO TIGn5 In the compare register mode GCCn0 GCCn5 detects match with TMGnO TMGn1 and clears the assigned Timebase So this match and clear mode is used to reduce the number of valid bits of the counter TMGn0 TMGn1 These registers can be read written in 16 bit units Caution If in Compare Mode write to this registers before POWER and ENFGx bit x 0 1 are 1 at the same time Figure 10 27 Timer Gn counter TMGn0 assigned Capture Compare Register GCCn0 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 1 value Remark This register is assigned fix to timebase TMGnoO Figure 10 28 Timer Gn counter TMGn1 assigned Capture Compare Register GCCn5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address a
52. Error delimiter Error bus off oO O O O O O O O OF o Extended format ID section s ay Se Ae CO OF CO CO O OGO GO Glo oO GO oO O O O O O O O 9 O O ol o ol of ol ol o of of of of of oO oOo 0 Others than above Reserved Suspend mode Remark The CACT4 to CACTO bits reflect the status of the CAN protocol layer Note The register address is calculated according to the following formula effective address PP_BASE address offset Preliminary User s Manual U15839EE1VOUMOO 501 Chapter 14 FCAN Interface Function Figure 14 39 CAN 1 to 4 Bus Activity Registers C1BA to C4BA 2 2 Indicates the message buffer which is either waiting to be transmitted or in transmis sion progress TMNO7 to TMNOO Number of Transmit Message Buffer TMNO7 to 0 to 31 Current transmit message buffer waiting for transmission TMNOO or in transmission progress 32 to 254 Reserved not possible No message waiting for transmission or in transmission progress 255 502 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 8 CAN 1 to 4 bit rate prescaler registers C1BRP to CABRP The CxBRP registers specify the bit rate prescaler and CAN bus speed of the corresponding CAN module x x 1 to 4 for the derivat
53. Figure 9 12 Sub Watch mode release by Watchdog reset NMI INT Sub Watch mode setting Main Oscillation circuit System clock Main OSC STOP state NMI or INT input _ Stabilization counter I 1 Main Oscillation circuit stop count time I pl a a 1 After oscillator stabilization time has passed CPU starts operation Remark Before entering the SUB WATCH mode the SSCG and the PLL are switched off by hard ware After the SUB WATCH mode has been released the PLL can be switched on by soft ware again once However the start up of the PLL causes always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a fast response when waking up from SUB WATCH mode the PLL should not be re enabled after waking up as this causes again the delay In this case time relevant reactions of the CPU should be done first before re enabling the PLL 264 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 4 8 Software STOP mode In this mode the CPU clock is stopped including the clock generators oscillator SSCG and PLL syn thesizer resulting in stop of the entire system for ultra low power consumption the only consumed is device leakage current However if SOSTP bit 1 the Sub oscillator and Watchdog timer keeps operating increasing ST
54. Remarks 1 TMDn value when overwritten 2 q CMDn value when overwritten 3 0 1 300 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 2 4 Control register 1 Timer Dn control register TMCDn n 0 1 The TMCDn register controls the operation of Timer Dn n 0 1 This register can be read written in 8 bit or 1 bit units Figure 10 22 Timer Dn Control Register TMCDn n 0 1 7 6 4 3 2 1 0 Address value Bit Position Bit Name Function Selects the TMDn count clock n 0 1 50 Count Clock 2 fpcik 4 fpoLk 8 16 32 64 128 foci 256 Caution Do not change the CS2 to CSO bits during timer operation If they are to be changed they must be changed after setting the CE bit to 0 If the CS2 to CSO bits are overwritten during timer operation the operation is not guaranteed Count Enable Controls the operation of TMDn n 0 1 0 Disable count timer stopped at OOOOH and does not operate 1 Perform count operation Caution CE bit is not cleared even if a match is detected by the compare operation To stop the count operation clear the CE bit Count Action Enable Controls the internal count clock 0 Asynchronously reset entire TMDn unit Stop clock supply to TMDn unit 1 Supply clock to TMDn unit n 0 1 Cautions 1 When CAE 0 is set the TMDn unit c
55. Similar delays are added also when a transition is made from the active to inactive level So a relative pulse width is guaranteed Figure 10 40 Timing of Output delay operation a i a oC Eu gD ye oD TMGCrO 0000H 0003H TOGn1 TOGn2 TOGn3 TOGn4 In this case the count clock is set to fpc K 2 Preliminary User s Manual U15839EE1VOUMOO 321 Chapter 10 Timer 10 3 6 Explanation of basic operation 1 Overview of the mode settings The Timer Gn includes 2 channels of 16 bit counters TMGn0 TMGn1 which can operate as independently timebases TMGnO TMGn1 can be set by CCSGO bit CCSG5 bit in the following modes free run mode match and clear mode When a timer output TOGnm or INTCCGnm interrupt is used one of the two counters can be selected by setting the TBGm bit m 1 to 4 of the TMGCMHn register The tables below indicate the interrupt output and timer output states dependent on the register setting values Table 10 5 Interrupt output and timer output states dependent on the register setting values Register setting value State of each output pin CCSGOn TBGm SWFGm CCSGm INTTMGnO INTCCGnO INTCCGnm Tim edge detection 0 CMPGm match Tied ae Overflow TIO edge eve Free run interrupt detection edge mode detection PWM CMPGm match free run Tlm edge detection Tied to inactive CMPGm match Overflow CMPGO level Match and Note 1 Note 2
56. a Enter sleep mode Set SLEEP bit 1 CxCTRL register or lt b gt Enter initialisation mode Set INIT bit 1 CxCTRL register and wait for ISTAT bit 1 Disable event processing Clear EVM flag CGST register Stop the CAN global time system counter Clear the TSM flag CGST register Stop the global CAN operation Clear GOM flag CGST register Switch off the CAN clock Set CSTP bit CSTOP register If the sequence is not observed any active CAN module may cause malfunction on the corresponding CAN bus Preliminary User s Manual U15839EE1VOUMOO 521 MEMO 522 Preliminary User s Manual U15839EE1VOUMOO Chapter 15 A D Converter 15 1 Features e 10 bit resolution on chip A D converter e Analog inputs 12 channels Standby function Current cut between AVpp AGND if A D conversion is stopped Current cut between AVper AGND if A D conversion is stopped A D conversion trigger modes A D trigger mode e Successive approximation technique Preliminary User s Manual U15839EE1VOUMOO 523 Chapter 15 A D Converter 15 2 Configuration The A D converter which employs a successive approximation technique performs A D conversion operation using A D converter mode register ADM A D converter register ADS and A D conversion result registers ADCRL ADCRH The A D converter consists of the following hardware Table 15 1 A D Converter Configuration Item Configuration Analog input 12 channels ANIO to
57. ddddddd adr bit 3 rrrrr1111 SR regID GR reg2 regID EIPSW FEPSW 11RRRRR reg2 regID 000000000 0100000 Note 7 PSW rrrrrilil 11RRRRR 000000000 1000000 regID reg2 GR reg2 SR regID EIPC lt PC 4 Restored PC EIPSW lt PSW ECR EICC lt Interrupt code PSW EP lt 1 PSW ID lt 1 PC lt 00000040H vector 00H to OFH 00000050H vector 10H to 1FH if PSW EP 1 then PC EIPC PSW EIPSW else if PSW NP 1 then PC lt FEPC PSW FEPSW else PC EIPC PSW EIPSW 000001111 vector 000000010 0000000 Special 000001111 1100000 000000010 1000000 000001111 1100000 000000010 0100000 Notes 1 ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Stops Only the lower half word data is valid ddddddddddddddddddddd is the higher 21 bits of dip22 ddddddad is the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification 598 Preliminary User s Manual U15839EE1VOUMOO Appendix A List of Instruction Sets Table A 6 Instruction Set
58. direction 67 Chapter 3 CPU Function 3 5 Memory Map The V850E CA2 reserves areas as shown in Figure 3 9 1 For pPD703128 Figure 3 9 Memory Map uPD703128 A Single chip mode Internal peripheral I O area kbytes x3FF FOOOH ot x3FF EFFFH 4 16 Kbytes x3FF BOOOH i x3FF AFFFH UY Internal RAM area 12 Kbytes x3FF 8000H x3FF 7FFFH 64 Mbytes External memory area x000 0000H 68 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 2 For PD703129 Figure 3 10 Memory Map uPD703129 A uPD703129 A1 Single chip mode SFP Internal peripheral 4 Kbytes x3FF F000H area x3FF EFFFH td 12 Kbytes x3FF x3FF BFFFH L 4 Internal RAM area 16 Kbytes x3FF 8000H x3FF 7FFFH OP 64 Mbytes External memory area x000 0000H Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 5 1 Area 1 External ROM area 70 The following areas can be used as external memory area a pPD703128 pPD703129 x000 0000H to x3FF 7FFFH Access to the external memory area uses the chip select signal assigned to each memory block which is carried out in the CS unit set by chip area selection control registers 0 and 1 CSCO CSC1 Furthermore the internal ROM internal RAM and internal peripheral I O areas cannot be accessed as external memory areas b Interrupt exception table The V850E CA2 i
59. 1 A D converter mode register ADM The ADM register is an 8 bit register that enables A D conversion and the conversion time It can be read or written in 1 bit or 8 bit units However writing to the ADM register during A D conversion operation interrupts the conversion operation and the data is lost The conversion operation restarts from the beginning If the ADCS bit is cleared 0 during conversion operation the conversion is aborted and the conversion operation is stopped While the ADCS bit is cleared 0 all DC current passes are cut between AVpp AVss and between AVpe_r Figure 15 2 A D Converter Mode Register ADM 7 6 5 4 3 2 1 0 Address Initial value Specifies enabling or disabling A D conversion 0 Conversion operation stop 1 Conversion operation enable Specifies the conversion time Conversion Clocks Conversion Time us 20 MHz fpgi 2 16 MHz 84 96 108 120 144 168 192 216 Setting prohibited Remark fpc Internal peripheral clock Notes 1 The bits FRO FR1 FR2 and must not be changed while ADCS bit is set 1 2 Conversion time actual A D conversion time Always set the time to 5 us lt Conversion time lt 12 us Caution Be sure not to change the setting of bits 0 1 and 6 from their reset value 0 If these bits are set 1 the operation is not guaranteed 528 Preliminary User s Manual U15839EE1VOUMO
60. 2 Generate transmission completion interrupt INTSTn 3 Read ASIFn register confirm that TXBF bit 0 Write data n lt 4 gt Generate start bit Start data n 1 transmission lt lt Transmission in progress gt gt lt 5 gt Generate transmission completion interrupt INTSTn lt 6 gt Read ASIFn register confirm that TXSF bit 1 There is no write data lt 7 gt Generate start bit Start data n transmission lt lt Transmission in progress gt gt lt 8 gt Generate transmission completion interrupt INTSTn lt 9 gt Read ASIFn register confirm that TXSF bit 0 Clear 0 the Power bit or TXE bit of ASIMn Initialize internal circuits register Preliminary User s Manual U15839EE1VOUMOO 379 4 380 Chapter 13 Serial Interface Function Receive operation An awaiting reception state is set by setting Power bit to 1 in the ASIMn register and then setting RXE bit to 1 in the ASIMn register To start a receive operation detects a start bit first The start bit is detected by sampling RXD5n pin When the receive operation begins serial data is stored sequential in the reception shift register according to the baud rate that was set A reception completion interrupt INTSRn is generated each time the reception of one frame of data is completed Normally the receive data is transferred from the reception buffer register RXBn to memory by this interrupt servicing n 0 1 a
61. 5 467 14 3 4 CAN message buffer 472 14 3 5 CAN Module 5 485 14 4 Operating Considerations 509 14 4 1 Rules to be observed for correct baud rate 509 14 4 2 Example for baudrate setting of CAN 510 14 4 3 Ensuring data 5 512 14 4 4 Operating states of the CAN modules 514 14 4 5 Initialisation 515 Chapter 15 A D 523 15 1 Features Ad eee da EUR 523 15 2 Configuration coe Soe a eee Se ates Ux e ee ER 524 15 3 Control Registers 22 2o le rire eee ee damas 527 15 3 1 Register format of A D Converter Control 527 15 3 2 Input voltage and conversion results 535 15 4 Interrupt Request eroten en elo Re RAD rs xm por REG 536 15 5 A D Converter Operation 537 15 5 1 A D converter basic operation 537 15 5 2 Operation modes
62. Chapter 14 FCAN Interface Function 4 CAN Module Registers Section The appropriate register section of each CAN module is shown in Table 14 5 for CAN module 1 in Table 14 6 Relative Addresses of CAN Module 2 Registers on page 435 for CAN module 2 in Table 14 7 Relative Addresses of CAN Module 3Note1 Registers on page 436 for CAN mod ule 3 and in Table 14 8 Relative Addresses of CAN Module 4Note1 Registers on page 437 for CAN module 4 Address OffsetNote2 Table 14 5 Relative Addresses of CAN Module 1 Registers Access Type Comment 1 bit 8 bits 1MASKLO CAN1 mask 0 register L lower half word 1 CAN1 mask 0 register upper half word 1MASKL1 CAN1 mask 1 register L lower half word 1MASKH1 CAN1 mask 1 register upper half word 1MASKL2 CAN1 mask 2 register L lower half word 1MASKH2 CAN1 mask 2 register upper half word 1 CAN1 mask register L lower half word 1 CAN1 mask register upper half word C1CTRL CAN1 control register bit set clear function C1DEF CAN1 definition register bit set clear function C1LAST information register read only C1ERC CAN1 error counter register read only 1 CANI interrupt enable register bit set clear function C1BA CAN1 bus activity register bit set clear function d S d d D 5 D Z 2 CAN
63. Figure 5 1 Example of Connection to SRAM a When data bus width is 16 bits A1 to A17 D1 to D16 A1 to A17 DO to D15 CSn RD V850E CA2 2 Mbit SRAM 256 Kwords x 16 bits b When data bus width is 8 bits DO to D7 d 1 Mbit SRAM 128 Kwords x 8 bits D8 to D15 K V850E CA2 1 Mbit SRAM 128 Kwords x 8 bits Remark CS0 CS3 and CS4 138 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function 5 1 3 SRAM external ROM external I O access Figure 5 2 SRAM External ROM External I O Access Timing 1 6 T1 a During read T2 T1 TW T2 System CLK Il VI VI VE VI VI MJ XML to A23 output Address CSn output RD output UWR output LWR output DO to D15 I O Data Data WAIT input Remarks 1 The circles indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CSO CS3 and CS4 Preliminary User s Manual U15839EE1VOUMOO 139 Chapter 5 Memory Access Control Function Figure 5 2 SRAM External ROM External l O Access Timing 2 6 b During read address setup wait idle state insertion System CLK to A23 output TASW T1 T2 TI ASS AA dur Xr a L CSn output RD output UWR output LWR output DO to
64. Instruction Group Appendix A List of Instruction Sets Table A 6 Instruction Set List 2 7 Operand Opcode Operation Load store reg2 disp16 regt rrrrri1110 11RRRRR ddddddddd Note 3 adr lt GR reg1 sign extend disp16 Store memory adr GR reg2 Halfword reg2 disp16 regt rrrrri1110 11RRRRR ddddddddd 1 Note 3 adr lt GR reg1 sign extend disp16 Store memory adr GR reg2 Word Arithmetic operation regi reg2 rrrrr0000 OORRRRR GR reg2 GR reg1 imm5 reg2 rrrrr0100 GR reg2 lt sign extend imm5 imm16 regt reg2 rrrrri1100 10RRRRR fs Es iE GR reg2 GR reg1 imm16 075 imm16 regt reg2 rrrrri1100 01RRRRR JULII Mug GR reg2 lt GR reg1 sign extend imm16 disp16 reg1 reg2 rrrrri1110 01RRRRR ddddddddd Note 3 adr GR reg1 sign extend disp16 GR reg2 sign extend Load memory adr Halfword disp16 reg1 reg2 rrrrri1110 01RRRRR ddddddddd ddddddl Note 3 adr GR reg1 sign extend disp16 GR reg2 Load memory adr Word reg2 disp7 ep rrrrr0111 ddddddd adr lt ep zero extend disp7 Store memory adr GR reg2 Byte regi reg2 rrrrr001110 RRRRR GR reg2 lt GR reg2 GR regt imm5 reg2 rrrrrO10010i GR reg2 lt GR r
65. Message identifier register lower half word m x 20H 1 M_IDLm Message identifier register m x 20H M_IDHm upper half word m x 20H 81 M_CONFm Message configuration register m x 20H 81 SC_STATm Message set clear status register m x 20H 81 M_STATm Message status register m x 20H 81 to Reserved m x 20H 81FH Notes 1 number of CAN message buffer m 00 to 31 2 The address of a message buffer entry is calculated according to the following formula effective address PP BASE address offset 3 The V850E CA2 Jupiter device does not contain an event processor Therefore the mes sage event bytes are reserved However these registers can be used for storing user data in case that the event processing is disabled explicitly by clearing the bit EVM in the register CAN global status register and by clearing the bit ERQ in the Message status register Preliminary User s Manual U15839EE1VOUMOO 431 Chapter 14 FCAN Interface Function 2 Interrupt Pending Registers Section The layout of the interrupt pending register section is shown in Table 14 3 Table 14 3 Relative Addresses of CAN Interrupt Pending Registers Access Type Address Not Offset ote R W 1 bit 8 bits Comment CCINTP CANinterrupt pending register CAN global interrupt pending CGINTP register bit set function only
66. The edge detection circuit has a noise elimination function This function regards a pulse not wider than 1 count clock period as a noise and does not detect it as an edge a pulse not shorter than 2 count clock periods is detected normally as an edge a pulse wider than 1 count clock period but shorter than 2 count clock periods may be detected as an edge or may be eliminated as noise depending on the timing This is because the count up signal of the counter is used for sampling timing The upper figure below shows the timing chart for performing edge detection The lower figure below shows the timing chart for not performing edge detection Basic settings x 0 1 and y Oto 5 Remark Count clock fpc 4 detection of both edges Figure 10 58 Timing of Edge detection noise elimination Timing chart for performing edge detection UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUL fcouNTx I TMGno TMGn1 TIGny INTCCGny GCCny t 4 t 6 lt Timing chart for noise elimination gt fex _ foountx In MM Im TMGn0 TMGn1 t 11 1 2 1 3 1 4 1 5 1 6 1 7 ne TIGny INTCCGny GCCny 346 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 3 10 Precautions Timer Gn 1 2 3 When POWER bit of TMGMHn register is set The rew
67. Undefined Xxxxn248H CAN message data register 180 M DATA180 Undefined xxxxn249H CAN message data register 181 M DATA181 Undefined Xxxxn24AH CAN message data register 182 M DATA182 Undefined xxxxn24BH CAN message data register 183 M DATA183 Undefined Xxxxn24CH CAN message data register 184 M DATA184 Undefined xxxxn24DH CAN message data register 185 M DATA185 Undefined xxxxn24EH CAN message data register 186 M DATA186 Undefined xxxxn24FH CAN message data register 187 M DATA187 Undefined Xxxxn250H CAN message ID register L18 Preliminary User s Manual U15839EE1VOUMOO M IDL18 Undefined 93 Address xxxxn252H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 10 18 Function Register Name CAN message ID register H18 M IDH18 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn254H CAN message configuration register 18 M CONF18 Undefined xxxxn255H CAN message status register 18 M STAT18 Undefined xxxxn256H CAN status set cancel register 18 SC STAT18 0000H Xxxxn260H CAN message event pointer 260 M EVT260 Undefined xxxxn261H CAN message event pointer 261 M EVT261 Undefined Xxxxn262H CAN message event pointer 262
68. Undefined xxxxn075H CAN message status register 03 M STATOS3 Undefined xxxxn076H CAN status set cancel register 03 SC STATOS 0000H Xxxxn080H CAN message event pointer 040 M_EVT040 Undefined xxxxn081H 86 CAN message event pointer 041 M_EVT041 Preliminary User s Manual U15839EE1VOUMOO Undefined Address Xxxxn082H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 3 18 Function Register Name CAN message event pointer 042 M_EVT042 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined Xxxxn083H CAN message event pointer 043 M EVTO43 Undefined Xxxxn084H CAN message data length register 04 M DLCO4 Undefined Xxxxn085H CAN message control register 04 M CTRLO4 Undefined Xxxxn086H CAN message time stamp register 04 M TIMEO4 Undefined Xxxxn088H CAN message data register 040 M_DATA040 Undefined Xxxxn089H CAN message data register 041 M DATA041 Undefined Xxxxn08AH CAN message data register 042 M DATA042 Undefined xxxxn08BH CAN message data register 043 M_DATA043 Undefined Xxxxn08CH CAN message data register 044 M_DATA044 Undefined xxxxn08DH CAN message data register 045 M_DATA045 Undefined xxxxn08EH CAN message data register 046 M DATA046 Undefin
69. areas cannot be controlled by external waits Input of the external WAIT signal can be done asynchronously to the system clock and is sampled at the rising edge of the clock in the T1 and TW states of a bus cycle If the setup hold time at sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 8 3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the programmable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is determined by the side with the greatest number of cycles Programmable wait Wait control Wait by WAIT pin For example if the programmable wait and the timing of the WAIT pin signal are as illustrated below three wait states will be inserted in the bus cycle Figure 4 7 Example of Wait Insertion T1 TW TW TW T2 CLKOUT BER WAIT Wait by WAIT pin J Programmable wait A Wait control A Remark The circle O indicates the sampling timing Preliminary User s Manual U15839EE1VOUMOO 133 Chapter 4 Bus Control Function 4 9 Idle State Insertion Function To facilitate interfacing with low speed memory devices an idle state can be inserted into the cur rent bus cycle after the T2 state to meet the data output float delay time tdf on memory read access f
70. C3BA CANG bus activity register bit set clear function d 2 D Z C3BRP CAN3 bit rate prescaler register in initialisation state only ISTAT bit 1 CAN3 bus diagnostic in diagnostic mode information register only z C3DINF 20 synchronization control C3SYNC register Notes 1 CAN module and CAN module 4 are available the derivatives uPD703129 A and uPD703129 A1 only 2 The address of an interrupt pending register is calculated according to the following for mula effective address PP BASE address offset 436 Preliminary User s Manual U15839EE1VOUMOO Address OffsetNote2 Chapter 14 FCAN Interface Function Table 14 8 Relative Addresses of CAN Module 4 e Registers CAN4 mask 0 register L Access Type R W 1 bit 8 bits Comment lower half word MASK CANA mask 0 register upper half word MASKL CANA mask 1 register L lower half word MASK CANA mask 1 register upper half word MASKL CAN4 mask 2 register L lower half word MASKH2 mask 2 register upper half word MASKL3 CAN4 mask 3 register L lower half word MASKH3 CAN4 mask 3 register H upper half word CACTRL control register bit set clear function C4DEF CAN4 definition register bit set clear function C4LA
71. CAN message configuration register 22 M_CONF22 Undefined xxxxn2D5H CAN message status register 22 M STAT22 Undefined xxxxn2D6H CAN status set cancel register 22 Preliminary User s Manual U15839EE1VOUMOO SC STAT22 0000H 95 xxxxn2E0H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 12 18 Function Register Name CAN message event pointer 230 M EVT230 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn2E1H CAN message event pointer 231 M EVT231 Undefined Xxxxn2EH CAN message event pointer 232 M_EVT232 Undefined Xxxxn2E3H CAN message event pointer 233 M_EVT233 Undefined Xxxxn2E4H CAN message data length register 23 M_DLC23 Undefined Xxxxn2E5H CAN message control register 23 M_CTRL23 Undefined Xxxxn2E6H CAN message time stamp register 23 M_TIME23 Undefined Xxxxn2E8H CAN message data register 230 M_DATA230 Undefined xxxxn2E9H CAN message data register 231 M DATA231 Undefined xxxxn2 EAH CAN message data register 232 M_DATA232 Undefined xxxxn2EBH CAN message data register 233 M_DATA233 Undefined xxxxn2ECH CAN message data register 234 M_DATA234 Undefined xxxxn2EDH CAN message data register 235 M_DATA235 Undefined xxxxn2EEH CAN message
72. EVM GOM EFSD TSM EVM GOM Read 1 2 Indicates the error status of the memory access controller MAC 0 No error occurrence 1 At least one error occurred since the flag was cleared last CGST 1010H A MAC error occurs under the following conditions An attempt to clear the GOM flag was performed although not all CAN modules are set to initialization state Access to an illegal address or access is prohibited by MAC see GOM flag description below Enable forced shut down 0 Forced shut down is disabled 1 Forced shut down is enabled Remark n case of an emergency it might be necessary to reset all CAN modules immediately In this case the EFSD flag has to be set before clearing the GOM flag Indicates the operating mode of the CAN global time system counter CGTSC 0 CAN global time system counter is stopped 1 CAN global time system counter is operating Indicates the event operating mode 0 CAN bridge is disabled 1 CAN bridge is enabled Remark Due to the reason that no CAN bridge is implemented in the V850E CA2 device this bit must not be set at any time Note The register address is calculated according to the following formula effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO 457 Chapter 14 FCAN Interface Function Figure 14 12 Global Status Hegister CGST 2 3 Read 2 2 Indicates the glob
73. Held pending y Servicing of pending NMIO NMIWDT NMIWDT request generated during NMIO servicing NP 1 retained before NMI1 request Main routine NMIO servicing _NMIWDT request Held pending NMIO request V NMIWDT servicing System reset NMIWDT request generated during NMIO servicing 0 set before NMIWDT request ANMO servicing LA NP 0 ee NMIWDT 77 request NMIWDT request generated during NMIO servicing 0 set after NMIWDT request NMIWDT servicing request NMIWDT servicing nd Held d RMIWDT pending 7 request P d 0 Y request NMIWDT NMIO request generated during NMIWDT servicing Main routine NMIWDT servicing request Invalid V request NMI1 request generated during NMIWDT servicing Main routine NMIWDT servicing NMIWDT request Invalid NMIWDT request Preliminary User s Manual U15839EE1VOUMOO 205 Chapter 8 Processing Function 8 2 1 Operation If a non maskable interrupt is generated the CPU performs the following processing and transfers con trol to the handler routine 1 N C3 5 SH Saves the restored PC to FEPC Saves the current PSW to FEPSW Writes exception code 0010H to the higher halfword FECC of ECR Sets the NP and ID bits of the PSW and clears the EP
74. INTTMDn Remark 0 1 296 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 2 3 Basic configuration Table 10 3 Timer Dn Configuration List n 0 1 Generated Count Clock Register Interrupt Capture Timer Other Signal Trigger Output S R Functions 2 fpoLk 4 fpcik 8 TMDn R m fecik 16 2 CMDn R W INTTMDn Timer Dn fpcLK 256 TMCDn RW Remarks 1 Internal peripheral clock 2 S R Set Reset Preliminary User s Manual U15839EE1VOUMOO 297 Chapter 10 Timer 1 Timer D counter Register TMDn n 0 1 Timer Dn is a 16 bit timer It is mainly used as an interval timer for software n 0 1 Starting and stopping TMDn is controlled by the CE bit of the Timer Dn control register TMCDn A division by the prescaler can be selected for the count clock from among fpc 2 and fpc 256 in 8 steps by the CS2 to CSO bits of the TMCDn register TMDn is read only in 16 bit units Figure 10 19 Timer Dn counter register TMDn n z 0 1 Initial 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address value The conditions for which the TMDn register becomes 0000H are shown below Reset input CAE bit 0 CE bit 0 Match of TMDn register and CMDn register Overflow Cautions 1 If the CAE bit of the TMCDn register is cleared to 0 a reset is performed 298 asynchronously 2 Ifthe
75. If the next transfer is executed in block transfer mode the DMAC moves to the T1FH state after the T2FH state In other modes if a wait has occurred the DMAC transitions to the T1FHI state If no wait has occurred the bus is released and the DMAC transitions to the TE state 13 TE state The TE state corresponds to DMA transfer completion The DMAC generates the internal DMA transfer completion signal and various internal signals are initialized After entering the TE state the bus invariably enters the TI state Note The Flyby transfer mode is not supported on Jupiter Preliminary User s Manual U15839EE1VOUMOO 185 Chapter 7 DMA Functions DMA Controller 7 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 7 15 DMAC Bus Cycle Slate Transition Diagram a Two cycle transfer 186 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 5 Transfer Mode 7 5 1 Single transfer mode In single transfer mode the DMAC releases the bus at each byte halfword word transfer If there is a subsequent DMA transfer request transfer is performed again once This operation continues until a terminal count occurs When the DMAC has released the bus if another higher priority DMA transfer request is issued the higher priority DMA request always takes precedence However if a lower prio
76. M TR Remarks 1 The circles Oindicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 Preliminary User s Manual U15839EE1VOUMOO 143 Chapter 5 Memory Access Control Function Figure 5 2 SRAM External ROM External l O Access Timing 6 6 f When write read operation T1 T2 T1 T2 CSn output RD output UWR output DO to D15 I O Remarks 1 The circles O indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 144 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function 5 2 Page ROM Controller ROMC The page ROM controller ROMC is provided for access to ROM page ROM with the page access COPAS of addresses with the immediately preceding bus cycle is carried out and wait control for normal access off page and page access on page is executed This controller can handle page widths from 8 to 128 bytes 5 2 1 Features Direct connection to 8 bit 16 bit page ROM supported n case of 16 bit bus width 4 8 16 32 64 word page access supported n case of 8 bit bus width 8 16 32 64 128 word page access supported Page ROM access a minimum of 2 states On page judgment function Addresses to be compared can be changed through setting of the PRC register Upto 7 states of progra
77. MODE2 Vppax RESET RESOUT connect to Vpp3x via a resistor X2 Please refer to the datasheet Please refer to the data sheet Please refer to the data sheet Vppsx AVpp Vsssx to A15 4 DO to D15 5 Preliminary User s Manual U15839EE1VOUMOO 53 Chapter 2 Pin Functions Figure 2 1 Pin VO Circuits Type 2 Type 3 Type 4 Voo e IN OUT deta Type 5 VDD e IN OUT output I N ch Output disable disable 77 777 input enable Type 5 K Type 9 C Vop Tr P ch Data t MH L P ch Comparator l T IN o IN OUT a E p gt mI om yp pU disable AVss VREF threshold voltage Input enable enable Type 16 feedback cut off _ _P ch E Do XT1 XT2 54 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function The CPU of the V850E CA2 Jupiter is based on a RISC architecture and executes almost all the instructions which can be accessed from the iCache in one clock cycle using a 5 stage pipeline control 3 1 Features Minimum instruction cycle 31 25 ns 9 internal 32 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general registers Internal 32 bit architecture Five stage pipeline control e Multiplication division instruc
78. Preliminary User s Manual U15839EE1VOUMOO 115 4 6 Bus Access Chapter 4 Bus Control Function 4 6 1 Number of access clocks The number of basic clocks necessary for accessing each resource is as follows Table 4 1 Number of Bus Access Clocks Resources Bus width Internal Instruc Internal RAM Peripheral I O External memory tion Cache 32 bits 16 bits 16 bits Bus Cycle Configuration 32 bits Instruction fetch Normal access 4 Note 1 4Note 1 oNote 2 Branch 2 1 Note 2 Operand data access 1 gNote 2 Note 2 Notes 1 The instruction fetch becomes 2 clocks in case of contention with data access 2 This is the minimum value 4 6 2 Bus sizing function The bus sizing function controls data bus width for each CS area The data bus width is specified by using the bus size configuration register BSC 1 Bus size configuration register BSC This register can be read written in 16 bit units 15 14 18 12 1 9 8 7 6 5 4 3 2 1 0 Address Wa value FFFFFO66H 5555H sos TE gt ems Temp 2 TES L L l L L L L l L l 50 57 56 55 54 53 52 CS1 Bit Name Function BSn1 0 n 0 to 7 Bit Position Data Bus Width Sets the data bus width of CSn area BSnO Data Bus Width of CSn area 8 bits 16 bits Cautions 1 Write to the BSC register after reset and then do not change the set value Also
79. Specifies the CAN bus type 0 CAN bus type is low speed bus lt 125 kbps 1 CAN bus type is high speed bus gt 125 kbps Note The register address is calculated according to the following formula effective address PP_BASE address offset Remarks 1 Writing to this register is only possible if CAN module is set into initialisation mode 2 CPU can read CxBRP register at any time Caution In diagnostic mode the CxBRP register is hidden and the CxDINF register appears instead of it at the same address Preliminary User s Manual U15839EE1VOUMOO 503 Figure 14 40 Chapter 14 FCAN Interface Function CAN 1 to 4 Bit Rate Prescaler Registers C1BRP to CABRP 2 2 BRP7 to BRPO TLM 1 BRP5 to BRPO TLM 0 Specifies the bit rate prescaler for the CAN protocol layer TLM 0 Bit Rate Prescaler fBTL fMEM 2 1 EIER fete fmem 4 BRPO k 8 0 0 0 0 0 0 fet 6 0 0 0 0 fer 10 fgr 126 fer 128 Bit Rate Prescaler BRPO fer 1 fBTL fem far fmem 2 fer fari fmem 4 fate 5 fer 255 fer 256 Remark The BRP defines the period of the base clock for the protocol layer of a CAN
80. rrrrr000 010RRRRR GR reg2 GR reg2 GR reg2 Note 4 Signed division regi reg2 rrrrr001 111RRRRR result GR reg2 GR reg1 imm5 reg2 rrrrr010 result GR reg2 sign extend imm5 CCCC reg2 rrrrrl11 1110ccce 00000000 00000000 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H Saturated operation regi reg2 rrrrr000 110RRRRR GR reg2 saturated GR reg2 GR reg1 imm5 reg2 rrrrr010 00111111 GR reg2 saturated GR reg2 Sign extend imm5 regt reg2 rrrrr000 101RRRRR GR reg2 saturated GR reg2 GR reg1 ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Only the lower half word data is valid ddddddddddddddddddddd is the higher 21 bits of dip22 dddddddd is the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification Preliminary Users Manual U15839EE1VOUMOO 595 Appendix A List of Instruction Sets Table A 6 Instruction Set List 4 7 Instruction Group Operand O
81. 1 Peripheral area selection control register BPC The BPC register is a 16 bit register that specifies the base address or the programmable peripheral area This register can be read written in 16 bit units Figure 3 16 Peripheral Area Selection Control Register BPC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addess al value scire 9 SPATZPATIPAT PIS PAS PA PAS PAS FAV PAS PA PAT PAGJFFFF Foes 0000H Ene adm Enables disables usage of programmable peripheral I O area PA15 Usage of Programmable Peripheral I O Area 0 Disables usage of programmable peripheral I O area 1 Enables usage of programmable peripheral I O area PA13to Specifies an address in programmable peripheral I O area PAO corresponds to A27 to A14 respectively Remark For V850E CA2 the recommended setting of the BPC setting is 8600H With that initialization the base address of the programmable peripheral area is located at 180 OOOOH Therefore the FCAN macro is mapped to the memory location 180 0000H to 180 11FFH 84 Preliminary User s Manual U15839EE1VOUMOO A list of the programmable peripheral I O registers is shown below Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 1 18 Bit Units Address Function Register Name fo
82. 1 2 478 Message Data Length Code Registers 00 to 31 M DLCOO to M DLC31 480 Message Control Registers 00 to 31 M CTRLOO to M CTRL31 1 2 481 Message Time Stamp Registers 00 to 31 M TIMEOO0 to M TIMES1 483 Message Event Registers m0 m1 and m3 M EVTm0O M EVTm1 M EVTm2 M EVTm3 m 00 31 484 CAN 1 to 4 Mask 0 to 3 Registers L H CxMASKLO to CxMASKL3 CXMASKHO to CXMASKH3 x 1 4 485 CAN 1 to 4 Control Registers C1CTRL to CACTRL 1 5 487 CAN 1 to 4 Definition Registers C1DEF to C4DEF 1 4 492 CAN 1 to 4 Information Registers C1LAST to CALAST 496 CAN 1 to 4 Error Counter Registers C1ERC to CAERO 497 CAN 1 to 4 Interrupt Enable Registers C1IE to CAIE 1 3 498 CAN 1 to 4 Bus Activity Registers C1BA to 1 2 501 CAN 1 to 4 Bit Rate Prescaler Registers C1BRP to C4BRP 1 2 503 GAN B s Bit TIMING tee oer ni ee e ee ee ee EE greed 505 CAN 1 to 4 Synchronization Control Registers C1 SYNC to C4SYNC 1 2 506 CAN 1 to 4 Bus Diagnostic Information Registers C1DINF to C4DINF
83. 1 to 2 for the deriva tive uPD703128 A Preliminary User s Manual U15839EE1VOUMOO 517 Chapter 14 FCAN Interface Function Example for C routine 518 int CAN Modulelnit unsigned char module no unsigned short value unsigned short sync value can module type can mod ptr define ptr can mod ptr amp can module module no load ptr can mod ptr CxCTRL clear CxCTRL except INIT can mod ptr CxDEF OxOOFF clear CXDEF can mod ptr CxlE 0xOOFF clear CxIE can mod ptr CxBRP brp value set CxBRP can mod ptr CxSYNC sync value set CXSYNC can mod ptr maskO low 0x0000 clear maskO can mod ptr maskO high 0x0000 can mod ptr gt mask1 low 0x0000 clear mask1 can mod ptr mask1 high 0x0000 can mod ptr mask2 low 0x0000 clear mask2 can_mod_ptr gt mask2_high 0x0000 can_mod_ptr gt mask3_low 0x0000 clear mask3 can_mod_ptr gt CxCTRL 0x0001 clear INIT flag return 0 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 3 Setting a CAN Module into initialisation state The following routine is required if a CAN module has to be set from normal operation into initiali sation mode Please notice that all CAN modules are automatically set to initialisation mode after reset There fore the sequence is only required if the CAN module is already in normal operation Figure 14 48 Setting CAN Module into Initia
84. 2 1 st Access Word data 31 24 23 16 15 8 7 7 0 0 Address 4n 2 External data bus lt 4 gt Access to address 4n 3 1 st Access Word data 126 31 24 23 16 15 8 Address 7 7 4n 3 0 0 External data bus 2 nd Access 31 24 23 16 15 8 Address 7 7 4n4 3 0 0 Word data External data bus 2 nd Access 31 24 23 16 15 8 Address 7 7 LE 4n 4 0 0 Word data External data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 4 0 0 Word data External data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 5 0 0 Word data External data bus Preliminary User s Manual U15839EE1VOUMOO 4 th Access 31 24 23 16 15 8 Address 7 7 4n 5 0 0 Word data External data bus 4 th Access 31 24 23 16 15 8 Address f 7 4n 6 0 0 Word data External data bus Chapter 4 Bus Control Function c When the data bus width is 16 bits Big Endian 1 Access to address 4n 1 st Access 31 24 23 16 Address 15 15 4n 8 8 7 7 4n 1 0 0 Word data External data bus 2 Access to address 4n 1 1 st Access 31 24 23 16 em Address 15 154 1 8 7 7 4n 1 0 0 Word data External data bus 2 nd Access 31 24 23 16 Addres 15 15 4n 2 8 8 7 7 4n4 3 0 0 Word data External data bus 2 nd Access 31 24 23 16 Address 15 15 4n 2 8 8 7 7 4n 3 0 0 Word data External data bus 3 rd Access 31 24 23 16 Address 15 15
85. 4n 4 8 8 7 0 ot Word data External data bus Preliminary User s Manual U15839EE1VOUMOO 127 128 Chapter 4 Bus Control Function 3 Access to address 4n 2 1 st Access 2 nd Access 31 31 24 24 23 23 16 Address 16 Address 15 15 15 15 4n 2 4n 4 8 8 8 8 7 7 7 7 4n 3 4n 5 0 0 0 0 Word data External Word data External data bus data bus lt 4 gt Access to address 4n 3 1 st Access 2 nd Access 3 rd Access 31 31 31 24 24 24 23 23 23 16 u Address 16 Address 16 Address 15 15 15 15 15 15 4 4 40 6 8 8 8 8 8 8 7 7 7 7 7 7 13 4n 3 4n 5 ra 0 0 0 0 0 O13 Word data External Word data External Word data External data bus data bus data bus Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function d When the data bus width is 8 bits Big Endian 1 Access to address 4n 1 st Access 2 nd Access 31 31 24 24 23 23 16 16 15 15 8 Address 8 Address 7 7 7 7 4n 4n 1 0 0 0 0 Word data External Word data External data bus data bus 2 Access to address 4n 1 1 st Access 2 nd Access 31 31 24 24 23 23 16 16 15 15 8 Address 8 Address 7 7 7 7 4 1 4n 2 0 0 0 0 Word data External Word data External data bus data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4 2 0 0 Word data External data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 3 0 0 Word data External data bus Preliminary User s Manual U15839
86. Buffer Register Configuration on page 183 shows the configuration of the buffer register Figure 7 14 Buffer Register Configuration Data read lt 23 a T ic Data write Master Slave Address register register count controller dip m Remark nz0to3 Preliminary User s Manual U15839EE1VOUMOO 183 7 4 Chapter 7 DMA Functions DMA Controller DMA Bus States 7 4 1 Types of bus states The DMAC bus states consist of the following 13 states 1 2 3 4 5 6 7 8 9 10 184 TI state The TI state is an idle state during which no access request is issued TO state This is the DMA transfer ready state state in which a DMA transfer request has been issued and the bus mastership is acquired for the first DMA transfer state The bus enters the T1R state at the beginning of a read operation in the two cycle transfer mode Address driving starts After entering the T1R state the bus invariably enters the T2R state T1RI state This is a state in which the DMAC is awaiting an acknowledge signal for an external memory read request After the last T1RI state the DMAC always transitions to the T2R state T2R state The T2R state corresponds to the last state of a read operation in the two cycle transfer mode or to a wait state In the last T2R state read data is sampled After entering the last T2R state the bus invariably enter
87. CxINT3 0 No Interrupt pending 1 Interrupt pending Notes 1 The register address is calculated according to the following formula effective address PP_BASE address offset x 1 to 2 for the derivative uPD703128 x 1 to 4 for the derivatives uPD703129 A uPD703129 A1 470 Preliminary User s Manual U15839EE1VOUMO00 Chapter 14 FCAN Interface Function Figure 14 23 1 to 4 Interrupt Pending Registers C1INTP to C4INTP 2 2 Read 2 2 Bit Position Note Indicates a error passive or bus off status on transmission of CAN module x CxINT2 0 No Interrupt pending 1 Interrupt pending Indicates a reception completion interrupt of CAN module x CxINT1 0 No Interrupt pending 1 Interrupt pending Write Bit Position Indicates a transmission completion interrupt of CAN module x CxINTO 0 No Interrupt pending 1 Interrupt pending Bit Name Note 1 2 Clears the interrupt pending bit CXINT6 CL CxINT6 0 No change of CxINT6 bit 1 CxINT6 bit is cleared 0 Clears the interrupt pending bit CXINT5 CL CxINT5 0 No change of CxINTS5 bit 1 CxINT5 bit is cleared 0 Clears the interrupt pending bit CxINTA CL CxINT4 0 No change of CxINT4 bit 1 CxINT4 bit is cleared 0 Clears the interrupt pending bit CXINT3 CL CxINT3 0 No change of CxINTS bit 1 CxINTS bit is cleared 0 Clears the interrupt pending bit CxINT2 CL CxINT2 0 No chang
88. Data Data 2 The broken line indicates the high impedance state CSn CS0 CS3 and CS4 Preliminary User s Manual U15839EE1VOUMOO 151 Chapter 5 Memory Access Control Function Figure 5 6 Page ROM Access Timing 3 4 c During read address setup wait idle state insertion when half word word access with 8 bit bus width or when word access with 16 bit bus width TASW T1 T2 TASW TO1 TO2 TI to A23 output Off page address On page address CSn output RD output UWR output ww TT DO to D7 I O DO to D15 I O WATT input Remarks 1 The circles O indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 152 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function Figure 5 6 Page ROM Access Timing 4 4 d During read address setup wait idle state insertion when byte access with 8 bit bus width or when byte half word access with 16 bit bus width TASW T1 T2 TASW TO1 TO2 TI to A23 output Off page address On page address CSn output RD output UWR output wee d DO to D7 I O DO to D15 I O WAIT input Remarks 1 The circles O indicate the sampling timing 2 The broken line indicates the
89. Delay g O0 Remarks 1 n 0to2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed Preliminary User s Manual U15839EE1VOUMOO 413 Chapter 13 Serial Interface Function Figure 13 36 Timing Chart of Interrupt Request Signal Output in Delay Mode 2 2 b When CKP bit z 1 DAP bit z 1 Input clock SCKOn input output SIOn input SO0n output Reg_R W INTCSIn interrupt CSOT bit Delay 4 Remarks 1 n 0to2 2 Reg R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBL n write was performed 414 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 2 Repeat transfer mode a Usage receive only 1 Set the repeat transfer mode AUTO bit of CSIMn register 1 and the receive only mode TRMD bit of CSIMn register 0 2 Read SIRBn register start transfer with dummy read 3 Wait for transmission reception completion interrupt request INTCSIOn 4 When the transmission reception completion interrupt request INTCSIOn has been set to 1 read the SIRBn registerN t reserve next transfer 5 Repeat steps 3 and 4 n 2 times n number of transfer data 6 Following output of the last tr
90. For additional information on the CAN bus bit timing please refer to ISO 11898 The relation between CAN memory clock and CAN bus baud rate is f 1 Seri CANBUS pDBTxTQ DBT DBTxBRP Valid values for DBT and BRP are ee qu Note BRP is the resulting bit rate prescaler value specified in the CxBRP register where the variable corresponds to the contents of bits BRP5 to BRPO when TLM bit 0 and bits BRP7 to BRPO bits when TLM bit 1 respectively x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A Preliminary User s Manual U15839EE1VOUMOO 505 Chapter 14 FCAN Interface Function The CxSYNC registers specify the data bit time DBT sampling point position SPT and syn chronisation jump width SJW of the corresponding CAN module x x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A These registers can be read written in 8 bit and 16 bit units However write access is only permit ted in initialisation mode ISTAT bit of the CxCTRL register 1 Figure 14 42 CAN 1 to 4 Synchronization Control Registers C1SYNC to C4SYNC 1 2 Address Initia ib 0H 18 Ec MS OE Ep 088 OR amp c4 S 2 OffsetNote value C18Y 05EH 0218H C28Y 09EH 0218H C3SY 10DEH 0218H C4SY 11EH 0218H
91. GMP Ca Le bia ie Me OO iusta dur Lt LM LM EMT Oh ahs p toh tees R 58 GTP SW eaae s Bact a dee ate I Rei E RUD OM ees e eta ee T Ed does 58 Current consumption 541 GN DD riat dite edem aer Pro e de ae ee 49 OV sued dure oU CHA dr a e SORA sR eR LA LE 49 Cycle measurement 287 D D A Converter o n el AE LIAE LR pU UE AC be o b oid V LOS bw 524 DADGO to DADGS oi x me T ones ee don e e P EE 175 Gata ramen ads ceste IE e RUE RUE V HER eO Gu e a ANUS D iI ONUS pe EAD RSEN 375 Data SPACE EIL 67 Data wait control registers 0 1 00 cee 131 DB GO eg ERRARE aes e Un deat ee Pati hate 174 Dec LPS 174 Bic EE 58 DBPSW usd Me strud te Stute sort PEU Ad II ALL E LA MAUS 58 DGHGO to DGHGO3 4 3 et ee eee Eun pub USER DRE De eS ed ed edad 177 DDAHO Lent ete denigrate mi Ax CUI HIE hae fens Rank tole btc Era Io takes ang tnt t D RE Go RAM Pe C 172 biker 172 602 Preliminary User s Manual U15839EE1VOUMOO Appendix B Index DDAEO ate eine Sa ies tke eae ER S se Ee els ul Pale E teeta Eae I tie ala ade a LM s 173 DDAE9 eod den elei date fi b ene onde amd ted bie e deal er ue 173 DIS ced or cru dicis stb ad LM E stt aod dia
92. Ground These are the ground pins for the 5 V power supply 24 Vppao Vppsg Power supply These are the positive 3 3 V power supply pins 25 Vss30 to Vss36 Ground These are the ground pins for the 3 3 V power supply 26 AVpp Analog power supply This is the analog positive power supply pin for the A D converter 27 Analog ground This is the ground pin for the A D converter 28 AVggr Analog reference voltage Input This is the reference voltage supply pin for the A D converter 29 AO to A15 Address output Output These pins are the address output pins 30 DO to D15 Data input output Input output These pins are the data input output pins 50 Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions 2 3 Types of Pin I O Circuit and Connection of Unused Pins Table 2 4 Types of Pin I O Circuit and Connection of Unused Pins 1 3 I O Circuit Type Recommended connection P10 FCRXD1 5 K For input individually connect to Vpps Vsss P11 FCTXD1 via a resistor For output leave open P12 FCRXD2 P13 FCTXD2 P14 FCRXD3 P15 FCTXD3 P16 RXD51 P17 TXD51 P20 5100 5 21 SO00 P22 SCK00 P23 5101 24 5001 25 SCKOT P26 RXD50 P27 TXD50 P30 TIGOO INTPOO 5 K P31 TIGO1 TOGO01 P32 TIGO2 TOGO02 P33 TIGO3 TOGO03 P34 TIGO4 TOG04 P35 TIGO5 5 40 TIG10 INTP10 5 K
93. INTCCGn1 Caution To perform successive write access during operation for rewriting the GCCny register n 1 to 4 you have to wait for minimum 7 peripheral clocks periods fpc 330 Preliminary User s Manual U15839EE1VOUMOO 3 Chapter 10 Timer PWM output free run Basic settings m 1 to 4 free run mode enable TOGnm Compare mode for GCCnm assign counter for GCCnm 0 TMGnO 1 TMGn1 Note The PWM mode is activated by setting the SWFGm and the CCSGm bit to 1 PWM setting method An usable compare register is one of GCCn1 to GCCn4 and the corresponding counter must be selected with the TBGm bit Select a count clock cycle with the CSE12 to CSE10 bits TMGn1 register or CSE02 to CSE00 bits TMGn0 register Specify the active level of a timer output TOGnm pin with the ALVGm bit When using multiple timer outputs the user can prevent TOGnm from becoming active simultaneously by setting the OLDE bit of TMGMHn register to provide step by step delays for TOGnm This capability is useful for reducing noise and current Write data to GCCnm Start timer operation by setting POWER bit and TMGOE bit or 1 bit Preliminary User s Manual U15839EE1VOUMOO 331 Chapter 10 Timer PWM operation 1 When the value of the counter matches the value of GCCnm a match interrupt INTCCGnm is output 2 When the counter overflows an overflow interrupt INTTMGn0 or INTTMGn1 is ge
94. INTCCGn5 is output and the counter is cleared This operation is referred to as match and clear TOGnm does not make a transition until the first match and clear event TOGnm makes a transition to the active level after the first match and clear event When the value of the counter matches the value of GCCnm TOGnm makes a transition to the inactive level and a match interrupt INTCCGnm is output 6 When the next match and clear event occurs INTCCGn0 INTCCGn5 is output and the counter is cleared The counter resumes count up operation starting with 0000H an cR Example where the data N is set and the counter TMGn0 is selected OFFFH is set in GCCn0 and N lt OFFFH Figure 10 53 Timing of PWM operation match and clear ENFGO TOGn1 ALVG1 1 TOGn 1 ALVG1 0 OFFFH OFFFH OFFFH Match TMGno E E GCCn1 E N INTCCGn1 INTCCGnO When OOOOH is set in GCCn0 GCCn5 the value of the counter is fixed at OOOOH and the counter does not operate The waveform of INTCCGnO INTCCGn5 varies depending on whether the count clock is the reference clock or the sampling clock Preliminary User s Manual U15839EE1VOUMOO 341 342 Chapter 10 Timer a When FFFFH is set in GCCn0 or GCCn5 match and clear When FFFFH is set in GCCn0 GCCn5 operation equivalent to the free run mode is performed When an overflow occurs INTTMGnO INTTMGn1 is generated but INTCCGnO INTCCGn5
95. In Output Mode When the P6 register is read the values of P6 are read Writing to the P6 register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as the serial interface CSI2 or as external interrupt request input Notes 1 lf using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register P6 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Alternate Pin Name Remarks Block Type Serial interface CSI2 input output or external interrupt request input Preliminary User s Manual U15839EE1VOUMOO 569 Chapter 16 Port Functions 2 Setting in input output mode and control mode Port 6 is set in input output mode using the port 6 mode register PM6 In control mode it is set using the port 6 mode control register PMC6 a Port 6 mode register PM6 This register can be read or written in 8 bit or 1 bit units Figure 16 23 Port 6 Mode Register PM6 0 Address At Reset 7 6 5 4 3 2 1 PM6n Specifies input output mode of P6n pin 7100 n 7 to 0 0 Output mode Output buffer on E 1 Input mode Output bu
96. M DATA251 Undefined Xxxxn32AH CAN message data register 252 M_DATA252 Undefined xxxxn32BH CAN message data register 253 M DATA253 Undefined xxxxn32CH CAN message data register 254 M DATA254 Undefined xxxxn32DH CAN message data register 255 M DATA255 Undefined xxxxn32EH CAN message data register 256 M DATA256 Undefined xxxxn32FH CAN message data register 257 M DATA257 X XXXIX XxX XxX Xx Undefined xxxxn330H CAN message ID register L25 M_IDL25 Undefined xxxxn332H CAN message ID register H25 M_IDH25 Undefined xxxxn334H CAN message configuration register 25 M CONF25 Undefined xxxxn335H CAN message status register 25 M STAT25 Undefined xxxxn336H CAN status set cancel register 25 SC STAT25 0000H xxxxn340H CAN message event pointer 260 M EVT260 Undefined xxxxn341H CAN message event pointer 261 M EVT261 Undefined xxxxn342H CAN message event pointer 262 M EVT262 Undefined xxxxn343H CAN message event pointer 263 M EVT263 Undefined xxxxn344H CAN message data length register 26 M DLC26 Undefined xxxxn345H CAN message control register 26 M CTRL26 Undefined xxxxn346H CAN message time stamp register 26 M TIME26 Undefined Xxxxn348H CAN message data register 260 M_DATA260 Undefined Xxxxn349H C
97. Market Communication Dept apes 4411 Fax 449 211 6503 274 PE SADED South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6465 6829 Fax 02 2719 5951 Thank you for your kind support Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 6250 3583 Japan NEC Semiconductor Technical Hotline Fax 81 44 435 9608 I would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity o Technical Accuracy Organization m
98. Non maskable interrupts of V850E CA2 are available for the following two requests e NMI pin input Non maskable watchdog timer interrupt request When the valid edge specified by the ESNO bit of the Interrupt mode register INTM3 is detected on the NMI pin the interrupt occurs The watchdog timer interrupt request is only effective as non maskable interrupt if the WDTMS bit of the watchdog timer mode register WDTM is set 0 If multiple non maskable interrupts are generated at the same time the highest priority servicing is exe cuted according to the following priority order the lower priority interrupt is ignored NMIWDT NMIO Note that if a NMI from port pin or NMIWDT request is generated while NMI from port pin is being serv iced the service is executed as follows 1 If a NMIO is generated while NMIO is being serviced The new NMIO request is held pending regardless of the value of the PSW NP bit The pending NMIVC request is acknowledged after servicing of the current NMIO request has finished after execution of the RETI instruction 2 Ifa NMIWDT request is generated while NMIO is being serviced If the PSW NP bit remains set 1 while NMIO is being serviced the new NMIWDT request is held pending The pending NMIWDT request is acknowledge after servicing of the current NMIO request has finished after execution of the RETI instruction If the PSW NP bit is cleared 0 while NMIO is being serviced the newly g
99. P41 TIG11 TOG11 P42 TIG12 TOG12 P43 TIG13 TOG13 P44 TIG14 TOG14 P45 TIG15 INTP15 P50 FCRXD4 5 K P51 FCTXD4 P52 INTP4 P53 INTP5 P54 TICOO INTP20 P55 TICO1 INTP21 P56 TOCO Preliminary User s Manual U15839EE1VOUMOO 51 Chapter 2 Pin Functions Table 2 4 Types of Pin I O Circuit and Connection of Unused Pins 2 3 I O Circuit Type Recommended connection For input individually connect to Vpps or Vsss via a resistor For output leave open For input individually connect to Vpps or Vsss via a resistor For output leave open For input individually connect to Vpps or Vsss via a resistor For output leave open For input individually connect to Vpps or Vsss via a resistor For output leave open For input individually connect to Vpps or Vsss via a resistor For output leave open For input individually connect to Vpps or Vsss via a resistor For output leave open 52 Preliminary User s Manual U15839EE1VOUMOO PCTO Chapter 2 Pin Functions Table 2 4 Types of Pin I O Circuit and Connection of Unused Pins 3 3 Circuit Type PCT1 PCT4 Recommended connection For input individually connect to Vpps or Vsss via a resistor For output leave open PCMO AINO AIN11 MODEO MODE1 connect to Vsssx via a resistor
100. Preliminary User s Manual U15839EE1VOUMOO 339 3 Chapter 10 Timer PMW output match and clear Basic settings m 1 to 4 match and clear mode enable TOGnm Compare mode for GCCnm assign counter for GCCnm 0 TMGnO 1 TMGn1 Note The PWM mode is activated by setting the SWFGm and the CCSGm bit to 1 anana N 0 01 roa 340 Setting Method An usable compare register is one of GCCn1 to GCCn4 and the corresponding counters TMGnO or TMGn1 must be selected with the TBGm bit m 1 to 4 Select a count clock cycle with the CSE12 to CSE10 TMGn1 bits or CSE02 to CSEOO TMGnO bits Specify the active level of a timer output TOGnm with the ALVGm bit When using multiple timer outputs the user can prevent TOGnm from making transitions simultaneously by setting the OLDE bit of TMGMHn register This capability is useful for reducing noise and current Set an upper limit on the value of the counter in GCCn0 or GCCn5 Timer Dn OOOOH is forbidden Write data to GCCnm Start count operation by setting POWER bit and TMGOE bit or TMG1E bit Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer Operation of PWM match and clear 1 When the value of the counter matches the value of GCCnm a match interrupt INTCCGnm is output Caution Do not set 0000H in GCCn0 or GCCn5 in match and clear modus 2 When the value of GCCn0 GCCn5 matches the value of the counter INTCCGnO
101. Preliminary User s Manual U15839EE1VOUMOO 565 Chapter 16 Port Functions 16 3 5 Port 5 Port 5 is a 7 bit input output port in which input or output can be specified in 1 bit units Each port bit can be independently configured to port input port output or peripheral functionNete 1 This register can be read or written in 1 bit and 8 bit units Figure 16 19 Port 5 P5 Address At Reset 7 6 5 4 3 2 1 0 n ux 5 n 7 to 0 Input output port Remark In Input Mode When the P5 register is read the pin levels at that time are read Writing to the P5 register writes the values to that register This does not affect the input pins In Output Mode When the P5 register is read the values of P5 are read Writing to the P5 register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output as the serial interface FCAN4Nete 3 ang as external interrupt request input 1 Operation in control mode Alternate Pin Name Remarks Block Type P50 CRXD4 P51 CTXD4 52 INTP4 Real time pulse unit RPU input output serial Port 5 P53 INTP5 interface FCAN4N te 3 input output or external A P54 TIO INTP20 interrupt request input P55 TH INTP21 P56 TOO Notes 1 lf using peripheral functions the direction setting for the respectiv
102. Program space Of the 32 bits of the PC program counter the higher 6 bits are set to 0 and only the lower 26 bits are valid Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation the higher 6 bits ignore the carry or borrow Therefore the lower limit address of the program space address 0000 0000H and the upper limit address O3FF FFFFH become contiguous addresses Wrap around refers to the situation that the lower limit address and upper limit address become contiguous like this Figure 3 7 Wrap around of Program Space O3FF FFFEH O3FF FFFFH 0000 0000H 0000 0001H Program space Program space 4 direction direction Caution No instruction can be fetched from the 4 KB area of FOOOH to 03FF FFFFH because this area is defined as peripheral I O area Therefore do not execute any branch address calculation in which the result will reside in any part of this area 2 Data space The result of operand address calculation that exceeds 32 bits is ignored Therefore the lower limit address of the program space address 0000 0000H and the upper limit address FFFF FFFFH are contiguous addresses and the data space is wrapped around at the boundary of these addresses Figure 3 8 Wrap around of Data Space FFFF FFFEH FFFF FFFFH 0000 0000H 0000 0001H Preliminary User s Manual U15839EE1VOUMOO Data space Data space direction
103. Reception Completion terrupt INTSERO SEROIC Reception Error 00000360H terrupt INSRO SROIC Reception Completion T 00000370H terrupt INTSTO STOIC Transmission Completion 00000380H terrupt INTSER1 SER1IC Reception Error 00000390H terrupt INSR1 SR1IC Reception Completion T 000003A0H terrupt INTST1 Transmission Completion 000003B0H terrupt INTDMAO pMAoic PMA Channel 0 transfer 000003C0H completed terrupt NTCSI2 CSI2IC 00000350H Notes 1 n 0 to FH 2 INTFC3RX INTFC3TX INTFC3ER INTFC4RX INTFC4TX and INTFCAER are available only in the derivatives PD703129 A and uPD703129 1 Preliminary User s Manual U15839EE1VOUMOO 201 Chapter 8 Interrupt Exception Processing Function Table 8 1 Interrupt Exception Source List 3 3 T Interrupt Exception Source Classifi Default Exception Handler cation Controlling Generating Source Generating Priority Code Address Register Unit nterrupt DMA A Channelt transter M 000003D0H nextPC completed nterrupt pmazic PMA Channel 2 transfer A2 000003E0H nextPC completed nterrupt INTOMA3 DMAaic Channel 3 transfer DMA3 000003FOH nextPC completed nterrupt DOVF DOVF DMA Overflow DMA Trigger 00000400H nextPC nterrupt INTPOO POOIC P30 Port Module 00000410H nextPC nterrupt INTP05 5 P35 Port Module 00000420H nextPC nterrupt INTP10 P10IC P40 Port Mo
104. Reception enabled state The receive operation is set to reception enabled state by setting the RXE bit in the ASIMO register to 1 RXE bit 1 Reception enabled state RXE bit Reception disabled state In reception disabled state the reception hardware stands by in the initial state At this time the contents of the reception buffer register RXBn are retained and no reception completion interrupt or reception error interrupt is generated b Starting a receive operation A receive operation is started by the detection of a start bit The RXDn pin is sampled according to the serial clock from the dedicated baud rate generator BRG of UART5n n 0 1 c Reception completion interrupt When RXE bit 2 1 in the ASIMn register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSRn is generated and the receive data within the reception shift register is transferred to RXBn at the same time Also if an overrun error OVE occurs the receive data at that time is not transferred to the reception buffer register RXBn and either a reception completion interrupt INTSRn or a reception error interrupt INTSERn is generated the receive data within the reception shift register is transferred to RXBn according to the ISRM bit setting in the ASIMn register Even if a parity error PE or framing error FE occurs during a reception operation the receive operation c
105. Table 9 9 Operating States in WATCH Mode Items Operation Clock generator Operating SSCG PLL Stopped Internal system clock Stopped WT WDT clock Operating CPU Stopped I O line Unchanged Peripheral function Stops exclude Watch timer Watchdog timer TMC calibration input Main Clock not available Retains all internal data before entering WATCH mode such as CPU registers status data and on chip RAM D 15 0 A 23 0 Hi Z RD WRi WRO CS 0 CS 4 2 H CLKOUT L Internal data WAIT Input value is not sampled Sub WATCH mode release The SUB WATCH mode can be released by a non maskable interrupt request an unmasked maskable interrupt request or RESET signal input Preliminary User s Manual U15839EE1VOUMOO 261 Chapter 9 Clock Generator 1 Release by interrupt request The SUB WATCH mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level After the main oscillator stabilization time has passed CPU starts operation However if the SUB WATCH mode is entered during execution of an interrupt handler the operation differs on interrupt priority levels as follows a If an interrupt request less priorities than the currently serviced interrupt request is generated the SUB WATCH mode is release but the interrupt is not acknowledged The interrupt request itself is retained b If an interrupt request including a non mask
106. Timer G1 10 3 1 Features of Timer G The Timer Gn n 0 1 operate as Pulse interval and frequency measurement counter event counter Interval timer Programmable pulse output PWM output timer Remark In this Timer Gn chapter following indexes were consequently used e 1104 for the free assignable Input Output channels e n 0 1 for each of the 2 Timer G instance in Jupiter e x 0 1 for bit index i e one of the 2 counters of each Timer Gn e y Oto5 for all of the 6 capture compare channels 306 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 3 2 Function overview of each Timer Gn e 16 bit timer counter TMGn0 TMGn1 2 channels Bit length Timer Gn registers TMGn0 TMGn1 16 bits e Capture compare register GCCny 6 16 bit 2registers are assigned fix to the corresponding one of the 2 counters 4 free assignable registers to one of the 2 counters e Count clock division selectable by prescaler frequency of peripheral clock fpc 16 MHz In 8 steps from fpciK 2 to 256 e Interrupt request sources Edge detection circuit with noise elimination Compare match interrupt requests 6 types Perform comparison of capture compare register with one of the 2 counters TMGn0 TMGn1 and generate the INTCCGny 0 to 5 interrupt upon compare match Timer counter overflow interrupt requests 2 types In free run mode the INTTMGnO INTTMGn1 interrupt is gene
107. ing each power save mode by interrupt or when resetting after executing interrupt pro cessing start executing from the next instruction without executing 1 instruction just after the store instruction Preliminary User s Manual U15839EE1VOUMOO 103 Chapter 3 CPU Function 3 6 1 Command Register PRCMD This command register PRCMD is to protect the registers that may have a significant influence on the application system PSC PSM from an inadvertent write access so that the system does not stop in case of a program hang up This register can only be written in 8 bit units undefined data is used when this register is read Only the first write access to a specific on chip register hereafter referred to as a specific register after data has been written to the PRCMD register is valid In this way the value of the specific register can be rewritten only in a specified sequence and an illegal write access is inhibited Figure 3 17 Command Register PRCMD Format 6 5 4 3 2 1 0 Address R W At Reset 7 REG7 to REGO registration code any 8 bit data Caution The register must be written with store instruction execution by CPU DMA transfer is prohibited 104 Preliminary User s Manual U15839EE1VOUMO00 Chapter 3 CPU Function 3 6 2 Peripheral Command Register PHCMD This command register PHCMD is to protect the registers that may have a significant influence on the application system WCC from an in
108. instruction execution time 31 25 ns 32 MHz General registers 32 bits x 32 e Instruction set V850E compatible with V850 plus additional powerful instructions for reducing code and increas ing execution speed Signed multiplication 16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits 1 to 2 clocks Saturated operation instructions with overflow underflow detection function 32 bit shift instructions 1 clock Bit manipulation instructions Load store instructions with long short format Signed load instructions Memory Part Number Internal ROM Internal RAM Full Can 2 0b active Full CAN RAM 1 Kbytes 32 message buffers 1 Kbytes 32 message buffers 1 Kbytes 32 message buffers uPD703128 A Rom less 12 Kbytes 2 Channels uPD703129 A Rom less 16 Kbytes 4 Channels uPD703129 A1 Rom less 16 Kbytes 4 Channels Cache Controller 2 way associative 4K Bytes Boot Loader Internal Boot Loader for downloading Flash Self Programming routines into RAM Support of virgin programming for external flash memories Clock Generator Internal Spread Spectrum PLL CPU Core BCU clock supply Internal PLL Peripheral clock supply 4 fold PLL Frequency range up to 32 MHz Crystal frequency range 4 MHz 5 MHz Internal Slow Running clock oscillator Built in power saving modes WATCH HALT STOP Power supply voltage range Vpps 4 5 V lt Vpp5
109. not It is read only and is set to 1 when DMA transfer ends and cleared 0 when it is read 0 DMA transfer had not ended 1 DMA transfer had ended When this bit is set to 1 at terminal count output the Enn bit is not cleared to 0 and the DMA transfer enable state is retained Moreover the next DMA transfer request can be accepted even when the TCn bit is not read When this bit is cleared to 0 at terminal count output the Enn bit is cleared to 0 and the DMA transfer disable state is entered At the next DMA request the setting of the Enn bit to 1 and the reading of the TCn bit are required When this bit is set to 1 DMA transfer is forcibly terminated If this bit is set to 1 in the transfer enable state TCn bit 0 Enn bit 1 transfer is started Specifies whether DMA transfer through DMA channel n is to be enabled or disabled This bit is cleared to 0 when transfer ends It is also cleared to 0 when DMA transfer is forcibly terminated by means of setting the INITn bit to 1 or by NMI input 0 DMA transfer disabled 1 DMA transfer enabled Remark nz0to3 Preliminary User s Manual U15839EE1VOUMOO 177 Chapter 7 DMA Functions DMA Controller 7 2 6 DMA disable status register DDIS This register holds the contents of the ENn bit of the DCHCn register during NMI input This register is read only in 8 bit or 1 bit units Figure 7 8 DMA Disable Status Register DDIS 7 6 5
110. o a E eN interrupt kail output Remarks 1 p Setting value of CCCOO register 0000H to FFFFH 292 2 q Setting value of CCCO01 register 0000H to FFFFH 3 p 1 44 4 In this example the active level of TOCO output is set to high level b When CCCO00 CCCO01 When the setting value of the CCCOO register and the setting value of the CCCO1 register are the same the TOCO output remains inactive and does not change Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 1 6 Sub Oscillator Calibration Function For automotive dashboard application customer need to achieve a watch timer accuracy of about 1 sec week This target is difficult to manage using a 32 KHz crystal for sub oscillator because of the temperature dependency of these crystal types The crystal type used for main oscillator has a temperature deviation which compensates themselves over one year summer winter while the temperature deviation of sub oscillator accumulates over one year A sub clock oscillator calibration function is available by measuring the sub clock deviation with the main clock oscillator To perform this measurement in a power efficient way a special clock path for Timer CO is supported This clock supply switches between the peripheral macro clock prescaler output and direct clock from the main oscillator input In the Jupiter device the Timer CO will be
111. occurrence of a Reset or if a power save mode has been released After release from Watch mode Idle mode or Stop mode the register PCC is set to Main oscillator mode After release from Sub Watch mode the register PCC is set to Main oscillator mode in case that the bit OSCDIS is cleared 0 or the register PCC is set to Sub Oscillator mode if the bit OSCDIS is set 1 The bit OSCDIS can be found in the register Power Save Mode PSM Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 3 5 Reset Source Monitor Register RSM This is a 8 bit register that indicates the source of the last system reset This register can only be read in 8 or 1 bit units Figure 9 6 Reset Source Monitor Register RSM Initial value 7 6 5 4 3 2 1 0 Address Reset Source Monitor flag RESM 0 Last Reset was caused by external RESET input 1 Last Reset was caused by internal Watchdog timer overflow Preliminary User s Manual U15839EE1VOUMOO 247 Chapter 9 Clock Generator 9 3 6 SSCG Frequency Modulation Control Register SCFMC This is a 5 bit register that controls the frequency modulation of SSCG in dithering mode and the post scale factor of the SSCG This register can be read or written in 8 or 1 bit units Figure 9 7 SSCG Frequency Modulation Control Register SCFMC 7 6 5 4 3 2 1 0 Address Pital value Bit name Function Frequency modulation control bits Post Scale Factor of the SSCG If SSCG operation is
112. serial clock I O from to CSI00 CSIO2 P25 P67 P26 P16 P27 P17 All Vpp3 pins have to be connected to each other On each pin of Vpp3 a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin serial receive data input to UART50 UARTS51 serial transmit data output from UART50 UART51 On CVpp a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin and must be connected to each other CAN module and CAN module 4 are available in the derivatives uPD703129 A and pgPD703129 A1 only 36 Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions Table 2 2 Non Port Pins 2 3 Pin Name Function Alternate FCRXD1 P10 FCRXD2 P12 serial receive data input to FCAN1 FCAN4 FCRXD3Note 3 P14 FCRXD4Note 3 P50 FCTXD1 P11 FCTXD2 P13 serial transmit data output to FCAN1 FCAN4 P15 FCTXD3Note 3 FCTXD4Note 3 P51 INTPO P61 INTP1 P62 INTP2 6 INTPS external interrupt request P64 INTP4 P52 INTP5 P53 INTPOO input Timer G 0 external interrupt 0 P30 TIGOO 5 input Timer G 0 external interrupt 5 P35 TIGO5 INTP10 input Timer G 1 external interrupt 0 P40 TIG10 INTP15 input Timer G 1 external interrupt 5 P45 TIG15 input Timer C 0 external interrupt 0 P54 TICOO input Timer C 0 extern
113. sponds to the DBTR4 to DBTRO bits of the CxSYNC register TQ DBTR q 1 TQ lt 25T 7 lt q lt 24 q decimal value of bits DBTR4 to DBTRO 3 Rule for synchronization jump width SJW setting The number of TQ allowed for soft synchronization must not exceed the number of TQ for PHASE SEG2 The length of PHASE SEG2 is given by the difference of data bit time DBTR and the sampling point position SPTR Converted to register values the following condition applies SJW 5 1 DBT SPT s S lt 4 1 s decimal value of bits SJWI SJWO Remark The time quantum TQ is determined by the base clock far for the CAN protocol layer which is defined in the CxBRP register 1 TQ Sart Caution The rules above represent CAN protocol limits Violating these rules may cause erro neous operation Preliminary User s Manual U15839EE1VOUMOO 509 Chapter 14 FCAN Interface Function 14 4 2 Example for baudrate setting of CAN module To illustrate how to calculate the correct setting of the registers CXBRP and CxSYNC the following example is given to 4 Requirements from CAN bus FCAN system global frequency 16 MHz CAN bus baud rate fcangus 831 3 kHz Sampling point 7596 or above Synchronization jump width 3 TQ First the frequency ratio between the global frequency and the CAN bus baud rate is calculated fMEM 16 MHz 6 f 1 192 3 2 CANBUS 83 3 KHz The register descript
114. transfer mode example in which a higher priority DMA transfer request is generated DMA channels 2 and 3 are used for the block transfer example Figure 7 26 Block Transfer Example DMA Transfer Request CH2 DMA Transfer Request CH3 The bus is always released DMA channel 3 terminal count 192 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 6 Transfer Types 7 6 1 Two cycle transfer In two cycle transfer data transfer is performed in two cycles a read cycle source to DMAC and a write cycle DMAC to destination In the first cycle the source address is output and reading is performed from the source to the DMAC In the second cycle the transfer destination address is output and writing is performed from the DMAC to the transfer destination Caution A one clock idle period is always inserted between a read cycle and a write cycle 7 7 Transfer Object 7 7 4 Transfer type and transfer object Table 7 1 Relationship Between Transfer Type and Transfer Object on page 193 lists the relation ships between transfer type and transfer object Table 7 1 Relationship Between Transfer Type and Transfer Object Destination Two Cycle Transfer On Chip Peripheral I O External I O Internal RAM External Memory On chip peripheral I O External I O Internal RAM External memory Caution Addresses between 3FFF000H and 3FFFFFFH cannot b
115. xxxxn124H CAN message data length register 09 M DLCO9 Undefined xxxxn125H CAN message control register 09 M CTRL09 Undefined xxxxn126H CAN message time stamp register 09 M TIMEO9 Undefined xxxxn128H CAN message data register 090 M DATAO90 Undefined xxxxn129H CAN message data register 091 M DATA091 Undefined xxxxn12AH CAN message data register 092 M_DATA092 Undefined xxxxn12BH CAN message data register 093 M_DATA093 Undefined xxxxn12CH CAN message data register 094 M_DATA094 Undefined xxxxn12DH CAN message data register 095 M DATAO95 Undefined xxxxn12EH CAN message data register 096 M DATA096 Undefined xxxxn12FH CAN message data register 097 M_DATA097 X XIXI XIX XxX Xx Xx Undefined xxxxn130H CAN message ID register L09 M IDLO9 Undefined xxxxn132H CAN message ID register H09 M IDH09 Undefined xxxxn134H CAN message configuration register 09 M CONFO9 Undefined xxxxn135H CAN message status register 09 M STATO9 Undefined xxxxn136H CAN status set cancel register 09 SC STATO9 0000H xxxxn140H CAN message event pointer 100 M EVT100 Undefined xxxxn141H CAN message event pointer 101 M EVT101 Undefined xxxxn142H CAN message event pointer 102 M EVT102 Undefined xxxxn143H CAN message event pointer10
116. 0 When autofill is complete this bit is cleared 0 auto matically 0 Way 0 fill complete 1 Way 0 fill operating This bit sets way 1 tag clear Setting 1 this bit clears invalidates way 1 tags When tag clear is complete this bit is cleared 0 automatically 0 Way 1 tag clear complete 1 Way 1 tag clear operating This bit sets way 0 tag clear Setting 1 this bit clears invalidates way 0 tags When tag clear is complete this bit is cleared 0 automatically 0 Way 0 tag clear complete 1 Way 0 tag clear operating Note During reset active the value of this register becomes 0003H and tag initialization begins auto matically Upon completion of tag initialization the value changes to OOOOH Cautions 1 If any of bits 0 1 or 4 is set do not forcibly clear that bit 2 Do not set bit 4 at the same time as the other bits 3 Do not set bit 12 Bit 12 can only be cleared 4 Make ICC register settings running code from an uncacheable area except for setting bit 4 158 Preliminary User s Manual U15839EE1VOUMOO Chapter6 Instruction Cache 2 Instruction Cache Data Configuration Register ICD The ICD register sets the address of the memory area to be autofilled when using the autofill func tion The ICD register can be read or written in 16 bit units Figure 6 4 Instruction Cache Data Configuration Register ICD Initial 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address value oo o BRATS
117. 0000H xxxxn160H CAN message event pointer 110 M EVT110 Undefined xxxxn161H CAN message event pointer1 1 1 M EVT111 Undefined xxxxn162H CAN message event pointer 112 M EVT112 Undefined xxxxn163H CAN message event pointer 113 M EVT113 Undefined xxxxn164H CAN message data length register 11 M DLC11 Undefined xxxxn165H CAN message control register 11 M CTRL11 Undefined xxxxn166H CAN message time stamp register 11 M_TIME11 Undefined xxxxn168H CAN message data register 110 M_DATA110 Undefined xxxxn169H CAN message data register 111 M DATA111 Undefined xxxxn16AH CAN message data register 112 M DATA112 Undefined xxxxn16BH CAN message data register 113 M DATA113 Undefined xxxxn16CH CAN message data register 114 M DATA114 Undefined xxxxn16DH CAN message data register 115 M DATA115 Undefined xxxxn16EH CAN message data register 116 M DATA116 Undefined xxxxn16FH CAN message data register 117 M DATA117 Undefined xxxxn1 70H CAN message ID register L11 M_IDL11 Undefined xxxxn1 72H CAN message ID register H11 M IDH11 Undefined xxxxn174H CAN message configuration register 11 M CONF11 Undefined xxxxn175H CAN message status register 11 M STAT11 Undefined xxxxn176H CAN status s
118. 14 13 12 11 10 9 7 6 5 4 3 2 1 0 Address ial value Remarks 1 The TMCO register can only be read If writing is performed to the TMCO register the subsequent operation is undefined 2 If the CAE bit of the TMCCOO register is cleared to 0 a reset is performed asynchronously TMCO performs the count up operations of an internal count clock Timer starting and stopping are controlled by the CE bit of Timer C control register 0 TMCCOO 274 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer Selection of the internal count clock TMCO operates as a free running timer TMCO is counted up for each input clock cycle specified by the CS2 to CSO bits of the TMCCOO register A division by the prescaler can be selected for the count clock from among fpciK 2 fpcik 4 feci 8 16 32 64 feci 28 and 256 by the TMCCOO register Remark fpork internal peripheral clock An overflow interrupt can be generated if the timer overflows Caution The count clock cannot be changed while the timer is operating The conditions when the TMCO register becomes 0000H are a Asynchronous reset CAE bit of TMCCOO register 0 RESET input b Synchronous reset CE bit of TMCCOO register 0 The CCCOO register is used as a compare register and the TMCO and CCCOO0 registers match when clearing the TMCO register is enabled CCLR bit of the TMCCO 1 register 1 Prelimi
119. 145 M DATA145 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn1CEH CAN message data register 146 M DATA146 Undefined xxxxn1CFH CAN message data register 147 M DATA147 Undefined xxxxn1DOH CAN message ID register L14 M IDL14 Undefined xxxxn1D2H CAN message ID register H14 M IDH14 Undefined xxxxn1D4H CAN message configuration register 14 M CONF14 Undefined xxxxn1D5H CAN message status register 14 M STAT14 Undefined xxxxn1D6H CAN status set cancel register 14 SC STAT14 0000H xxxxn1EOH CAN message event pointer 150 M EVT150 Undefined xxxxn1E1H CAN message event pointer 151 M EVT151 Undefined xxxxn1E2H CAN message event pointer 152 M EVT152 Undefined xxxxn1E3H CAN message event pointer 153 M_EVT153 Undefined xxxxn1E4H CAN message data length register 15 M DLC15 Undefined Xxxxn1E5H CAN message control register 15 M CTRL15 Undefined Xxxxn1E6H CAN message time stamp register 15 M TIME15 Undefined xxxxn1E8H CAN message data register 150 M DATA150 Undefined xxxxn1E9H CAN message data register 151 M DATA151 Undefined xxxxn1 EAH CAN message data register 152 M_DATA152 Undefined xxxxn1 EBH CAN message data register 153 M_DATA153 Undefined xxxxn1ECH CAN message d
120. 3 2 1 0 Address Initial value Biens E pestes 1008 Bit Position Bit Name Function D RQNote DOF Note pes Sets the interrupt source that serves as the DMA start factor Interrupt Source Peripheral Source INTIN1 CSIO INTIN2 csi csl2 INTIN5 UARTO Transmission INTIN7 UART1 Transmission INTIN8 ADC INTIN13 TMGO 3 INTIN14 TMG1 3 Note DRQ and DOFL are set by hardware and reset by software Setting these bits by software is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR2 register set tings 2 Aninterrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor Preliminary User s Manual U15839EE1VOUMOO 181 Chapter 7 DMA Functions DMA Controller 7 2 11 DMA trigger factor register 3 DTFR3 This 8 bit registers is used to control the DMA transfer start trigger of DMA channel 3 through interrupt requests from on chip peripheral I O The interrupt requests set with these registers serve as DMA transfer start factors This register can be read written in 8 bit 1 bit units Figure 7 13 DMA Trigger Factor Registers 3 DTFR3 7 6 5 4 3 2 1 0 Address Initial value DTFR3 DOFL IFC2 IFC1 IFCO FFFFF846H 00H Bit Position Bit Na
121. 3 4n 5 8 8 8 8 7 7 7 7 4n 2 4n 4 0 0 0 0 Word data External Word data External data bus data bus lt 4 gt Access to address 4n 3 1 st Access 2 nd Access 31 31 24 24 23 23 16 Address 16 Address 15 15 15 15 4n 3 4n 5 8 8 8 8 7 7 1 7 7 Po 4 4 0 0 0 0 Word data External Word data External data bus data bus 3 rd Access 31 24 23 16 BA Address 15 155 8 8 7 7 4n 6 0 0 Word data External data bus Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function b When the bus width is 8 bits Little Endian 1 Access to address 4n 1 st Access 2 nd Access 31 31 24 24 23 23 16 16 15 15 8 Address 8 Address 7 7 7 7 4n 4n 1 0 0 0 0 Word data External Word data External data bus data bus 2 Access to address 4n 1 1 st Access 2 nd Access 31 31 24 24 23 23 16 16 15 15 8 Address 8 Address d 7 7 7 4n 1 4n 2 0 0 0 0 Word data External Word data External data bus data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 2 0 0 Word data External data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 3 0 0 Word data External data bus Preliminary User s Manual U15839EE1VOUMOO 4 th Access 31 24 23 16 15 8 Address 7 7 4n 0 0 Word data External data bus 4 th Access 31 24 23 16 15 8 Address 7 7 4n 4 0 0 Word data External data bus 125 Chapter 4 Bus Control Function 3 Access to address 4n
122. 4 3 2 1 0 Address Initial value 3to0 to Reflects the contents of the ENn bit of the DCHCn register during NMI input The con CHO tents of this register are held until the next NMI input or until the system is reset Remark nz0to3 7 2 7 DMA restart register DRST This register is used to restart DMA transfer that has been forcibly interrupted by a non maskable inter rupt NMI The ENn bit of this register and the ENn bit of the DCHCn register are linked to each other Following forcible interrupt by NMI input the DMA channel that was interrupted is confirmed from the contents of the DDIS register and DMA transfer is restarted by setting the ENn bit of the corresponding channel to 1 This register can be read written in 8 bit or 1 bit units Figure 7 9 DMA Restart Register DRST 7 6 5 4 3 2 1 0 Address Initial value Bit Position Bit Name Function Specifies whether DMA transfer through DMA channel n is to be enabled or disabled This bit is cleared to 0 when DMA transfer is completed in accordance with the termi nal count output It is also cleared to 0 when DMA transfer is forcibly terminated by setting the INITn bit to 1 or by NMI input 0 DMA transfer disabled 1 DMA transfer enabled Remark nz0to3 178 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 2 8 DMA trigger factor register 0 DTFRO This 8 bit registers is used to control the DMA transfer s
123. 500 us to 16 4 s by using the clock selector for the Watch Timer see Chapter 8 2 Configuration on page 198 2 Interval timer The interval timer generates an interrupt request INTWTI at time intervals of 500 us to 2 1 s Preliminary User s Manual U15839EE1VOUMOO 349 Chapter 11 Watch Timer 11 2 Configuration The watch timer consists of the following hardware Table 11 1 Configuration of Watch Timer Item Configuration Counter 5 bits x 1 Prescaler 11 bits x 1 Control register Watch timer mode control register WTM 11 3 Watch Timer Control Register The watch timer mode control register WTM controls the watch timer 1 Watch timer mode control register WTM This register enables or disables the count clock and operation of the watch timer sets the interval time of the prescaler controls the operation of the 5 bit counter and sets the set time of the watch flag WTM is set by a 1 bit or 8 bit memory manipulation instruction Figure 11 2 Watch Timer Mode Control Register WTM 1 2 7 6 5 4 3 2 1 0 Address Rw After Reset WTM7 Selects main input frequency from prescaler 0 Clock input fcksg is selected 1 Clock input fcksg 2 is selected Selects Interval Time of Prescaler fy 4 MHz 350 Preliminary User s Manual U15839EE1VOUMOO Chapter 11 Watch Timer Figure 11 2 Watch Timer Mode Control Register WTM 2 2 Selects Set Time of Watch Flag
124. ANI11 Successive approximation register SAR A D conversion result register ADCR A D conversion result register ADCRL only lower 2 bits of A D conversion result can be read A D conversion result register ADCRH only higher 8 bits of A D conversion result can be read Register A D converter mode register ADM Analog input channel setting register ADS Control register 1 Input circuit The input circuit selects an analog input channel ANIm according to the mode set in the ADM register and sends it to the sample and hold circuit m 2 O to 11 2 Sample and hold circuit The sample and hold circuit samples the analog input sent from the input circuit and sends it to the comparator It holds the sampled analog input during A D conversion 3 Voltage comparator The voltage comparator compares the analog input voltage from the input with the output voltage of the D A converter 4 D A converter The D A converter is used to generate a voltage that matches an analog input The output voltage of the D A converter is controlled by the successive approximation register SAR 5 Successive approximation register SAR The SAR is a 10 bit register that controls the output value of the D A converter for comparing with an analog input voltage value When an A D conversion terminates the current contents of the SAR conversion result are stored in the A D conversion result register ADCR ADCRL ADCRH Whe
125. C1INTP CAN1 interrupt pending register bit clear function only C2INTP interrupt pending register bit clear function only C3INTP CANG interrupt pending register bit clear function only CAINTP interrupt pending register S D d S D S D d m bit clear function only Note The address of an interrupt pending register is calculated according to the following formula effective address PP_BASE address offset 432 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 3 CAN Common Registers Section The layout of the common register section is shown in Table 14 4 Table 14 4 Relative Addresses of CAN Common Registers Access Type Address Note Offset R W 1 bit 8 bits Comment CAN stop register CAN global status register bit set clear function CAN global interrupt enable register bit set clear function CAN main clock select register only if GOM bit 0 CAN timer event enable register CAN global time system counter complete clear only CAN message search start register write only CAN message search result register read only CAN test bus register Note The address of an interrupt pending register is calculated according to the following formula effective address PP_BASE address offset Preliminary User s Manual U15839EE1VOUMOO 433
126. CAN message event pointer 202 M_EVT202 Undefined Xxxxn283H CAN message event pointer 203 M_EVT203 Undefined Xxxxn284H CAN message data length register 20 M_DLC20 Undefined Xxxxn285H CAN message control register 20 M_CTRL20 Undefined Xxxxn286H CAN message time stamp register 20 M_TIME20 Undefined Xxxxn288H CAN message data register 200 M_DATA200 Undefined Xxxxn289H CAN message data register 201 M_DATA201 Undefined Xxxxn28AH CAN message data register 202 M_DATA202 Undefined xxxxn28BH CAN message data register 203 M DATA203 Undefined xxxxn28CH CAN message data register 204 M DATA204 Undefined xxxxn28DH CAN message data register 205 M DATA205 Undefined xxxxn28EH CAN message data register 206 M DATA206 Undefined xxxxn28FH CAN message data register 207 M DATA207 Undefined Xxxxn290H CAN message ID register L20 M_IDL20 Undefined Xxxxn292H CAN message ID register H20 M_IDH20 Undefined Xxxxn294H 94 CAN message configuration register 20 M_CONF20 Preliminary User s Manual U15839EE1VOUMOO Undefined Xxxxn295H Chapter 3 CPU Function Table 3 7 List of programmable peripheral VO registers 11 18 Function Register Name CAN message status register 20 M_STAT20 Bit Units for Manipulat
127. CCCOOIC CCCOOIF CCCOOMK CCCOOPR2 CCCOOPRI1 CCCOOPRO FFFFF148H CCCO01IC CCCO01IF CCCO1MK CCC01PR2 CCCO01PR1 CCCO01PRO FFFFF14AH ADIC ADIF ADMK ADPR2 ADPR1 ADPRO FFFFF14CH MACIC MACIF MACMK MACPR2 MACPR1 MACPRO FFFFF14EH FC1RXIC FC1RXIF FC1RXMK FC1RXPR2 FC1RXPR1 FC1RXPRO FFFFF150H FC1TXIC FC1TXIF FC1TXMK FC1TXPR2 FC1TXPR1 FC1TXPRO FFFFF152H FC1ERIC FC1ERIF FC1ERMK FC1ERPR2 FC1ERPR1 FC1ERPRO FFFFF154H FC2RXIC FC2RXIF FC2RXMK FC2RXPR2 FC2RXPR1 FC2RXPRO FFFFF156H FC2TXIC FC2TXIF FC2TXMK FC2TXPR2 FC2TXPR1 FC2TXPRO FFFFF158H FC2ERIC FC2ERIF FC2ERMK FC2ERPR2 FC2bERPR1 FC2ERPRO FFFFF15AH FC3RXICNOTE FC3RXIF FC3RXMK FC3RXPR2 FC3RXPR1 FC3RXPRO FFFFF15CH FC3TXICNOTE FC3TXIF FC3TXMK FC3TXPR2 FC3TXPR1 FC3TXPRO FFFFF15EH FCSERICNOTE FC3ERIF FC3ERMK FC3ERPR2 FC3ERPR1 FC3ERPRO FFFFF160H FC4RX FC4RXIF FC4RXMK FC4RXPR2 FC4RXPR1 FC4RXPRO FFFFF162H FC4TX FC4TXIF FC4TXMK FC4TXPR2 FC4TXPR1 FC4TXPRO FFFFF164H FC4ER FC4ERIF FC4ERMK O O OoO oo o olo o oj o o oj ojo oo oiojo oo o o o o o o oj ojo olooojioj oio o o o o o Oloiooo oj o j ojo ojoj ojoj ooo o o o oj oj o o ooolo oj o oijioio o o ioiloiojo o o oo o
128. CS mode control 01H FFFF Port CT mode control 10H FFFF F04C Port CM mode control PMCCM x 01H FFFF F060 CPU Chip Area Select Control register 0 CSCO R W x 2C11H FFFF F062 CPU Chip Area Select Control register 1 CSC1 R W x 2C11H FFFF F064 CPU Peripheral Area Select Control register BPC R W x OFFFH FFFF F066 CPU Bus Size Configuration register BSC R W x 5555H FFFF F068 CPU Endian Configuration register BEC R W x 0000H FFFF F06A CPU Cache Configuration register BHC R W x 0000H FFFF FOGE CPU VPB Strobe Wait Control register VSWC R W x x 77H FFFF F070 Instruction Cache Control Register ICC R W x 0003H FFFF F072 Instruction Cache Index Register ICI RAN x FFFFH FFFF F074 Instruction Cache Data Configuration ICD R W x undefined FFFF F080 DMA source address register OL DSALO R W x undefined FFFF F082 DMA source address register OH DSAHO R W x undefined FFFF F084 DMA destination address register OL DDALO R W x undefined FFFF F086 DMA destination address register OH DDAHO R W x undefined FFFF F088 DMA source address register 1L DSAL1 R W x undefined FFFF F08A DMA source address register 1H DSAH1 R W x undefined FFFF F08C DMA destination address register 1L DDAL1 R W x undefined FFFF FO8E DMA destination address register 1H DDAH1 R W x undefined FFFF F090 DMA source address register 2L DSAL2 R W x undefined FFFF F092 DMA source address register 2H DSAH2 R W x undefined FFFF F094 DMA destination address register 2L
129. CSIMn register 0 Preliminary User s Manual U15839EE1VOUMOO 397 Chapter 13 Serial Interface Function 3 Clocked serial interface reception buffer registers SIRBO to SIRB2 The SIRBn register is a 16 bit buffer register that stores receive data n 0 to 2 When the receive only mode is set TRMD bit of CSIMn register 0 the reception operation is started by reading data from the SIRBn register These registers are read only in 16 bit units In addition to reset input these registers can also be initialized by clearing 0 the CSIE bit of the CSIMn register Figure 13 24 Clocked Serial Interface Reception Buffer Registers SIRBO to SIRB2 Initial value SIRBO SIRB15 SIRB14 SIRB13 SIRB12 SIRB11 SIRB10 SIRB9 SIRB8 SIRB7 ISIRB6 SIRBS SIRB4 SIRB3 SIRB2 SIRB1 SIRBO FFFF FD02H 0000H se SRT pen v eo SBS Sr re SOP FF eon see rene esf m er Senes fen pe Terre ron n 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Biss Eran SIRB15 to i 15100 SIRBO Store receive data Cautions 1 Read the SIRBn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOT bit of CSIMn register O If the SIRBn register is read during data transfer the data cannot be guaranteed 398 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interf
130. CT Mode Control Register PMCCT Address At Reset 7 6 5 4 3 2 1 0 Specifies operation mode of PMCCTA pin PMCCT4 0 Input output port mode 1 RD Read strobe signal output Specifies operation mode of PMCCT1 pin PMCCT1 0 Input output port mode 1 UWR Upper write strobe signal output Specifies operation mode of PMCCTO pin PMCCTO 0 Input output port mode 1 LWR Lower write strobe signal output 580 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 13 Port CM Port CM is an 1 bit input output port in which input or output can be specified in 1 bit units After reset port pin PCMO operates as the wait insertion input WAIT This port bit can be configured to port input port output or peripheral functionNete 1 This register can be read in 1 bit and 8 bit units Figure 16 38 Port CM PCM Address At Reset 7 6 5 4 3 2 1 0 PCMO Input output port Remark In Input Mode When the PCM register is read the pin levels at that time are read Writing to the PCM register writes the values to that register This does not affect the input pins In Output Mode When the PCM register is read the values of PCM are read Writing to the PCM register writes the values to that register and those values are immediately output Besides functioning as a port in control mode PCMO can operate as the wait insertion signal input when external slow memory peripherals are connected Notes 1 lf usin
131. CTPC Status saving register during CALLT execution CTPSW Status saving register during exception debug trap DBPC Status saving register during exception debug trap DBPSW CALLT base pointer CTBP Reserved number for future function expansion operations that access these register numbers cannot be guaranteed Notes 1 Because this register has only one set to approve multiple interrupts it is necessary to save this register by program 2 Accessis only possible while the DBTRAP instruction is executed Caution Even if bit 0 of EIPC FEPC or CTPC is set to 1 with the LDSR instruction bit 0 will be ignored when the program returned by RETI instruction after interrupt servicing because bit 0 of the PC is fixed to 0 When setting the value of EIPC FEPC or CTPC use the even value bit 0 0 Remark Access allowed x Access prohibited 58 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function Figure 3 3 Interrupt Source Register ECR 31 1615 0 After reset FECC EICC 00000000H 31 to 16 FECC Exception code of non maskable interrupt NMI 15100 EICC Exception code of exception maskable interrupt Preliminary User s Manual U15839EE1VOUMOO 59 Chapter 3 CPU Function Figure 3 4 Program Status Word PSW After reset RSW 00000020H Bit Position Function Reserved field fixed to 0 Indicates that non maskable interrupt NMI processing is in pr
132. Chann Timer G0 qe CC coincidence Chann Timer G0 o 9 9 nterrupt INTGCC05 GCC05 000001 nextPC nterrupt INTTMG10 TMG10 000001 nextPC nterrupt INTTMG11 TMG 11 000001 nextPC nterrupt INTGCC10 GCC10 000001 nextPC nterrupt INTGCC11 GCC11 000001 nextPC nterrupt GCC12 000001 next PC nterrupt 13106613 000001 1410661416 coincidence Chann Timer G1 00000200H next PC nterrupt 15 GCC15IC coincidence Chann Timer G1 00000210H next PC nterrupt INTTMCO TMCOIC Time base Overflow Timer C0 00000220H next PC Notes 1 0 FH 2 INTFC3RX INTFC3TX INTFC3ER INTFC4RX and INTFCAER are available only in the derivatives PD703129 and uPD703129 A1 N CC coincidence Chann Timer G0 oo Time base 0 Overflow Timer G1 co Time base 1 Overflow Timer G1 n CC coincidence Chann Timer G1 gt CC coincidence Chann Timer G1 n gt CC coincidence Chann Timer G1 n2 CC coincidence Chann Timer G1 DO gt gt 200 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function Table 8 1 Interrupt Exception Source List 2 3 Di Interrupt Exception Source Classifi
133. D15 I O WAIT input Jj uU fF v Remarks 1 The circles O indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 140 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function Figure 5 2 SRAM External ROM External VO Access Timing 3 6 c During write T1 T2 T1 TW T2 CSn output RD output UWR output WO om p WAIT input Remarks 1 The circles Oindicate the sampling timing DO to D15 I O 2 The broken line indicates the high impedance state CS0 CS3 and CS4 Preliminary User s Manual U15839EE1VOUMOO 141 Chapter 5 Memory Access Control Function Figure 5 2 SRAM External ROM External l O Access Timing 4 6 d During write address setup wait idle state insertion TASW T1 T2 TI CSn output RD output UWR output DO to D15 I O WAIT input Remarks 1 The circles O indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 142 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function Figure 5 2 SRAM External ROM External VO Access Timing 5 6 e When read write operation T1 T2 T1 T2 CSn output UWR output DO to D15 I O
134. Data Wait Control register 1 DWC1 R W x 7777H FFFF F488 MEMC Bus Cycle Control register BCC R W x FFFFH FFFF F48A MEMC Address Setup Wait Control Reg ASC R W x FFFFH FFFF F49A Page ROM Configuration register PRC R W x 7000H FFFF F540 Timer DO counter TMDO R x 0000H FFFF F542 Timer DO compare register CMDO R W x 0000H FFFF F544 DO Control register TMCDO R IW x x 00H FFFF F550 Timer D1 counter TMD1 R x 0000H FFFF F552 D1 compare register CMD1 R W x 0000H Preliminary User s Manual U15839EE1VOUMOO 79 Address Chapter 3 CPU Function Table 3 6 List of Peripheral I O Registers 5 7 Function Register Name Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value FFFF F554 Timer D1 Control register TMCD1 R W x x 00H FFFF F560 Watch timer mode register WTM R W x x 00H FFFF F571 Watchdog timer time select register WDCS R W x x 00H FFFF F572 Watchdog timer mode register WDTM R W x 00H FFFF F580 Watchdog Timer command register WCMD undefined FFFF F582 Watchdog Timer command status register WPHS R W x x 00H FFFF F600 Timer CO timer counter register TMCO R x 0000H FFFF F602 Timer CO capture compare register 0 CCCO0O0 R W x 0000H FFFF F604 Timer CO capture compare register 1 CCCO01 R W x 0000H FFFF F606 Tim
135. Default Exception Handler cation Controlling Generating Source Generating Priority Code Address Register Unit terrupt INTCCCOO CCCOIC coincidence Channel 0 Timer C0 00000230H terrupt INTCCCO1 CCC1IC ICC coincidence Channel 1 Timer C0 00000240H terrupt INTAD ADIC A D conversion end A D 00000250H terrupt INTMAC MACIC MAC Interrupt CGINTP 1 2 FCAN MAC 00000260H N ine 1 terrupt INTFC1RX FC1RXIC CAN1 Receive Interrupt 00000270H terrupt INTFC1TX FC1ITXIC CAN1 Transmit Interrupt ine 1 00000280H terrupt INTFC1ER FC1ERIC CAN1 Error Interrupt nea 00000290H terrupt INTFC2RX FC2RXIC 2 Receive Interrupt ine 2 000002A0H terrupt INTFC2TX FC2TXIC Transmit Interrupt ine 2 000002B0H terrupt INTFC2ER FC2ERIC 2 Error Interrupt ine 2 000002C0H nterrupt INTFC3RX FC3RXIC CAN3 Receive Interrupt 000002D0H Note 2 ne 3 eae NTFC3TX FC3TXIC CAN3 Transmit Interrupt 000002E0H NTFC3ER FC3ERIC CAN3 Error Interrupt 000002F0H NTFC4RX FC4RXIC CAN4 Receive Interrupt 00000300H MD NTFCATX FCATXIC Transmit Interrupt 00000310H NTFC4ER FC4ERIC CAN4 Error Interrupt 00000320H Transmission Reception Interrupt INTCSIO CSIOIC Completion 00000330H Transmission Reception terrupt INTCSH CSHIC 00000340H Transmission
136. EVT283 Undefined xxxxn384H CAN message data length register 28 M DLC28 Undefined xxxxn385H CAN message control register 28 M CTRL28 Undefined xxxxn386H CAN message time stamp register 28 M TIME28 Undefined Xxxxn388H CAN message data register 280 M_DATA280 Undefined Xxxxn389H CAN message data register 281 M_DATA281 Undefined Xxxxn38AH CAN message data register 282 M_DATA282 Undefined Xxxxn38BH CAN message data register 283 M_DATA283 Undefined xxxxn38CH CAN message data register 284 M DATA284 Undefined xxxxn38DH CAN message data register 285 M DATA285 Undefined xxxxn38EH CAN message data register 286 M DATA286 Undefined xxxxn38FH CAN message data register 287 M DATA287 Undefined xxxxn390H CAN message ID register L28 M IDL28 Undefined xxxxn392H CAN message ID register H28 M IDH28 Undefined xxxxn394H CAN message configuration register 28 M CONF28 Undefined xxxxn395H CAN message status register 28 M STAT28 Undefined xxxxn396H CAN status set cancel register 28 SC STAT28 0000H xxxxn3A0H CAN message event pointer 290 M_EVT290 Undefined xxxxn3A1H CAN message event pointer 291 M EVT291 Undefined Xxxxn3A2H CAN message event pointer 292 M_EVT292 Undefined Xxxxn3A3H
137. FFFF F104 Interrupt Mask register 2 FFFFH FFFF F106 Interrupt Mask register 3 IMR3 RW x x FFFFH FFFF F110 Interrupt control register 0 WTIC RW x x 47H FFFF F112 Interrupt control register 1 TMDOIC RW x x 47H FFFF F114 Interrupt control register 2 TMD1IC RW x x 47H FFFF F116 Interrupt control register WTIIC RW x x 47H FFFF F118 Interrupt control register 4 POIC RW x x 47H FFFF F11A Interrupt control register 5 P1IC RW x x 47H FFFF F11C Interrupt control register 6 P2IC RW x x 47H FFFF F11E Interrupt control register 7 P3IC RW x x 47H FFFF F120 control register 8 RW x x 47H FFFF F122 Interrupt control register 9 P5IC RW x x 47H FFFF F124 Interrupt control register 10 TMGOOIC R W x x 47H FFFF F126 Interrupt control register 11 TMGO1IC R W x x 47H FFFF F128 Interrupt control register 12 CCGOOIC R W x x 47H FFFF F12A Interrupt control register 13 CCGO1IC R W x x 47H FFFF F12C Interrupt control register 14 CCGO2IC R W x x 47H FFFF F12E Interrupt control register 15 CCGO3IC x x 47H FFFF F130 Interrupt control register 16 CCGO04IC R W x x 47H FFFF F132 Interrupt control register 17 CCGO5IC R W x x 47H FFFF F134 Interrupt control register 18 TMG10IC R W x x 47H FFFF F136 Interrupt control register 19 TMG11IC RIW x x 47H FFFF F138 Interrupt control register 20 CCG101C R W x x 47H FFFF F13A Interrupt control register 21 CCG11IC x x 47H FFFF F13C Interr
138. Figure 13 33 Serial Shift Registers Low SIOLO to SIOL2 Initial value SIOLO SIO7 5100 FFFFFDOAH 7 6 5 4 3 2 1 0 Address 7100 Fa to Data is shifted in reception or shifted out transmission from the MSB or 5100 LSB side Caution Access the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOT bit of CSIMn register 0 If the SIOLn register is accessed during data transfer the data cannot be guaranteed Preliminary User s Manual U15839EE1VOUMOO 407 Chapter 13 Serial Interface Function 13 3 4 Operation 1 Single transfer mode a Usage In the receive only mode TRMD bit of CSIMn register 0 transfer is started by readingN t 1 the receive data buffer register SIRBn SIRBLn n 0 to 2 In the transmission reception mode TRMD bit of CSIMn register 1 transfer is started by writingNete 2 to the transmit data buffer register SOTBn SOTBLn In the slave mode the operation must be enabled beforehand CSIE bit of CSIMn register 1 When transfer is started the value of the CSOT bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSIOn is set 1 and the CSOT bit is cleared 0 The next data transfer request is then waited for Notes 1 When the 16 bit data length CCL bit of CSIMn register 1 has been set read the SIR
139. Frame Handling upon Reception into a Transmit Message Buffer M CTRLm setting Resulting Automatic Remote Frame Handling RMDEO RMDE1 RTR DN flag other actions x 0 no change ignore remote frame Clear when transmit message buffer send transmit message buffer data sent successfully frame as an automatic answer no change Note DN is set upon reception Clear when transmit message buffer send transmit message buffer data sent successfully frame as an automatic answer DN is set upon reception Note Note Auto answer upon remote frame is suppressed because the transmit message buffer is config ured to send a remote frame RTR 1 Remarks 1 In case a remote frame is automatically answered upon receiving a remote frame for a transmit message buffer the reception of the remote frame is not notified by a receive interrupt However the successful transmission of the data frame i e the automatic answer is notified by the corresponding transmit interrupt 2 m 00 to 31 Preliminary User s Manual U15839EE1VOUMOO 451 Chapter 14 FCAN Interface Function 14 3 Control and Data Registers 14 3 1 Bit set clear function Direct writing of data bit operations read modify write direct writing of a target value is not allowed to few specific registers where bit setting and bit clearing might be performed by CPU and by the FCAN system The following registers of the FCAN system are
140. INT6JE INTSE INT4 E INT3 E INT2 E INT1JE INTO E INT6JE INTSE INT4E INT3 E INT1JE INTO 10088 C4IE 1118H Note The register address is calculated according to the following formula effective address PP BASE address offset 498 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 38 CAN 1 to 4 Interrupt Enable Registers to C4IE 2 3 Read Enables CAN module error interrupt INT6 0 Interrupt disabled 1 Interrupt enabled Enables CAN bus error interrupt INT5 0 Interrupt disabled 1 Interrupt enabled Enables wake up from CAN sleep mode interrupt INT4 0 Interrupt disabled 1 Interrupt enabled Enables interrupt for error passive on reception INT3 0 Interrupt disabled 1 Interrupt enabled Enables interrupt for error passive or bus off on transmission INT2 0 Interrupt disabled 1 Interrupt enabled Enables reception successful completion interrupt INT1 0 Interrupt disabled 1 Interrupt enabled Enables transmission completion interrupt INTO 0 Interrupt disabled 1 Interrupt enabled Preliminary User s Manual U15839EE1VOUMOO 499 Chapter 14 FCAN Interface Function Figure 14 38 CAN 1 to 4 Interrupt Enable Registers to C4IE 3 3 Write Sets clears the E INT6 bit CL E INT6 Status of E INT6 bit 1 E INT6 bit is cleared 0 0 E
141. INTP15 P45 Input mode P50 CRXD4Note P50 Input mode P51 CTXD4Note P51 Input mode P52 INTP4 P52 Input mode P5S3 INTP5 P54 TIO INTP20 P54 Input mode P55 TH INTP21 P53 Input mode P55 Input mode P56 TOO P55 Input mode Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and PD703129 A1 548 only Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions Table 16 2 Port Pin Functions 2 3 Mode Setting Register Port Name Pin Name Pin Function after Reset P60 NMI P60 Input mode P61 IINTPO P61 Input mode P62 INTP1 P62 Input mode P63 INTP2 P63 Input mode P64 INTP3 P64 Input mode P65 SI2 P65 Input mode P66 SO2 P66 Input mode P67 SCKO2 SCKI2 P65 Input mode P70 ANIO P70 Input ANIO P71 ANI1 P71 Input ANI P72 ANI2 P72 Input ANI2 P73 ANI3 P73 Input ANI3 P74 ANI4 P74 Input ANI4 P75 ANI5 P75 Input ANI5 P76 ANI6 P76 Input ANI6 P77 ANI7 P77 Input ANI7 P80 ANI8 P80 Input ANI8 P81 ANI9 P81 Input ANI9 P82 ANI10 P82 Input ANI10
142. List 7 7 Instruction Group Operand Opcode Operation 00000111 1100000 PSW ID 1 000000010 Maskable interrupt disabled 1100000 10000111 1100000 PSW ID 0 000000010 Maskable interrupt enabled 1100000 000000000 Uses 1 clock cycle without doing 0000000 anything Notes 1 ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Only the lower half word data is valid ddddddddddddddddddddd is the higher 21 bits of dip22 dddddddd is the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification Preliminary Users Manual U15839EE1VOUMOO 599 MEMO 600 Preliminary User s Manual U15839EE1VOUMOO Appendix B Index Numerics 2 way associative instruction memory 155 A A D conversion result register 525 531 A D conversion termination 536 A D Converter Mode Register 528 A D converter mode register
143. Manual U15839EE1VOUMOO 2 Chapter 10 Timer Compare operation match and clear Basic settings m 1 to 4 CCSGOn match and CCSG5n clear mode SWFGm disable TOGnm Compare mode for GCCnm ccsGm assign counter for GCCnm 0 TMGnO 1 TMGn1 a Example Interval timer match and clear Setting Method An usable compare register is one of GCCn1 to GCCn4 and the corresponding counter must be selected with the TBGm bit Select a count clock cycle with the CSE12 to CSE10 bits TMGn1 CSE02 to CSEOO bits TMGnO Set an upper limit on the value of the counter in GCCn0 or GCCn5 Write data to GCCnm Start timer operation by setting the POWER bit and TMGxE bit x 0 1 Operation When the value of the counter matches the value of GCCnm a match interrupt INTCCGnm is output When the value of GCCnO or GCCn5 matches the value of the counter INTCCGnO INTCCGn5 is output and the counter is cleared This operation is referred to as match and clear The counter resumes count up operation starting with 0000H Preliminary User s Manual U15839EE1VOUMOO 337 Chapter 10 Timer Figure 10 51 Timing of compare operation match and clear ENFGO TMGnO GCCn1 INTCCGn1 INTCCGnO In this example the data N is set in GCCn1 and TMGn0 is selected OFFFH is set in GCCnO N lt OFFFH b When 0000H is set in GCCn0 or GCCn5 match and clear When OO
144. P15PR1 P15PRO P20PR2 P20PR1 P20PRO P21PR2 P21PR1 P21PRO 1 1 1 Oloj ojojoj oj oj ojojooiloojo jo o o o o o o Remark For the interrupt source to the respective controlling registers xxICn refer to Table 8 1 Interrupt Exception Source List on page 200 Note FC3RXIC FC3TXIC FC3ERIC FCARXIC FC4TXIC and FC4ERIC are available only in the derivatives uPD703129 A and uPD703129 A1 218 Preliminary User s Manual U15839EE1VOUMOO Chapter8 Interrupt Exception Processing Function 8 3 5 Interrupt mask registers 0 to 3 IMRO to IMR3 These registers set the interrupt mask state for the maskable interrupts The xxMK bit of the IMPO to IMR registers is equivalent to the xxMK bit of the xxIC register IMRm registers can be read written in 16 bit units m 0 to 3 When the IMRm register is divided into two registers higher 8 bits IMRmH register and lower 8 bits IMRmL register these registers can be read written in 8 bit or 1 bit units m 0 to 3 The address of the lower 8 bit register IMRmL is equal to that of the 16 bit IMRm register and the higher 8 bit register IMRmH can be accessed on the following address address IMRm 1 Figure 8 11 Interrupt Mask Registers 0 to 3 IMRO to IMR3 15 14 13 12 11 1
145. P97 can be set to input or output in 1 bit units using the port 9 mode register PM9 Preliminary User s Manual U15839EE1VOUMOO 9 10 Chapter 2 Pin Functions PAHO to PAH7 Port AH Input output Port AH is an 8 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in control mode this port operates as the address bus A16 to A23 for when memory is accessed externally An operation mode of port or control mode can be selected for each bit and specified by the port AH mode control register PMCAH a Port mode PAHO to PAH7 can be set to input or output in 1 bit units using the port AH mode register PMAH b Control mode PAHO to PAH7 can be used as A16 to A23 by using PMCAH c A16 to A23 Address Output This pin outputs the upper 8 bit address of the 24 bit address in the address bus on an external access PCSO PCS3 PCS4 Port CS Input output Port CS is a 3 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in control mode it operates as a chip select control signal output when memory is accessed externally An operation mode of port or control mode can be selected for each bit and specified by the port CS mode control register PMCCS a Port mode PCSO PCS3 PCS4 can be set to input or output in 1 bit units using the port CS mode register PMCS b Control mode PCSO PCS3 PCS4 can b
146. PC Interrupt request pendin PSW pt req g exception code 0 CPU processing 1 handler address Interrupt processing Note For the ISPR register see 8 3 6 In service priority register ISPR on page 220 An INT input masked by the interrupt controllers and an INT input that occurs while another interrupt is being processed when PSW NP 1 or PSW ID 1 are held pending internally by the interrupt control ler In such case if the interrupts are unmasked or when PSW NP 0 and PSW ID 0 as set by the RETI and LDSR instructions input of the pending INT starts the new maskable interrupt processing 210 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function 8 3 2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction When the RETI instruction is executed the CPU performs the following steps and transfers control to the address of the restored PC 1 Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0 2 Transfers control to the address of the restored PC and PSW Figure 8 7 illustrates the processing of the RETI instruction Figure 8 7 RETI Instruction Processing RETI instruction PC FEPC PSW PSW lt FEPSW Corresponding bit of ISPRNete Restores original processing Note For the ISPR
147. PCM 0 operate Remarks 1 N A This configuration is not available 2 Input data is not sampled Notes 1 during output during input 2 Output values must be set to recessive level by software before activating standby mode Otherwise CAN bus might be continuously blocked by dominant level 3 FCTXDA to FCTXD3 FCRXD4 to FCRXD3 only for uPD703129 Preliminary User s Manual U15839EE1VOUMOO 255 Chapter 9 Clock Generator 9 4 4 HALT mode In this mode the CPU clock is stopped though the clock generators oscillator SSCG and PLL synthe sizer continue to operate for supplying clock signals to other peripheral function circuits Setting the HALT mode when the CPU is idle reduces the total system power consumption In the HALT mode program execution is stopped but the contents of all registers and internal RAM prior are retained as is On chip peripheral hardware irrelevant to the CPU instruction execution also continues to operate The state of the various hardware units in the HALT mode is tabulated below Table 9 4 Operating states in HALT mode Items Operation Clock generator Operating SSCG PLL Operating Internal system clock Operating WT WDT clock Operating CPU Stopped but CPU clock still operates line Unchanged Peripheral function Operating TMC calibration input Main Clock available Retains all internal data before entering HALT mode such as C
148. Peripheral eriphera WRP nn Function 2 P Nn 1 oe 5 5 lt RDP Nn Address Peripheral _ Function Remark 1 to 6 9 Port number nz0to 7 Port pin for port number 1 2 6 9 0 6 Port pin for port number 5 n 20to3 Port pin for port number 3 4 Preliminary User s Manual U15839EE1VOUMOO 551 Peripheral Bus Chapter 16 Port Functions Figure 16 3 Type B Block Diagram WR O PMCAHn WR pan PAHn Selector o o e y 9 Remark 552 RD paun Address 0107 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions Figure 16 4 Type C Block Diagram MA WRewccsn PMCCSn WR o 29 e O PMCSn t N uni 2 8 5 PCSn o E 7 8 5 p O lt 3 E Ne RD pesn Address Remark n 0 3 4 Preliminary User s Manual U15839EE1VOUMOO 553 Peripheral Bus Chapter 16 Port Functions Figure 16 5 Type D Block Diagram WRewcctn PMCCTn Selector Remark 554 Selector Selector RD petn Address n 0 1 4 Preliminary User s Manual U15839EE1VOUMOO Peripheral Bus d Wr 2 BELA Selector Chapter 16 Port Function
149. Pin Functions 23 60 eee eae ae Seale EN ae ea eee 583 17 4 Reset by RESET Pin olei oui Rl Ti de REL ERA 585 17 5 Reset by Watchdog 587 17 6 ResetOutput eL l de deere dw ce eat See 587 17 7 Anttialization oi ee eee eee o oer Peete due Vee de 588 Appendix A List of Instruction Sets erne eee 589 Appendix B Index iir uix a RR AIR OCURRA RR E EORR eae RUN RR 601 12 Preliminary User s Manual U15839EE1VOUMOO Figure 1 1 Figure 1 2 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 List of Figures V850E CA2 Jupiter Pin Configuration ssssseseseeeenenennene enne 27 V850E CA2 Jupiter Block Diagram sssssss
150. REA BE eA aba at da 56 57 gerieral registers seine cad a cha EN KDE RR eral Feb Bal ee as RERO ELA RR At 55 57 Global poibteri EE MSN tae M me ente e 57 H Haltword access 16 bits visse iE e REX ER RISE tok E Seri dep Re ek e ARRA 121 FIA TMOG Ad us sec scie Ihe zum vri aep d 253 256 handler addresses 5 feed whee ds 70 hiQh Impedance state 2 20 ae Gated wane bain Gate dais 583 l aid taii ena e a nad a dio aaa a iu ealn 55 eet eA a aeri E T EE LR ER LLLI Lh Ste Anm unten tU m E 220 IDEE MOOO sis ume vene RUEDA S d ra SiG 258 IDEE moda ir hte ade a BE be de tee ee 253 idle StateS citu Bape d exta Rap e tea us 137 Illegal opeode definition TERT e aes Sand a nde bea ela eats 230 Images pg ener LA i p ERO e iT pe dade RE ERR CG Meg GATE gee ad 66 IMBPO TO TIME rm tik viet teat Gey geek Ed uer e e Seu mc ate tisch SH Ane METER wy Wee AT ede 219 Input eae tur LEE Ve WI aed Aig 541 In service priority 220 Instruction Cache 155 Instr
151. RTT pe pw o per pw or rope ow ree ui 0to 14 DATAO to Address of the memory area to be autofilled These bits specify the address bits 25 to DATA14 11 ofthe start address of the memory area to be autofilled Cautions 1 Do not overwrite the ICD register while autofill is operating 2 Since the initial value of the ICD register is undefined when using the autofill function be sure to set a value in the ICD register prior to setting the FILLO bit of the ICC register If the FILLO bit of the ICC register is set without setting a value in the ICD register the operation cannot be guaranteed 3 Instruction Cache Initial Register ICI The ICI register controls the iCache operation by the MODE bit The ICI register can be accessed by 16 bit access Figure 6 5 Instruction Cache Initial Register ICI 15 14 18 12 11 10 9 8 7 6 5 4 2 1 0 Address Initial value IGI SO MOBE EE EEOTORCIREH Bit Position Function MODE Instruction Cache Operation Mode Control bit Caution bits of the ICI register must be cleared immediately following a system reset The following procedure must be executed to clear the ICI register Example st h rO OxfffffO72 rO Preliminary Users Manual U15839EE1VOUMOO 159 Chapter 6 Instruction Cache 6 4 Instruction Cache Operation 1 Instruction Cache Basic Operation The instruction cache automatically performs a caching operation whenev
152. Rege e A APERIRE Linee Ee om Dd as 359 PAL MP C 360 Word access 32 bits 2e eee trn ad rernm n xo d ede rv e ees 123 WPS suet EA At Us VAI veneti RD ETE BQGES ED BU EI ded 361 Wrap arou nd que a e ede MeL EE 67 WAM AAE EAGRAN 350 X KA siet a Sette eos d piste totus 49 beets ute vty ook itte er DI Led i DL ADEM ME DE EE MA D MI UM ALIAE 49 2 ZOO TOST sedis sail EPIRI RR Lbs Y ed 57 Zero scale error wale did are WE ais EET ae gee ee ane te RE ERR RA Ner 543 Preliminary User s Manual U15839EE1VOUMOO 609 610 Preliminary User s Manual U15839EE1VOUMOO NEC Message From Name Company Tel FAX Although NEC has taken all possible steps to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may encounter problems in the documentation Please complete this form whenever you d like to report errors or suggest improvements to us Address North America Hong Kong Philippines Oceania NEC Electronics Inc NEC Electronics Hong Kong Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 1 800 729 9288 1 408 588 6130 Korea Europe i NEC Electronics Europe GmbH bn aos Hong Kong Ltd
153. Register 0 INTMO RIW x x 00H FFFF F882 Interrupt Mode Control Register 1 INTM1 RW x x 00H FFFF F884 Interrupt Mode Control Register 2 INTM2 RIW x x 00H FFFF F886 Interrupt Mode Control Register INTM3 RIW x x 00H FFFF FAOO UART operation mode register ASIMO RIW x x 01H FFFF FA02 Reception buffer register RXBO R x FFFF UART reception error status register ASISO R x 00H FFFF FA04 Transmission buffer register TXBO R W x FFH FFFF FA05 UART transmission error status register ASIFO R x 00H FFFF FAO6 Clock selection register CHKSRO RW x x pd 00H FFFF FA07 Baudrate definition register BRGCO RW x x FFH FFFF FA40 UART operation mode register ASIM1 RW x x 01H FFFF FA42 Reception buffer register RXB1 R x i FFH FFFF FA43 UART reception error status register ASIS1 R x 00H FFFF FA44 Transmission buffer register TXB1 R W x FFH FFFF FA45 UART transmission error status register ASIF1 R x 00H Preliminary User s Manual U15839EE1VOUMOO 81 Chapter 3 CPU Function Table 3 6 List of Peripheral I O Registers 7 7 Bit Units Address Function Register Name for Manipulation 1 bit 8 bit 16 bit Initial Value FFFF FA46 Clock selection register CHKSR1 FFFF FA47 Baudrate definition register BRGC1 FFFF FDOO CSI operation mode register CSIMO FFFF FD01 Clock selection register CSICO SIRBO 0000H SIRBLO 00H SOTBO 0000H SOTBLO 00H SOTBFO 0000H SOTBFLO 00H 5100 0000H SIOL
154. SIO2 The SIOn register is a 16 bit shift register that converts parallel data into serial data The SIOn register is used for both transmission and reception Data is shifted in reception and shifted out transmission from the MSB or LSB side The actual transmission reception operations are started up by access of the buffer register Serial I O shift registers Low SIOLO to SIOL2 The SIOLn register is an 8 bit shift register that converts parallel data into serial data The SIOLn register is used for both transmission and reception Data is shifted in reception and shifted out transmission from the MSB or LSB side The actual transmission reception operations are started up by access of the buffer register Clocked serial interface reception buffer registers SIRBO to SIRB2 The SIRBn register is a 16 bit buffer register that stores receive data Clocked serial interface reception buffer registers Low SIRBLO to SIRBL2 The SIRBLn register is an 8 bit buffer register that stores receive data Clocked serial interface read only reception buffer registers SIRBEO to SIRBE2 The SIRBEn register is a 16 bit buffer register that stores receive data The SIRBEn register is the same as the SIRBn register It is used to read the contents of the SIRBn register Clocked serial interface read only reception buffer registers Low SIRBELO to SIRBEL2 The SIRBELn register is 8 bit buffer register that stores receive data The SIR
155. Store instruction ST SST instruction Bit operation instruction SET1 CLR1 NOT1 instruction Please see the following example for initialization of a power save mode The PSC register is a specific register and therefore the PRCMD register has to be written first The following 5 NOPs are necessary for waken from the STOP mode Example 1 MOV 0x02 r10 2 STB r10 PRCMD rO 9 STB r10 PSC r0 lt 4 gt NOP dummy instruction 5 times NOP required No special sequence is required when reading the specific registers Remarks 1 A store instruction to a command register will not be received with an interrupt This presupposes that this is done with the continuous store instructions in lt 1 gt and lt 2 gt above in the program If another instruction is placed between lt 1 gt and lt 2 gt when an interrupt is received by that instruction the above sequence may not be established and cause a malfunction so caution is necessary The data written in the PRCMD register is dummy data but use the same general pur pose register for writing to the PRCMD register lt 2 gt in the example above as was used in setting data in the specified register lt 3 gt in the example above Addressing is the same in the case where a general purpose register is used In a store instruction to the PSC register for setting it in the software STOP mode or IDLE mode it is necessary to insert 1 or more NOP instructions just after When clear
156. TOGnm starts and continues outputting the active level immediately after the first match and clear event until count operation stops The figure shows the state of TOGn1 when OFFFH is set in GCCn0 1FFFH is set in GCCn1 and TMGn0 is selected Figure 10 56 Timing when the value of GCCnm exceeding GCCn0 or GCCn5 match and clear ENFGO TMGnO GCCni 1FFFH INTCCGn1 Low INTCCGnO TOGn1 ALVG1 1 TOGn1 ALVG1 0 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer When GCCnm is rewritten during operation match and clear When 1 is rewritten from 0555H to OAAAH the operation shown below is performed The figure below shows a case where OFFFH is set in GCCn0 and TMGnO is selected for GCCn1 Figure 10 57 Timing when GCCnm is rewritten during operation match and clear ENFGO TMGnO GCCn1 Slave register GCCn1 Master register 0555H INTCCGn1 INTCCGnO TOGn1 ALVG1 1 SSH ow TOGn ALVG1 0 If GCCn1 is rewritten to after the second INTCCGn 1 is generated as shown in the figure above OAAAH is reloaded to the GCCn1 register when the next overflow occurs The next match interrupt INTCCGn1 is generated when the value of the counter is The pulse width also matches accordingly Preliminary User s Manual U15839EE1VOUMOO 345 Chapter 10 Timer 10 3 9 Edge noise elimination
157. The operation mode is specified according to the status of pins MODEO to MODE2 In an application system fix the specification of these pins and do not change them during operation Operation is not guaranteed if these pins are changed during operation To program erase the contents of the external memory device it is required to enable a Flash Pro gramming Mode The following operation modes are generally available for the V850E CA2 Jupiter device PD703128 PD703129 Table 3 4 Operation Modes Operation Mode ROM less mode 0 Direct Normal operation mode ROM less mode 1 Low EMI Normal operation mode Flash memory programming mode 0 Direct Flash memory programming mode 1 Low EMI Other than above Setting prohibited Remarks 1 L Low level input 2 H High level input Preliminary User s Manual U15839EE1VOUMOO 63 1 2 3 Chapter 3 CPU Function ROM less Mode 0 When a system reset is released the bus interface pins enter the peripheral mode and the pro gram branches to the reset entry address in the external memory to start instruction execution Address output is masked by additional circuitry in the ROMLESS Mode 0 to reduce EMI Address is output only in case external access is performed Data and instructions in the internal boot ROM cannot be accessed or fetched ROM less Mode 1 When a system reset is released the bus interface pins enter the peripheral mode and
158. Tim edge clear mode interrupt match deleet n PWM CMPGm match match and clear Notes 1 An interrupt is generated only when the value of the GCCn0 register is FFFFH 2 An interrupt is generated only when the value of the GCCn0 register is not FFFFH Remark The setting of the CCSGm bit in combination with the SWFGm bit sets the mode for the tim ing of the actualization of new compare values In compare mode the new compare value will be immediately active n PWM mode the new compare value will be active first after the next overflow or match amp clear of the assigned counter TMGO TMG1 322 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer Table 10 6 Interrupt output and timer output states dependent on the register setting values Register setting value State of each output pin CCSG5n TBGm SWFGm CCSGm INTTMGn1 INTCCGn5 INTCCGnm Tim edge detection 0 CMPGm match Tied P us Overflow TI5 edge eve Free run interrupt detection Tim edge iis detection PWM CMPGm match free run Tim edge detection Tied to inactive CMPGm match Overflow CMPG5 level Match and Note 2 Tim edge clear mode Match detection interruptNete 1 PWM CMPGm match match and clear Notes 1 interrupt is generated only when the value of the GCC5 register is FFFFH 2 Aninterrupt is generated only when the value of t
159. Types of Pin I O Circuit and Connection of Unused 51 Ghapter 3 CPU Function ute o mp E SIE NE RENE EUR EA NERA sai 55 jJ lot AI ENAN eg EANAN Med LE pee 55 3 2 CPU Register Set n a E aE a nn nn nnn 56 3 21 s oec eode aati wine Pha Rial rede bU e We Kup pr ave 57 3 2 2 System register set iiie legs pana pg Ae a e c isles 58 3 3 Operation Modes sseseesseseeeeeeee nnn n nnn 62 3 371 Operation Modes sic evi she Hated eats edad eig aues 62 3 3 2 Operation mode 63 3 4 Address SPace oi eles nid eee etre EMEN ERE E rd RE d 65 3 4 1 CPU address space rn 65 344 2 tiagecs iet ted Pe V deeb ees eu REX a REB eu EU 66 3 4 3 Wrap around of CPU address 67 3 5 Memory Map ee hie weet ee ERR ee REN ee et 68 Rod LATOB Gite Gai AKA MARE ee ee ee ee mE e ks 70 3 5 2 Recommended use of address space 75 3 5 8 Peripheral I O 5 lt 76 3 5 4 Programmable peripheral I O 83 3 6 Specific RegisterS 0c ee eee 103 3 6 1 Command Register P
160. Vpp30 to Vppso to Vpps2 Port AH Port CMO Port CS Port CT Reset Reset Out Receive Data Input Serial Clock Serial Input Serial Output Timer Input Timer Output Transmit Data Output 8 V Power Supply 5 V Power Supply Wait Write Enable Read Chip Select Crystal Main OSC Crystal Sub OSC Note FCRXD3 FCTXD3 FCRXD4 and FCTXD4 are available only in the derivatives PD703129 A and uPD703129 A1 Remark 28 n 0 1 Preliminary User s Manual U15839EE1VOUMOO 1 6 Function Block Diagram INTPO to INTP5 INTPOO INTPO5 INTP10 INTP15 Chapter 1 Introduction Figure 1 2 V850E CA2 Jupiter Block Diagram NMI Interrupt Controller INTP20 INTP21 TIGOO to TIGOS Tenit Timer TOGO1 to TOG04 TMGO TIG10 to TIC15 16 bit Timer TOG11 to TOG14 IM Ties To 16 bit Timer Note 16 bit Timer power supply E Barrel Shifter System Registers Hardware Multiplier A0 to A15 A16 to A23 DO to D15 WAIT CS0 CS3 C84 RD R LWR Bus Control Unit 4 iCache c General Registers Internal Peripheral Bus TMDO y 16 bit Timer TMD1 FCRXD1 FCAN1 FCTXD1 FCRXD2 FCAN2 FCTXD2 FCRXD3 Nag FCAN3 FCTXD3 FCRXD4 Nu FCAN4 FCTXD4 RXD50 UART50 TXD50 BAG RXD51 UARTS1 TXD51 5100 5000 CSI00 A 5101 10 bit Ports
161. _Interrupt time of watch timer 2j Interval timer Bre Interval time n peras Se ji Interval time gt I I interrupt INTWTI nT nT m a 4 Watch timer interrupt INTWT i RE 1 H Note The Watch Timer frequency depends of the CKC register Clock Generator and the WTM Watch Timer register Remarks 1 fy Watch timer clock frequency 2 n Interval timer operation numbers Preliminary User s Manual U15839EE1VOUMOO 355 MEMO 356 Preliminary User s Manual U15839EE1VOUMOO Chapter 12 Watchdog Timer Function 12 1 Functions The watchdog timer has the following functions e Watchdog Timer with non maskable interrupt INTWDT e Watchdog Timer with hardware RESET Figure 12 1 Block Diagram of Watchdog Timer Clear fk 221 fwor Prescaler f x Output INTWDT Control ane ae Circuit RESET Selector WDTM4 WDTM3 WDCS WDCS2 WDCS1 WDCSO WDTM 2 Internal bus Remark fyp Watchdog Timer clock frequency depends on clock tree settings 1 Interrupt mode This mode detects program runaway When runaway is detected a non maskable interrupt can be generated 2 RESET mode This mode detects program runaway When runaway is detected a hardware RESET is generated Preliminary User s Manua
162. a CAN network can be provided i e transmitted by only one node All other nodes in the network may receive that data frame Using a transmit message buffer for a remote frame generation means that two message buffers for han dling of one message within one node are required one receive message buffer for the reception of a data frame and the transmit message buffer explicitly for the remote frame generation Preliminary User s Manual U15839EE1VOUMOO 449 2 Chapter 14 FCAN Interface Function Reception of a remote frame The FCAN allows the reception of remote frames in message buffers defined for reception or for transmission a Reception in a receive message buffer If a remote frame is received in a message buffer m m 00 to 31 configured for reception the fol lowing message buffer information will be updated M_DLCm message data length code register message control register message time stamp register 16 bit message data byte 0 message data byte 1 message data byte 2 message data byte 3 message data byte 4 message data byte 5 message data byte 6 message data byte 7 message identifier register lower half word message identifier register upper half word message status register Remarks 1 Receiving a remote frame in a receive message buffer does not activate any automatic 450 remote frame handling activities from the FCAN system The appl
163. a standard format identifier the irrelevant mask bits CMID17 to CMIDO have to be set 1 Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Remarks 1 0 to mask number 2 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 3 1 to 2 for the derivative uPD703128 A Preliminary User s Manual U15839EE1VOUMOO 485 Chapter 14 FCAN Interface Function Table 14 17 Address Offsets of the CAN 1 to 4 Mask Registers Address OffsetNete 3 x22 x 3Note 1 2 x 4Note 1 2 SymbolNotet 2 CxMASKLO CxMASKHO CxMASKL1 CxMASKH1 CxMASKL2 CxMASKH2 CxMASKL3 CxMASKH3 Notes 1 CAN module number 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 2 CAN module number 1 to 2 for the derivative 0703128 3 The register address is calculated according to the following formula effective address PP_BASE address offset 486 Preliminary User s Manual U15839EE1VOUMOO 2 CAN 1 to 4 control registers C1CTRL to CACTRL The CxCTRL registers control the operating modes and indicate the operating status of the Chapter 14 FCAN Interface Function corresponding CAN module x x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A These registers can be read in 8 bit and 16 bit units It can be written in 16 bit units only For set ting and clearing
164. always acknowledged 8 5 1 Operation If a software exception occurs the CPU performs the following processing and transfers control to the handler routine 1 Savesthe restored PC to EIPC 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower 16 bits EICC of ECR interrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Pp ee ee Figure 8 21 illustrates the processing of a software exception Figure 8 21 Software Exception Processing T TRAP instructionNote EIPC restored PC EIPSW PSW ECR EICC exception code PSW EP 1 PSW ID 1 PC handler address Exception processing Note TRAP Instruction Format TRAP vector the vector is a value from 0 to 1FH CPU processing The handler address is determined by the TRAP instruction s operand vector If the vector is 0 to OFH it becomes 00000040H and if the vector is 10H to 1FH it becomes 00000050H Preliminary User s Manual U15839EE1VOUMOO 227 Chapter 8 Interrupt Exception Processing Function 8 5 2 Restore Recovery from software exception processing is carried out by the RETI instruction By executing the RETI instruction the CPU carries out the following processing and shifts control to the restored PC s address 1 Loads the restored PC and PSW from EIPC and EIPSW because the EP bi
165. anymore Preliminary User s Manual U15839EE1VOUMOO 469 Chapter 14 FCAN Interface Function 3 CAN 1 to 4 interrupt pending registers C1INTP to CAINTP The C1INTP to CAINTP registers indicate the corresponding CAN module interrupt pending sig nals The interrupt pending flags can be cleared by writing to the registers according to the special bit clear method Refer to chapter 14 3 1 Bit set clear function on page 452 This register can be read and written in 8 bit and16 bit units Figure 14 23 CAN 1 to 4 Interrupt Pending Registers C1INTP to C4INTP 1 2 Address Read 44 13 P og 90 9 8 7 6 5 4 3 2 Offset value Note 1 1022H 0000H 1024H 0000H 1026H 0000H cal 1008H 0000H Wie 1 14 13 12 W 1 9 8 7 6 5 4 3 2 4 0 CAINT 1022H CAINT 024H CSINT 1026H CAINT 028H Read 1 2 Y Bit Name i Indicates a CAN module x error CxINT6 0 No Interrupt pending 1 Interrupt pending Indicates a CAN bus error of CAN module x CxINT5 0 No Interrupt pending 1 Interrupt pending Indicates a wake up from sleep mode of CAN module x CxINT4 0 No Interrupt pending 1 Interrupt pending Indicates a error passive status on reception of CAN module x
166. area between x0000H and x1200H is used exclusively for the FCAN controller The internal bus of the V850E CA2 becomes active when the peripheral I O register area 3FF FOOOH to 3FF FFFFH or the programmable peripheral I O register area xxxx m000H to xxxx nFFFH is accessed m xx00B n xx11B Note that when data is written to the peripheral I O register area the written contents are reflected also on the upper 4 KB area of the programmable peripheral I O area The base address of the programmable peripheral I O area is specified by the initialization of the peripheral area selection control register BPC Figure 3 15 Programmable Peripheral I O Register Outline 3FF FFFFH Peripheral I O register Internal local bus FOOOH 3FF EFFFH d NFFFH ES Programmable Peripheral peripheral I O area x 3000H xxx M000H VO register x 2FFFH Programmable peripheral RUE I O area x OFFFH Dedicated area for x 00008 FCAN controller 000 0000H Cautions 1 The CAN message buffer register can allocate address xxxx freely as a program mable peripheral I O register but once the address xxxx is set it cannot be changed 2 If the programmable peripheral I O area overlaps the following areas the pro grammable peripheral I O area becomes ineffective Peripheral I O area ROM area RAM area Remark xx00B N xx11B Preliminary User s Manual U15839EE1VOUMOO 83 Chapter 3 CPU Function
167. area is provided as a programmable peripheral I O area refer to 3 5 4 Programmable peripheral I O registers on page 83 74 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 5 2 Recommended use of address space The architecture of the V850E CA2 requires that a register is utilized for address generation when accessing operand data in the data space Operand data access from instruction can be directly exe cuted at the address in this pointer register 32 KB However the use of general registers as pointer registers decreases the number of usable general registers for handling variables but minimizes the deterioration of address calculation performance when changing the pointer value and minimizes the program size as well To enhance the efficiency of using the pointer in consideration of the memory map of the V850E CA2 the following points are recommended 1 2 Program space Of the 32 bits of the PC program counter the higher 6 bits are fixed to zero 0 and only the lower 26 bits are valid Therefore a contiguous 64 MB space starting from address 0000 0000H unconditionally corresponds to the memory map of the program space Data space For the efficient use of resources to be performed through the wrap around feature of the data space the continuous 16 MB address spaces 0000 0000H to OOFF FFFFH and FF00 OOOOH to FFFF FFFFH of the 4 GB CPU address space are used as the data space With the V850E C
168. be switched on by software once However the start up of the SSCG and PLL cause always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a fast response when waking up from WATCH mode the SSCG and PLL should not be re enabled immediately after waking up as this causes again the delay In this case time relevant reactions of the CPU should be done first before re enabling the SSCG and PLL 260 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 4 7 SUB WATCH mode In this mode fopy clock and the main oscillator are stopped while the sub oscillator continue to operate to achieve low power though only oscillator amp Watch timer Watchdog timer continue to operate This mode compensates the HALT modes concerning the oscillator stabilization time and power con sumption At release for the main oscillator an additional oscillator stabilization time is required This mode compensates the WATCH modes concerning the power consumption of the main oscillator This mode is entered by configuration the PSM and PSC registers In the SUB WATCH mode program execution is stopped but the contents of all registers and internal RAM prior to entering this mode are retained On chip other peripheral hardware operation is also stopped The state of the various hardware units in the WATCH mode is tabulated below
169. bit Sets the handler address corresponding to the non maskable interrupt to the PC and transfers control The processing configuration of a non maskable interrupt is shown in Figure 8 2 206 Figure 8 2 Processing Configuration of Non Maskable Interrupt NMI input Non maskable interrupt request INTC acknowledgement CPU processing FEPC lt Restored PC FEPSW lt PSW ECR FECC lt Exception code PSW NP lt 1 PSW EP lt 0 PSW ID lt 1 lt NMI Handler address Interrupt service Interrupt request pending Preliminary User s Manual U15839EE1VOUMOO Chapter8 Interrupt Exception Processing Function 8 2 2 Restore 1 NMIO Execution is restored from the non maskable interrupt NMIO processing by the RETI instruction When the RETI instruction is executed the CPU performs the following processing and transfers control to the address of the restored PC 1 Restores the values of the PC and the PSW from FEPC and FEPSW respectively because the EP bit of the PSW is 0 and the NP bit of the PSW is 1 2 Transfers control back to the address of the restored PC and PSW Figure 8 3 illustrates how the RETI instruction is processed Figure 8 3 RETI Instruction Processing RETI instruction EIPC PC FEPC EIPSW PSW FEPSW Original processing restored Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable inte
170. bunt e eco Re ed 302 10 2 6 Application 304 10 2 7 Precautions for Timer Dn 305 10 3 E M 306 10 3 1 Features of 306 10 3 2 Function overview of each Timer Gn 307 10 3 3 Basicconfiguration e 309 10 3 4 5 313 10 3 5 Output delay 321 10 3 6 Explanation of basic 322 10 3 7 Operation in Free run 324 10 3 8 Match and clear mode 335 10 3 9 Edge noise 346 10 3 10Precautions Timer 347 Chapter 11 Watch Timer 22 ouo or EE ERE REST E RT Cede dee 349 11 1 FutnicHon uu e II RM ad Re AU RARE EAE REM 349 11 2 Configuration s uuum eris aa a a See E 350 11 3 Watch Timer Control 350 11 4 Operations xo ete see diets Doe eee Meee ret eoe nce 352 11 4 1 Selection of the Watch Timer
171. can be read written in 8 bit units Figure 14 30 Message Control Registers 00 to 31 M CTRLOO to M CTRL31 1 2 Address Initial OffsetNote value m x 20H Specifies the remote frame handling mode 1 0 DN flag is not changed when receiving a remote frame 1 DN flag is set 1 when receiving a remote frame Remark The remote frame handling mode 1 is only valid for transmit messages and indicates how the DN flag is updated if a remote frame is received on that message buffer For details refer to chapter 14 2 8 Remote frame han dling on page 449 Specifies the remote frame handling mode 0 0 Auto answering of remote frame is not active 1 Auto answering of remote frame is active Remark The remote frame handling mode 0 is only valid for transmit messages and indicates how to respond if a remote frame is received on that message buffer For details refer to chapter 14 2 8 Remote frame handling on page 449 Controls appending of the time stamp 0 No time stamp appending 1 Append time stamp Only valid for transmit messages Remark This bit is only handled for transmit messages If ATS is set 1 and the data length code DLC is greater or equal 2 the last two data bytes are replaced by the 16 bit time stamp The appended time stamp is the cap ture value of the CAN global time system counter CGTSC on the SOF for this message The last two data bytes defined in the data area are ignored For furth
172. certain bits a special set clear method applies refer to chapter 14 3 1 clear function on page 452 C2CTRL pz Figure 14 34 CAN 1 to 4 Control Registers C1CTRL to CACTRL 1 5 ST DLEVR ST DLEVR RECS1 RECS1 RECS1 RECS1 ST DLEVT ST DLEVT RECS0 RECS0 RECS0 RECS0 ST OVM RSTAT RSTAT RSTAT ST SLEEP STAT STAT STAT ST INIT TPE TPE TPE oL TPE DLEVR DLEVR DLEVR eL DLEVR CL DLEVR DLEVT DLEVT DLEVT eL DLEVT oL DLEVT oV oV oV eL OVM eL TMR SLEEP SLEEP SLEEP CL_ SLEEP eL SLEEP C3CTRL pF C3CTRL ST DLEVR ST DLEVR ST DLEVT ST DLEVT ST OVM Preliminary User s Manual U15839EE1VOUMOO ST SLEEP ST SLEEP ST INIT eL TPE eL DLEVR eL DLEVR eL DLEVT CL DLEVT eL OVM eL TMR oL SLEEP eL SLEEP Address Offse Note 050H 1090H ODOH 110H 1050H 1090H 10D0H Initia Bit set Value 0 ce e 487 Chapter 14 FCAN Interface Function Figure 14 34 CAN 1 to 4 Control Registers C1CTRL to C4CTRL 2 5 Read 1 2 Bit Position Bit Name Function Indicates the transmission error counter stat
173. clock cycle with the CSE12 to CSE10 bits TMGn1 or CSE02 to CSE02 bits TMGnO 3 Select a valid TlGny edge with the IEGy1 and IEGyO bits A rising edge falling edge or both edges can be selected 4 Start timer operation by setting POWER bit and TMGOE bit for TMGnO or TMG1E bit for TMGn1 Capture Operation 1 When a specified edge is detected the value of the counter is stored in GCCny and an edge detection interrupt INTCCGny is output 2 When the counter overflows an overflow interrupt INTTMGnO or INTTMGn1 is generated If an overflow has occurred between capture operations the CCFGy flag is set when GCCny is read Correct capture data by checking the value of CCFGy Using CCFGy When using GCCny as a capture register use the procedure below 1 After INTCCGny edge detection interrupt generation read the corresponding GCCny register 2 Check if the corresponding CCFGy bit of the TMGSTn register is set 3 If the CCFGy bit is set the counter was cleared from the previous captured value CCFGy is set when GCCny is read So after GCCny is read the value of CCFGy should be read Using the procedure above the value of CCFGy corresponding to GCCny can be read normally Caution If two or more overflows occur between captures a software based measure needs to be taken to count overflow interrupts INTTMGnO INTTMGn1 Preliminary User s Manual U15839EE1VOUMOO 325 Chapter 10 Timer Figure 10 41 T
174. clock management Data can be written to it only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang up See also PHCMD register This register can be read or written in 8 bit units Figure 9 2 Clock Control Register CKC 1 2 7 6 5 4 3 2 1 0 Address Initial value OKO PEN DENE ESO TERENE 307 00H Bit name Function PLLEN enable bit This bit enables or disables PLL operation 0 PLL disabled 1 PLL enabled PLLEN Caution The PLL is enabled when this bit is set 1 Before applying the PLL clock as the clock supply for the CPU or the peripherals it must have been secured by soft ware that the PLL stabilization time 1ms has been elapsed During this stabili zation time the software must remain in a loop and the CPU and the peripherals are supplied by the main oscillator clock Switching to an unstable clock source is not protected by hardware SSCG enable bit This bit enables or disables Spread Spectrum Clock Generation 0 SSCG disabled 1 SSCG enabled SCEN Caution The SSCG is enabled when this bit is set 1 Before applying the SSCG clock as the clock supply for the CPU it must have been secured that the SSCG sta bilization time has been elapsed The SCSTAT bit in the CGSTAT register shows the status of the SSCG The value of the read only bit SCSTAT must be read as set 1 before enabling the SSCG clock to the CPU
175. control Register 1 1 1 2 280 Valid Edge Selection Register 282 Timing of basic operation of Timer C sse 283 Timing of interrupt operation after overflow 284 Timing of capture for pulse cycle measurement rising 285 Timing of capture for pulse width measurement both edges 286 Timing of cycle measurement operation 288 Timing of compare 289 Timing of interval timer operation 290 Timing of PWM output operation overview 291 Timing of PWM output operation 292 Multiplexed Inputs for Timer C Sub Oscillator Calibration Function 294 Block Diagram of Timer Dn n 0 1 296 Timer Dn counter register TMDn n 0 1 298 Timer Dn Compare Register CMDn n 0 1 299 Timing of Timer Dn Operation sse 300 Timer Dn Control Register TMCDn n 0 1 sse 301 Timing of Compare Operation 1 2 sess 302 Block Diagram of Timer nennen nennen nnns nnns 308 Timer Gn Counter 0 Value Registers TMG
176. differs on interrupt priority levels as follows a If an interrupt request less priorities than the currently serviced interrupt request is generated the WATCH mode is release but the interrupt is not acknowledged The interrupt request itself is retained b If an interrupt request including a non maskable one priorities than the currently serviced interrupt request is generated the interrupt request is acknowledged along with the WATCH mode release Preliminary User s Manual U15839EE1VOUMOO 259 Chapter 9 Clock Generator Table 9 8 Operation after WATCH mode release by interrupt request Ese BEES NMI request Branches to handler address Maskable interrupt Branches to handler address or A Executes the next instruction request executes the next instruction Remark f WATCH mode is entered during execution of a particular interrupt handler and an unmasked interrupt request with a higher priority than the previous one is subsequently generated the program branches to the vector address for the later interrupt 2 When released by RESET input This operation is the same as normal reset operation except oscillation stabilization time is not required 3 When released by Watchdog Timer RESET input After oscillator stabilization time has passed CPU starts operation Remark Before entering the WATCH mode the SSCG and PLL are switched off by hardware After the WATCH mode has been released the SSCG and PLL can
177. do not change the set value Also do not access an external memory area other than that for this initialization routine until initial setting of the PRC register is finished However it is possible to access exter nal memory areas whose initialization has been finished Preliminary User s Manual U15839EE1VOUMOO 149 Chapter 5 Memory Access Control Function 5 2 5 Page ROM access Figure 5 6 Page ROM Access Timing 1 4 a During read when half word word access with 8 bit bus width or when word access with 16 bit bus width T1 TW T2 TO1 TO2 to A23 output Off page address On page address CSn output RD output UWR output LWR output d p TTU e m SGD 27 21 DO to 015 I O WAIT input Remarks 1 The circles O indicate the sampling timing 2 The broken line indicates the high impedance state 3 CSn CS0 CS3 and CS4 150 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function Figure 5 6 Page ROM Access Timing 2 4 b During read when byte access with 8 bit bus width or when byte half word access with 16 bit bus width T1 TW T2 TO1 TO2 to A23 output Off page address On page address CSn output RD output UWR output LWR output NE ES DO to D7 I O DO to D15 I O WATT input Remarks 1 The circles indicate the sampling timing
178. edge ESNO 0 Falling edge 1 Rising edge Notes 1 This register can be written only once ESNO is cleared to 0 by Reset 2 This register should always be programmed even if the user needs to use the reset value This will prevent unintended write to this register afterwards 3 NMI functionality is masked by PMC6O Selection of valid edge for NMI must be performed while PMC60 is 208 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function 8 3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers The V850E CA2 has 63 maskable interrupt sources If two or more maskable interrupt requests are generated at the same time they are acknowledged according to the default priority In addition to the default priority eight levels of priorities can be speci fied by using the interrupt control registers programmable priority control When an interrupt request has been acknowledged the acknowledgement of other maskable interrupt requests is disabled and the interrupt disabled DI status is set When the El instruction is executed in an interrupt processing routine the interrupt enabled El status is set which enables servicing of interrupts having a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priori
179. enable register Note 1 C1IE 0000H xxxxn105AH bus active register C1BA 00FFH xxxxn105CH CAN bit rate prescaler register C1BRP 0000H xxxxn105DH CAN1 bus diagnostic information register C1DINF 0000H xxxxn105EH CAN1 synchronization control register C1SYNC 0218H xxxxn1080H CAN address mask register LO C2MASKLO Undefined xxxxn1082H CAN address mask register HO C2MASKHO Undefined xxxxn1084H CAN address mask register L1 C2MASKL1 Undefined xxxxn1086H CAN address mask register H1 C2MASKH1 Undefined xxxxn1088H CAN address mask register L2 C2MASKL2 Undefined xxxxn108AH CAN address mask register H2 C2MASKH2 Undefined xxxxn108CH CAN address mask register L3 C2MASKL3 Undefined xxxxn108EH CAN address mask register H3 2 OK mK ox o Undefined xxxxn1090H CAN control register Note 1 C2CTRL 0101H xxxxn1092H CAN definition register Note C2DEF 22 0000H xxxxn1094H CAN information register C2LAST 00FFH xxxxn1096H CAN error counter register C2ERC 0000H xxxxn1098H CAN interrupt enable register Note 1 C2IE mixix 0000H xxxxn109AH CAN bus active register C2BA 00FFH xxxxn109CH CAN bit rate p
180. epe te etie a aa Seeded bien Sah et dett 357 Program Spaces Lupi EE ia DUE oie RR RE puto 67 Program Status Word 60 Program status word E ERA hh 60 Programmable peripheral I O registers 83 113 Programmable pulse generator function 271 Programmable pulse 306 PRSCMO PRSCM1 rani i eun atini aen iao aarte KRAN lehren 425 PRSMOLPRSM iie AED oe ta eek Meee eae dale YER ra Pedo e Ver 424 mol M TIER 268 RSMH ciet epa Que AEG eb t suene eru geht WA dede d 270 Diete suut tiu metis te Plate Sealing Sart fate Gainer e ONUS ED exu tao eta ree eta 58 60 pulse cycle measurement 285 Pulse interval and frequency measurement counter 306 Pulse width measurement 335 PWM 3 TM 271 291 306 331 Q Quiartizatiom Error det Eel Dp Leu Riz lt dub lu aub abes 543 R RAN uh Rite aan Ay aca rece ante Anat once et Lut Et M LE Lm EL DE IAE 30 Reception buffer registers 3 4 te teens 372 Reception completion interrupt syor irere eria RR IIR I eh 374 Reception error interrupt ui
181. high impedance state 3 CSn CS0 CS3 and CS4 Preliminary User s Manual U15839EE1VOUMOO 153 MEMO 154 Preliminary User s Manual U15839EE1VOUMOO Chapter 6 Instruction Cache The V850E CA2 Jupiter device contains a 4 KByte 2 way associative instruction memory iCache to improve the system s instruction execution speed and performance 6 1 Features Use of Least Recently Used LRU algorithm The LRU algorithm replaces the cache line that has not been used since the longest time The probability of a instruction cache hit is mostly higher compared to the direct mapped type Using the tag clear function the contents of all tags can be cleared invalidated Using the autofill function instructions for one way can be filled automatically way 0 only A filled way is locked automatically and replacing data in the way or writing to tags is disabled Thus it also can be used as a ROM that can operate in one cycle Preliminary User s Manual U15839EE1VOUMOO 155 Chapter 6 Instruction Cache 6 2 Configuration To improve the instruction execution speed and the total system s performance the V850E CA2 Jupiter device provides a 4 KByte 2 way associative instruction cache memory The instruction cache is organ ized as 4 words x 128 entries x 2 ways Figure 6 1 Instruction Cache Configuration Instruction Cache External Memory Bus Control Unit Memory Controller BCU MEMC V850E System Bus VSB j
182. in TMR bit value Sets clears the STOP bit ST STOP CL STOP Status of STOP bit ST STOP STOP bit is cleared 0 CL STOP STOP bit is set 1 Others No change in STOP bit value 490 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 34 CAN 1 to 4 Control Registers C1CTRL to CACTRL 5 5 Write 2 2 Sets clears the SLEEP bit CL SLEEP Status of SLEEP bit SLEEP bit is cleared 0 SLEEP bit is set 1 Others No change in SLEEP bit value ST SLEEP CL SLEEP Sets clears the INIT bit ST INIT CL INIT Status of INIT bit INIT bit is cleared 0 INIT bit is set 1 ST INIT CL INIT Others No change in INIT bit value Note The register address is calculated according to the following formula effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO 491 3 Read Chapter 14 FCAN Interface Function CAN 1 to 4 definition registers CTDEF to CADEF The CxDEF registers define normal and diagnostic operation and indicate CAN bus error and states of the corresponding CAN module x x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A These registers can be read in 8 bit and 16 bit units It can be written in 16 bit units only For set ting and clearing certain bits a special set clear method applies refer to chapter 14 3 1 Bit s
183. interface initial transmission buffer registers 405 Clocked serial interface mode 395 Clocked serial interface read only reception buffer registers 400 Clocked serial interface read only reception buffer registers Low 401 Clocked serial interface reception buffer registers 398 Clocked serial interface reception buffer registers Low 399 Clocked serial interface transmission buffer registers 402 Clocked serial interface transmission buffer registers Low 403 COMO tO COMA ass aiid er DD ru MD Lees 49 Command Register a drania ae e a a a ett 104 Compare operation ansaan aanne 289 302 337 Continuous transmission sssusa aaee 377 Conversion Ume 5 se es pee RAPERE SEC Een EA MER Ek 528 ol PE 24 Gountopoeraltlon a iue e Duae E dare edd nen ARMAR E RENE ANUS EE aed ya eS He Rn 283 CSCO ede tuer bd pee reme ebore eva em elem dot y ove dod ah 111 CS cti ud e eU du cd ls d Nu DE etu EI ER e arcs Rn 111 to GSIO2 eei rco eL REIR ees Iq e eer MESE de ded Re 396 CSIMO to CSIM2 usseseelseleel ehh hh 395 ae eee eh a ce et Ba peindre reo OT inta 58
184. interrupt request INTTMCO is generated at the same time However if CCCOO is set to the compare mode CMSO bit of the TMCCO 1 register 1 and match clear during comparison of TMCO and CCCOO0 is enabled CCLR bit of TMCC01 register 1 and TMCO is cleared to 0000H following match at FFFFH TMCO is considered to have been cleared and the OVF bit does not become 1 nor is the INTTMCO interrupt generated The OVF bit holds a 1 until 0 is written to it or an asynchronous reset is applied while the CAE bit 0 Interrupts by overflow and the OVF bit are independent and even if the OVF bit is manipulated this does not affect the interrupt request flag for INTTMCO TMCIFO register If an overflow occurs while the OVF bit is being read the value of the flag changes and the value is returned at the next read 278 Preliminary User s Manual U15839EE1VOUMOO Bit Position Chapter 10 Timer Figure 10 5 Timer C control Register 0 TMCCOO 2 2 Bit Name CS2 to CSO Function Selects the internal count clock for TMCO Count Clock fpciK 2 fpck 4 fpcik 8 fpcik 16 fecLk 32 fecLk 64 fecuk 256 Caution Do not change the CS2 to CSO bits during timer operation If they are to be changed they must be changed after setting the CE bit to 0 If the CS2 to CSO bits are overwritten during timer operation the operation is not guaranteed Remark fpc internal peripheral clock C
185. is not generated b When 0000H is set in GCCnm match and clear When 0000H is set in GCCnm TOGnm is tied to the inactive level The figure below shows the state of TOGn1 when OOOOH is set in GCCn1 and TMGn0 is selected Note however that OFFFH is set in GCCnO Figure 10 54 Timing when OOOOH is set in GCCnm match and clear ENFGO OFFFH OFFFH OFFFH Match TMGnO i INTCCGn1 INTCCGnO TOGn1 ALVG1 1 Low TOGn1 ALVG1 0 High GCCn1 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer c When the same value as set in GCCn0 or GCCn5 is set in GCCnm match and clear When the same value as set in GCCn0 GCCn5 is set in GCCnm TOGnm outputs the inactive level for only one clock period immediately after each match and clear event excluding the first match and clear event The figure below shows the state of TOGn1 when OFFFH is set in and GCCn1 and TMGn0 is selected Figure 10 55 Timing when the same value as set in GCCn0 GCCn5 is set in GCCnm match and clear ENFGO Match TMGnO INTCCGn1 INTCCGnO TOGn1 ALVG1 1 i TOGn1 ALVG1 0 1 Preliminary User s Manual U15839EE1VOUMOO 343 344 Chapter 10 Timer d When a value exceeding the value set in GCCn0 or GCCn5 is set in GCCnm match and clear When a value exceeding the value set in GCCn5 is set in GCCnm
186. lt Assignment GR General register SR System register zero extend n Zero extends n to word length sign extend n Sign extends n to word length load memory a b Reads data of size b from address a store memory a b c load memory bit a b store memory bit a b c Writes data b of size c to address a Reads bit b from address a Writes c to bit b of address a Performs saturated processing of n n is 215 complements Result of calculation of n If nisn 2 7FFFFFFFH as result of calculation 7FFFFFFFH If n is n lt 80000000H as result of calculation 80000000H result Reflects result to a flag Byte Byte 8 bits Halfword Half word 16 bits Word Word 32 bits Add Subtract saturated n Bit concatenation Multiply Divide Logical product Logical sum Exclusive logical sum Logical negate logically shift left by Logical left shift logically shift right by arithmetically shift right by Logical right shift Arithmetic right shift Table A 4 Symbols Used for Flag Operation Symbol Description Not affected Cleared to 0 Set of cleared according to result Previously saved value is restored Preliminary Users Manual U15839EE1VOUMOO 591 Appendix A List of Instruction Sets Table A 5 Condition Codes Condition Name Condition Code cond cccc Conditional Ex
187. module x x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative 703128 These registers can be read only 8 bit and 16 bit units Figure 14 39 CAN 1 to 4 Bus Activity Registers C1BA to C4BA 1 2 Address Initial OffsetNet value CIBA 0 0 CACTA4 CACT3 CACT2 CACT CACTO TMNO7 TMNOG TMNOS TMNO4 TMNO3 TMNO2 TMNO1 TMNOO 105AH O0FFH C2BA 0 0 0 CACT4 CACT3 CACT2 CACTI CACTO TMNO7 TMNO6 TMNOS TMNO4 TMNO3 TMNO2 TMNO1 TMNOO 109AH 00FFH C3BA 0 0 0 ICACT4ICACT3ICACT2ICACT1 CACTO TMNO TMNO6 TMNOS TMNO4 TMNO3 TMNO2 TMNO1TMNOO 10DAH 00FFH C4BA 0 0 0 CACT4 CACT3 CACT2 CACTI CACTO TMNO7 TMNOG TMNOS TMNO4 TMNO3 TMNO2 TMNO1 TMNOO 111AH 00FFH Indicates the CAN module activity CACT4 CACT3 CACT2 CACT1 CACTO CAN Module Activity Reset state Waiting for bus idle Bus idle Start of frame SOF Standard format ID section Data length code section Data field section CRC field section CRC delimiter Acknowledge slot CACTA to CACTO Acknowledge delimiter End of frame section EOF Intermission state Suspend transmission Error frame Waiting for error delimiter
188. of clocks are generated fxx 8 fxx 6 fyy 4 fxx 3 and can be supplied as the operating clock for the CPU BCU fcpy Clock generator CG The clock generator includes two types of oscillators Main OSC and Sub OSC The Peripheral PLL can also be used as the clock supply for the CPU BCU fxxp fxxp 2 The peripherals can be supplied with the clock fxxp or fyxp 2 Preliminary User s Manual U15839EE1VOUMOO 8 9 10 11 Chapter 1 Introduction Real time pulse unit RPU This unit has 3 channels of 16 bit multi purpose timer event counter and 2 channels of 16 bit inter val timer built in and it is possible to measure pulse widths or frequency and to output a program mable pulse Serial interface SIO A 2 channel asynchronous serial interface UART 3 channel clocked serial interface CSI and 4 channel FCAN are provided as serial interface UART transfers data by using the TXDn and RXDn pins n 0 1 CSI transfers data by using the SOn SIn and SCKn pins n 0 2 FCAN performs data transfer using CTXDn and CRXDn pins n 1 4 A D converter ADC One high resolution 10 bit A D converter it includes 12 analog input pins Conversion uses the successive approximation method Ports As shown below the following ports have general port functions and control pin functions Port 1 Port Function 8 bit input output Control Function Serial interface input output Port 2 8 bit inpu
189. output port mode 1 TXD1 output mode At Reset 00H Specifies operation mode of P16 pin 0 Input output port mode 1 RXD1 input mode Specifies operation mode of P15 pin 0 Input output port mode 1 CTXD3 output mode Specifies operation mode of P14 pin 0 Input output port mode 1 CRXD3 input mode Specifies operation mode of P13 pin 0 Input output port mode 1 CTXD2 output mode Specifies operation mode of P12 pin 0 Input output port mode 1 CRXD2 input mode Specifies operation mode of P11 pin 0 Input output port mode 1 CTXD1 output mode Specifies operation mode of P10 pin 0 Input output port mode 1 CRXD1 input mode 558 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 2 Port 2 Port 2 is an 8 bit input output port in which input or output can be specified in 1 bit units Each port bit can be independently configured to port input port output or peripheral functionNete 1 This register can be read or written in 1 bit and 8 bit units Figure 16 10 Port 2 P2 Address At Reset pa FFFFFAO2H oo ote 2 P2n n 7t00 Input output port Remark In Input Mode When the P2 register is read the pin levels at that time are read Writing to the P2 register writes the values to that register This does not affect the input pins In Output Mode When the P2 register is read the values of P2 are read Writing to the P2 register writes the values to that regist
190. overwritten during timer operation the operation is not guaranteed Figure 10 7 Valid Edge Selection Register SESCO 7 6 5 4 3 2 1 0 Address value Bit Position Bit Name Function Specifies the valid edge of TICnO pins Operation IES11 IES10 Falling edge Rising edge Setting prohibited Both rising and falling edges IESO1 IESOO Remark nz0 1 282 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 1 5 Operation 1 Count operation Timer C can function as a 16 bit free running timer When it operates as a free running timer and the CCCOO register or CCCO1 register and the TMCO count value match an interrupt signal is generated and the timer output signal TOCO can be set or reset Also a capture operation that holds the TMCO count value in the or CCC01 register is performed synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger The capture value is held until the next capture trigger is generated Figure 10 8 Timing of basic operation of Timer C fcount Tuco 0000HY0001H 0002H Y 0003H o FBFEH Y0001HY 0002H Count start Count disabled Count start CE c 1 CE lt 0 CE 1 Preliminary User s Manual U15839EE1VOUMOO 283 2 Chapter 10 Timer Overflow When the TMCO register has counted the count clock from FFFFH to 0000H the OVF bit of the TM
191. receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed Preliminary User s Manual U15839EE1VOUMOO 411 Chapter 13 Serial Interface Function Figure 13 35 Timing Chart According to Clock Phase Selection 2 2 c When CKP bit 0 DAP bit z 1 SCKOn input output 510 input SO0n output Reg_R W INTCSIn interrupt CSOT bit d When bit 1 DAP bit 1 SCKOn input output SIOn input SO0n output Reg_R W INTCSIn interrupt Se ees CSOT bit Remarks 1 0 2 2 Reg R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBL n write was performed 412 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function c Transmission reception completion interrupt request signals INTCSIO to INTCSI2 INTCSIOn is set 1 upon completion of data transmission reception Caution The delay mode CSIT bit 1 is valid only in the master mode bits CKS2 to CKSO of the CSICn register are not 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKSO 111B Figure 13 36 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 input output SCKOn input output b E sen Con Ce CD CD Cm XC Reg R W INTCSIn interrupt CSOT bit
192. registers 5 18 Function Register Name CAN message time stamp register 08 M TIMEO8 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn108H CAN message data register 080 M DATAO80 Undefined xxxxn109H CAN message data register 081 M DATAO81 Undefined xxxxn10AH CAN message data register 082 M_DATA082 Undefined xxxxn10BH CAN message data register 083 M_DATA083 Undefined xxxxn10CH CAN message data register 084 M_DATA084 Undefined xxxxn10DH CAN message data register 085 M_DATA085 Undefined xxxxn10EH CAN message data register 086 M DATA086 Undefined xxxxn10FH CAN message data register 087 M_DATA087 X XJI XJI XIX XxX Xx Xx Undefined xxxxn110H CAN message ID register L08 M_IDLO8 Undefined xxxxn112H CAN message ID register H08 M IDHO8 Undefined xxxxn1 14H CAN message configuration register 08 M CONFO8 Undefined xxxxn1 15H CAN message status register 08 M STATO8 Undefined xxxxn1 16H CAN status set cancel register 08 SC STATO8 0000H xxxxn120H CAN message event pointer 090 M EVTO90 Undefined xxxxn121H CAN message event pointer 091 M EVTO91 Undefined xxxxn122H CAN message event pointer 092 M 92 Undefined xxxxn123H CAN message event pointer 093 M EVTO93 Undefined
193. s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 2 1 Program register set The program register set includes general registers and a program counter 1 General registers Thirty two general registers rO to r31 are available Any of these registers can be used as a data variable or address variable However rO and r30 are implicitly used by instructions and care must be exercised when using these registers rO is a register that always holds 0 and is used for operations using 0 and offset 0 addressing r30 is used by means of the SLD and SST instructions as a base pointer for when memory is accessed Also r1 r3 to r5 and r31 are implicitly used by the assembler and C compiler Therefore before using these registers their contents must be saved so that they are not lost The contents must be restored to the registers after the registers have been used Table 3 1 Program Registers Operation ro Zero register Always holds 0 ri Assembler reserved register Working register for generating 32 bit immediate data r2 Address data variable registers r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area Register to indicate the start of the text area where pro 2 Text pointer gram code is located to r29 Address data variable registers r30 Element pointer Base pointer when memory is accessed r31 Link pointe
194. shows DMAC transfers in line transfer mode in which a lower priority DMA transfer request is generated within one clock after the end of a line transfer When two DMA transfer requests are acti vated at the same time the two DMA transfers are performed alternately DMA channel 0 and 3 in Figure 7 24 Line Transfer Example 3 on page 191 are used for the line transfer example Figure 7 24 Line Transfer Example 3 DMA Transfer Request CHO Transfer Request CH3 channel 0 channel 3 terminal count terminal count DMA channel 0 in Figure 7 25 Line Transfer Example 4 on page 191 is used for a single transfer and channel 3 is used for the line transfer Figure 7 25 Line Transfer Example 4 DMA Transfer Request CHO Transfer Request CH3 DMA channel 0 terminal count DMA channel 3 terminal count Note The bus is always released Preliminary User s Manual U15839EE1VOUMOO 191 Chapter 7 DMA Functions DMA Controller 7 5 4 Block transfer mode In the block transfer mode once transfer begins the DMAC continues the transfer operation without releasing the bus until a terminal count occurs No other DMA requests are acknowledged during block transfer After the block transfer ends and the DMAC releases the bus and another DMA transfer can be acknowledged Figure 7 26 Block Transfer Example on page 192 shows a block transfer mode example It is a block
195. teda Mets Fx 178 debug traps i eee ex Bev pq eique beige Mp e erre eis 232 dedicated baud rate 364 Dedicated baud rate generators BRG 384 Dedicated baud rate generators 0 1 0 cece ee 423 Saee d dopo te Uie o dr eger qun bse us 169 DMA addressing control registers Oto 3 175 DMA channel control registers 177 DMA controller DMAC 169 Block transfer mode ra eee eee 192 Bus cycle state 5 186 Bus States sete Seda dete eed e edente o heel et d Den i ege ee 184 Chanel priorities 5 224 SEY ee P ER DW LA Ane EET ARES 194 Forcible interruption RR RH in 195 Forcible nn 196 Next address setting function 183 Precautions 75 ee Oe LEER RIS ete Baek Rt 198 Single transfer mode 187 Single step transfer mode
196. the particular interrupt has been identified the corresponding interrupt pending flag must be reset by soft ware at least before leaving the interrupt service routine Figure 14 4 FCAN Interrupt Bundling of V850E CA2 Register Set and clear Logic set and clear signal CGINTP CxINTP GINT7 0 0 GINT4 GINT3 GINT2 GINT1 0 0 CxINTG CxINTS CxINTACxINTS CxINT2 CxINT1 CxINTO INTMAC CANxERR CANXTRX Y tr x a x gt lt E 5 tc tc LLI tc tcc 4 ke tc ke LLI t 0 0 0 0 0 co e e N N T gt lt gt 2 2 2 2 2 2 2 z z lt lt lt lt lt lt lt lt lt 2 2 O Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit8 Bit7 Bito Bits Bit4 Bit2 Bito CCINTP x a LLI tc H 0 0 0 0 0 0 o 0 0 0 0 x 3 x lt lt Ed O Bit31 Bit30 Bit29 Bit28 Bit27 Bit26 Bit25 Bit24 Bit23 Bit22 Bit21 Bit20 Bit19 Bit18 Bit17 Bit16 Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Remark 1 to 2 for the derivative PD703128 x 1 to 4 for the derivatives uPD703129 A and 0703129 A1 P
197. the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification 596 Preliminary User s Manual U15839EE1VOUMOO Appendix A List of Instruction Sets Table A 6 Instruction Set List 5 7 Instruction Group Operand Opcode Operation rfrrrllll 111cccc GR reg2 GR reg2 logically 000000001 shift right by GR regt 0000000 regi reg2 GR reg2 GR reg2 logically imm5 reg2 uu dc shift right Logic by zero extend imm5 operation rrrrrl111 11RRRRR GR reg2 GR reg2 arithmeti 000000001 cally shift right by GR reg1 0100000 regi reg2 GR reg2 GR reg2 arithmeti cally shift right by zero extend imm5 rrrrr0101 imm5 reg2 01 000000000 regt lt GR regt l1RRRRR 000001111 Odddddd ddddddddd PC lt PC sign extend disp22 Note 5 rrrrrllti 0dddddd GR reg2 PC 4 disp22 reg ddddddddd PC sion extend disp22 Note 5 1 11 if conditions are satisfied dddcccc then PC lt PC sign extend Note 6 disp9 adr lt GR reg1 sign extend 00bbb1111 disp16 bit 3 10RRRRR dis
198. the input output pins of on chip peripheral I O in control mode Refer to 3 Port block diagram for a block diagram of the block type of each port Port Name Pin Name P10 to P17 Table 16 1 Port Function 8 bit input output Functions of each port Function In Control Mode Serial interface input output FCAN1 to FCAN3Nete UART1 P20 to P27 8 bit input output Serial interface input output CSIO CSI1 UARTO P30 to P35 6 bit input output Real time pulse unit RPU input output External interrupt input P40 to P45 6 bit input output Real time pulse unit RPU input output External interrupt input P50 to P56 7 bit input output Real time pulse unit RPU input output Serial interface input output FCANANete External interrupt input P60 to P67 8 bit input output Serial interface input output CSI2 External interrupt input P70 to P77 8 bit input Digital input of ANIO to ANI7 Port 7 8 P70 to P77 P80 to P83 12 bit input Digital input of ANIO to ANI 1 Port 9 P90 to P97 8 bit input output Port AH PAHO to PAH7 8 bit input output External address bus A16 to A23 Port CS PCSO PCS3 PCS4 3 bit input output External bus interface control signal output Port CT PCTO PCT1 PCT4 3 bit input output External bus interface control signal output Port CM PCMO 1 bit input output
199. the reception shift operation starts synchronized with the detection of the start bit and when the reception of one frame is completed the contents of the reception shift register are transferred to the RXBn register A reception completion interrupt INTSRn is also generated in synchronization with the transfer to the RXBn register 368 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function Figure 13 2 Asynchronous Serial Interface Mode Registers ASIMO ASIM1 3 3 0 parity During transmission the parity bit is cleared 0 regardless of the transmit data During reception no parity error is generated because no parity bit is checked No parity No parity bit is added to transmit data During reception the receive data is considered to have no parity bit No parity error is generated because there is no parity bit Specifies character length of transmit receive data 0 7 bits 1 8 bits Caution To overwrite the CL bit first clear 0 the TXE and RXE bits Specifies stop bit length of transmit data 0 1 bit 1 2 bits Caution To overwrite the SL bit first clear 0 the TXE bit Since reception is always done using a single stop bit the SL bit setting does not affect receive operations Enables disables generation of reception completion interrupt requests when an error occurs 0 Generate a reception error interrupt request INTSERn as an interrupt when an error occurs In thi
200. time DBT 16 TQ sampling point SPT 13 TQ prescaler BRP 16 data bit time DBT 12 TQ sampling point SPT 8 TQ 511 Chapter 14 FCAN Interface Function 14 4 3 Ensuring data consistency If the CPU reads data from the CAN message buffers the consistency of data read has to be ensured Therefore two mechanisms are provided Sequential data read Burst mode data read 1 Sequential data read If the data is read by the CPU by sequential accesses to the CAN message buffers the following sequence has to be observed Figure 14 44 Sequential CAN Data Read by CPU CPUREAD Y Clear DN Read data END As the DN flag is only set by the CAN module and cleared by the CPU only it is ensured that the CPU can recognize that new data is stored in the message buffer during the read operation Remark If the CPU reads the data by only one read access the data consistency is always ensured Therefore the check of the DN flag after reading the data is not necessary 512 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 2 Burst Mode Data Read For faster access to a complete message the burst read mode is applicable In burst read mode the complete message is copied from the internal message buffer to a tempo rary read buffer located outside the CAN memory section This allows read access without any wait if the CAN memory is accessed by the CAN mo
201. to handler address Maskable interrupt Branches to handler address or request executes the next instruction Executes the next instruction Remark f HALT mode is entered during execution of a particular interrupt handler and an unmasked interrupt request with a higher priority than the previous one is subsequently generated the program branches to the vector address for the latter interrupt 2 Release by RESET pin input This operation is the same as normal reset operation Preliminary User s Manual U15839EE1VOUMOO 257 9 4 5 IDLE Mode Chapter 9 Clock Generator In this mode the CPU clock is stopped resulting in stop of the entire system though the clock genera tors oscillator SSCG and PLL synthesizer continue to operate As it is not necessary to secure the oscillator oscillation stabilization time and the PLL lock up time it is possible to quickly switch to the normal operating mode in response to a release cause The IDLE mode can be entered by configuration the PSM and PSC registers In the IDLE mode program execution is stopped but the contents of all registers and internal RAM prior to entering this mode are retained On chip peripheral hardware operation is also stopped The state of the various hardware units in the IDLE mode is tabulated below Table 9 6 Operating States in IDLE Mode Items Operation Clock generator Operating SSCG PLL Operating Internal system clock Stopped W
202. to port input port output or peripheral functionNete 1 This register can be read or written in 1 bit and 8 bit units Figure 16 16 Port 4 Address At Reset 7 6 5 4 3 2 1 0 A BONUS NEG uo P4n n7 to 0 Input output port Remark In Input Mode When the P4 register is read the pin levels at that time are read Writing to the P4 register writes the values to that register This does not affect the input pins In Output Mode When the P4 register is read the values of P4 are read Writing to the P4 register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output and external interrupt request input Notes 1 lf using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register P4 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Alternate Pin Name Remarks Block Type TIG10 INTP10 TOG11 TIG11 TOG12 TIG12 Real time pulse unit RPU input or external TOG13 TIG13 interrupt request input TOG14 TIG14 TIG15 INTP15 564 Preliminary User s Manual U15839EE1V
203. transfer direction MSB first no interrupt delay single transfer mode operation mode CKP bit 0 DAP bit 1 SCKOn input output SO0n output SIOn input output Reg R W SOTBLn register P Yr Je sn CR register SIRBLn register CSOT bit INTCSIn interrupt Remarks 1 0 2 2 Reg R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBL n write was performed 410 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function b Clock phase selection The following shows the timing when changing the conditions for clock phase selection CKP bit of CSICn register and data phase selection DAP bit of CSICn register under the following conditions Data length 8 bits CCL bit of CSIMn register 0 e First bit of transfer data MSB DIR bit of CSIMn register 0 No interrupt request signal delay control CSIT bit of CSIMn register 0 Figure 13 35 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 SCKOn input output Slon input SOO0n output Reg Rw _ INTCSIn interrupt URS o S b When CKP bit 1 DAP bit 0 SCKOn input output Slon input SOO0n output Reg RW _ INTCSininterupt o coma DI Remarks 1 n 0to2 2 Reg_R W Internal signal This signal indicates that
204. used to meas ure the sub clock frequency by capture operation of the Watch timer interrupts The device can be switched to Watch mode during measurement operation To enable usage of the sub watch mode for real watch timer applications a sub oscillator calibration mode is implemented into Jupiter In this mode the actual sub clock frequency can be measured taking the main oscillator frequency as reference and the calculated watch time can be corrected according to the actual sub clock deviation The sub oscillator calibration mode is implemented in the following way Capture input for CCCO01 input channel of Timer C can be switched to watch timer interrupt output input of Timer can be clocked directly by the main oscillator with fx For the sub oscillator calibration the Timer C peripheral clock and the CCCO1 capture input need to be multiplexed Preliminary User s Manual U15839EE1VOUMOO 293 Chapter 10 Timer Figure 10 17 Multiplexed Inputs for Timer C Sub Oscillator Calibration Function fx OSC PSM CMODE Sub Clock Calibration CCCO01 Edge To use the sub oscillator calibration feature the watch timer clock must be derived from the sub oscillator This is the flow for sub oscillator calibration 1 Disable Timer CO 2 Enable sub oscillation calibration feature in Jupiter clock controller by setting the CMODE bit in the PSM register to 1 3 Enable Timer CO and set CCCO01
205. 0 receive only and store valid message in message buffer type 7 1 receive only and store valid message as in normal operation mode Remarks 1 The settings of the DGM bit are only effective in diagnostic mode MOM 1 In normal operation mode MOM 0 the DGM bit settings have no meaning When the diagnostic mode is active a valid reception is indicated by setting the VALID flag and depending on the setting on the setting of the DGM flag storing valid data either in a message buffer of buffer type 7 or in the same way as in normal operation mode The CAN pro tocol layer does not send an acknowledge error frame or transmit message and also the error counter does not count Defines the module operating mode 0 Normal operating mode 1 Diagnostic mode Remarks 1 The diagnostic mode provides the following functional behavior a Transmission of data frames and remote frames is not possible b No acknowledge is generated upon reception of a valid message c On reception of a valid message the VALID flag is set 1 d Receive and transmit error counters remain unchanged on errors The diagnostic mode can be used for baud rate detection and diagnos tic purposes Caution When the diagnostic mode MOM 1 is defined for a CAN module the CxBRP register is only accessible in the initialisation state ISTAT z 1 While ISTAT is cleared 0 write access to the CxBRP is prohib ited and reading the address of the CxBR
206. 0 0 0 0 OL Halfword External Halfword External Halfword External data data bus data data bus data data bus d When the data bus width is 8 bits Big Endian lt 1 gt Access to even address 2n lt 2 gt Access to odd address 2n 1 1 st Access 2 nd Access 1 st Access 2 nd Access 15 15 15 15 8 Address 8 Address 8 Address 8 Address 7 7 7 T 74 7 7 7 2n 2 1 2 1 2 2 0 0 0 0 0 0 0 0 Halfword External Halfword External Halfword External Halfword External data data bus data data bus data data bus data data bus 122 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 3 Word access 32 bits a When the bus width is 16 bits Little Endian 1 Access to address 4n 1 st Access 2 nd Access 31 31 24 24 23 23 16 Address 16 Address 15 15 15 15 4n 1 4n 3 8 8 8 8 7 7 7 7 4n 4n 2 0 0 0 0 Word data External Word data External data bus data bus lt 2 gt Access to address 4n 1 1 st Access 2 nd Access 3 rd Access 31 31 31 24 24 24 23 23 23 16 Address 16 Address 16 m Address 15 15 15 15 15 151 Lr 4n 1 am 4n 3 8 8 8 8 8 81 7 Tor cs 7 7 7 7 Por 4n 2 4n 4 0 0 0 0 0 0 Word data External Word data External Word data External data bus data bus data bus Preliminary User s Manual U15839EE1VOUMOO 123 124 Chapter 4 Bus Control Function 3 Access to address 4n 2 1 st Access 2 nd Access 31 31 24 24 23 23 16 Address 16 Address 15 15 15 15 4n 4
207. 0 9 8 Address Initial value IMRO GCCOS3MK GCCO2MK GCCO1MK GCCOOMK TMGO1MK TMGOOMK P5MK P4MK FFFFF100H FFFFH 7 6 5 4 3 2 1 0 P3MK P2MK P1MK POMK WTIMK TMD1MK TMDOMK WTMK 15 14 13 12 11 10 9 8 Address Initial value IMR1 1 MACMK ADMK CCCO1MK CCCOOMK TMCOMK GCC15MK GCC14MK FFFFF102H FFFFH 7 6 5 4 3 2 1 0 GCC13MK GCC12MK GCC11MK GCC10MK TMG11MK TMG10MK GCC05MK GCCO4MK 15 14 13 12 11 10 9 8 Address Initial value IMR2 SROMK SEROMK CSI2MK CSITMK CSIOMK FC4ERMK FC4TXMK FC4RXMK FFFFFI04H FFFFH 7 6 5 4 3 2 1 0 FC3ERMK FC3TXMK FC3RXMK FC2ERMK FC2TXMK FC2RXMK FC1ERMK FC1TXMK 15 14 13 12 11 10 9 8 Address Initial value IMR3 1 21 P20MK P15MK P10MK POSMK POOMK DOVFMK FFFFF106H FFFFH 6 5 4 3 2 1 0 7 Bit Position Function Interrupt mask flag 15100 0 Interrupt servicing enabled 1 Interrupt servicing disabled pending Remark Identification name of each peripheral unit WT TMD P TMG GCC AD MAC FC CSI UART DMA Preliminary User s Manual U15839EE1VOUMOO 219 Chapter 8 Processing Function 8 3 6 In service priority register ISPR This register holds the priority level of the maskable interrupt currently acknowledged When an inter rupt request is acknowledged the bit of this register corresponding to the priority level of that interrupt request is set to 1 a
208. 0 to m7 M DATAm0 to M DATAm m 00 to 31 1 2 7 6 5 4 3 2 1 is 7 Do5 Do2 DO1 aa Di7 D16 D15 D14 D12 D11 D10 ds F D27 D26 D25 D24 D23 D22 D21 D20 EU D37 D36 D35 D34 D33 D32 D31 D30 D4 7 D46 D45 D44 D42 D41 D40 EA D57 D56 D55 D54 D53 D52 D51 D50 gene D67 D66 D65 D64 D63 D62 D61 DEO cod D77 D76 D75 D74 D73 D72 D71 D70 478 Preliminary User s Manual U15839EE1VOUMOO Address OffsetNote 808H m x 20H 809H m x 20H 80AH m x 20H 80BH m x 20H 80CH m x 20H 80DH m x 20H 80EH m x 20H 80FH m x 20H Initial value undef undef undef undef undef undef undef undef Chapter 14 FCAN Interface Function Figure 14 28 Message Data Registers m0 to m7 M DATAmO0 to M DATAm 7 m 00 to 31 2 2 7100 M DATAmO Contents of the message data byte O first message data byte 7100 M DATAm 1 Contents of the message data byte 1 7100 M DATAm2 Contents of the message data byte 2 7100 M DATAm3 Contents of the message data byte 3 7100 M DATAm4 Contents of the message data byte 4 7100 M DATAm5 Contents of the message data byte 5 7100 M DATAm6 Contents of the message data byte 6 7100 M DATAm7 Contents of
209. 0030H nextPC TRAPOn Note 1 TRAP1n Note 1 ILGOP Illegal opcode DBTRAP DBTRAP instruction nterrupt INTWT WTIC Real Time Clock Divider Tick Watch timer 00000080H nextPC nterrupt INTTMDO TMDOIC Compare Match Timer DO 00000090H nextPC nterrupt INTTMD1 TMD1IC Compare Match Timer D1 000000A0H nextPC nterrupt INTWTI WTIIC Interval time Watch timer 000000B0H nextPC nterrupt INTPO POIC P61 Port Module 000000C0H nextPC nterrupt INTP1 P1IC P62 Port Module 000000D0H nextPC nterrupt INTP2 P2IC P63 Port Module 000000E0H nextPC nterrupt INTP3 P64 Port Module 000000F0H nextPC nterrupt INTP4 P4IC P52 Port Module 000001 nextPC nterrupt INTP5 P5IC P53 Port Module 000001 nextPC nterrupt INTTMG00 TMGOOIC 000001 nextPC nterrupt INTTMGO1 TMGO01IC 000001 nextPC nterrupt INTGCC00 GCCO0lC 000001 nextPC nterrupt INTGCC01 GCC011C 000001 nextPC nterrupt INTGCC02 GCCO021C 000001 nextPC nterrupt INTGCC03 GCCO3IC coincidence Chann Timer GO 000001 nextPC nterrupt INTGCC04 GCC04lC ICC coincidence Chann Timer G0 000001 nextPC C C C C C C C Exception TRAP instruction 00000040H nextPC Exception TRAP instruction 00000050H nextPC Exception 00000060H nextPC oj col NN Dm A wr Time base 0 Overflow Timer G0 Time base 1 Overflow Timer GO gt CC coincidence Chann Timer G0 CC coincidence
210. 0H Note 3 004H Note 3 002H Note 3 Notes 1 The address of a message buffer entry is calculated according to the following formula effective address PP BASE address offset 2 TRX transmit message 3 5 higher prior transmit messages assigned to message buffers with lower address values Preliminary User s Manual U15839EE1VOUMOO 445 2 Chapter 14 FCAN Interface Function Message reception Due to the vast initialisation possibilities for each message buffer in the FCAN system it is possi ble that a received message fits in several message buffers assigned to a CAN module A fixed rule according to the priority classes has been implemented to avoid arbitrary message storage and uncontrolled behaviour The storage priority for data frames and for remote frames is different refer to Table 14 12 and Table 14 13 Table 14 12 Storage Priority for Reception of Data Frames Priority Class Condition received data frame fits in non masked receive buffer received data frame fits in receive buffer linked to mask 0 received data frame fits in receive buffer linked to mask 1 received data frame fits in receive buffer linked to mask 2 received data frame fits in receive buffer linked to mask 3 Table 14 13 Storage priority for Reception of Remote Frames Priority Class Condition received remote frame fits in transmit buffer received remote frame fits in non mas
211. 1 Preliminary User s Manual U15839EE1VOUMOO 291 N C3 INTCCCO1 _ INTCCCOO interrupt _ 1 008 Chapter 10 Example output By setting the and TMCC01 registers as described below Timer C can output a PWM of an arbitrary frequency with the values that were set in advance in the CCCO0 and CCCO1 registers determining the intervals Setting method set corresponding port pins P5 to Timer C output PM5 to input PMC5 to Timer CO set CAE bit of TMCCOO register to 1 for activating the Timer C peripheral set the active level of TOCO output by the bit of the TMCCO 1 register here ALV 1 set ENT1 CMS1 and CMSO bits of TMCCO register to 1 leave CLR bit to 0 set CE bit to 1 to enable the counter and start operation Operation When the counter value of the TMCO register matches the setting value of the CCCOO register the TOCO output becomes active When the counter value of the TMCO register matches the setting value of the CCCO1 register the TOCO output becomes inactive This enables a PWM of an arbitrary frequency to be output Figure 10 16 Timing of PWM output operation detail TMCO P a 0000 0001 P register A A Count start Clear 1 1 44 CCCOO0 p p p p p _ CCCO01 q q q q
212. 1 The contents of this register can be read in the normal sequence 242 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 3 2 Clock Generator Status Register CGSTAT This is an 8 bit register that monitors the status of the SSCG and main oscillator hard macro operation This register can be read in 8 or 1 bit units Figure 9 3 Clock Generator Status Register CGSTAT 7 6 5 4 3 2 1 0 Address value Bit name Function Main clock stabilization indication bit determined by counter OSCSTAT 0 Main oscillator is not stabilized 1 Main oscillator is stabilized SSCG lock status determined by SSCG Lock signal SCSTAT 0 SSCG is not stabilized 1 SSCG is stabilized Preliminary User s Manual U15839EE1VOUMOO 243 Chapter 9 Clock Generator 9 3 3 Watchdog Timer Clock Control Register WCC This is an 8 bit register that controls the watchdog timer clock Data can be written to it only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang up See also PHCMD register This register can be read or written in 8 bit units Figure 9 4 Watchdog Timer Clock Control Register WCC 7 6 5 4 3 2 1 0 Address Mal value Specifies the clock source for the Watchdog WDTSELO Watchdog clock source Main oscillator fx WDTSEL1 WDTSELO Sub oscillator fxr Main oscillator 128 128 reserved Caution Data is set
213. 1 CxCTRL STOP 1 Normal Operation CxCTRL ISTAT 0 Power Offor WAKE 1 Interrupt Generation Detection ofbus SLEEP 1 and transition CANbus busy SLEEP 1 and CAN bus idle SLEEP Mode CxCTRL ISTAT 0 CxCTRL SLEEP 1 CxCTRL STOP 0 Remark 1 to 4 for the derivatives uPD703129 A uPD703129 A1 x 1 to 2 for the deriva tive UPD703128 A 514 Preliminary User s Manual U15839EE1VOUMO00 Chapter 14 FCAN Interface Function 14 4 5 Initialisation routines Below the necessary steps for correct start up of the CAN interface are explained Caution Itis very important that the software programmer observes the sequence given in the following paragraphs Otherwise unexpected operation of the CAN interface or any CAN module can occur 1 Global initialisation sequence for the CAN interface Before any operation on the CAN memory can be done it is essential that the common control register are initialised The general initialisation sequence is shown in Figure 14 46 Figure 14 46 General Initialisation Sequence for the CAN Interface INIT GLOBAL REGISTERS Set the common registers CGST but do not set GOM flag CGCS CGIE CGTSC CGTEN Clear all message buffers set at least MA 2 0 of each message buffer to 0 Enable global operation set GOM flag of register CGST
214. 1 10 9 8 7 6 5 4 3 2 1 O Address Initial value DDAH1 FFFFFO8EH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DDAH2 FFFFFO96H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DDAH3 FFFFFO9EH undef Bit Position Bit Name Function Specifies the DMA destination address 0 External memory or On chip peripheral I O 1 Internal RAM DA27 to Sets the DMA destination addresses A27 to A16 During DMA transfer it stores the DA16 next DMA transfer destination address 172 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 2 DMA destination address registers LO to L3 DDALO to DDAL3 These registers can be read written in 16 bit units Figure 7 4 DMA Destination Address Registers LO to L3 DDALO to DDAL3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DDALO FFFFF084H undef 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DDAL1 FFFFF08CH undef 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DDAL2 FFFFF094H undef 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value 15100 DA15 to Sets the DMA destination address A15 to AO During DMA transfer it stores the next DAO DMA transfer destination address Preliminary User s Manual U15839EE1VOUMOO 173 Chapter 7 DMA Functions DMA Controller 7 2 3 DMA transfer count registers 0 to 3 DBCO to DBC3 These 16 bit regis
215. 1 bit rate prescaler register in initialisation state only ISTAT 1 z CAN1 bus diagnostic in diagnostic mode C1DINF information register only 20 Notes 1 434 synchronization control register C1SYNC CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only The address of an interrupt pending register is calculated according to the following for mula effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO Address OffsetNote Chapter 14 FCAN Interface Function Table 14 6 Relative Addresses of CAN Module 2 Registers CAN mask 0 register L Access Type R W 1 bit 8 bits Comment lower half word MASK CAN2 mask 0 register upper half word MASKL CAN2 mask 1 register L lower half word MASK CAN2 mask 1 register H upper half word MASKL CAN2 mask 2 register L lower half word MASKH2 CAN2 mask 2 register upper half word MASKL3 CAN2 mask 3 register L lower half word MASKH3 CAN2 mask register upper half word C2CTRL CAN control register bit set clear function C2DEF CAN definition register bit set clear function C2LAST CAN2 information register read only error counter register read only interrupt enable registe
216. 11 1 M ID Hm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E ID14 ID13 ID12 ID11 1D10 ID7 105 ID4 ID3 ID2 ID1 810H undef m m x 20H Bit Position Bit Name Function Specifies the format of message identifier 0 Standard format mode 11 bit 1 Extended format mode 29 bit When IDE 0 standard format ID28 to ID18 specify the 11 bit identifier where ID28 is the most significant bit ID28 to ID17 ID16 contain received data bits Note 2 3 ID16 When IDE 1 extended format ID28 to ID16 specify the 13 most significant bits of the 29 bit identifier where ID28 is the most significant bit When IDE 0 standard format 1015 IDO contain received data bits ID15 to IDO 9 When IDE 1 extended format 1015 to IDO specify the 16 least significant bits of the 29 bit identifier Note 2 3 Notes 1 The register address is calculated according to the following formula effective address PP BASE address offset 2 In standard format mode IDE 0 these bits ID17 to IDO are only used for receive mes sage buffers linked to a mask Bits ID17 to ID10 storing the first data byte DO is stored where ID17 is the MSB Bits ID9 to ID2 storing the second data byte D1 where ID9 is the MSB Bits ID1 IDO contain the two most significant bits 7 and 6 of the third byte D2 3 When received message in standard format mode IDE 0 has less than 18 data bits the values of the not receive
217. 13 30 Figure 13 31 Figure 13 32 Figure 13 33 Figure 13 34 Figure 13 35 16 Timing of PWM operation match and 341 Timing when OOOOH is set in GCCnm match and clear 342 Timing when the same value as set in GCCn0 GCOCn5 is set in GCCnm match and clear t i e t deve especie Pete dii esed dra Hd iue ge 343 Timing when the value of GCCnm exceeding GCCn0 or GCCn5 match and clear irent ete ee petat de pee dade eee d esu et dade uas 344 Timing when GCCnm is rewritten during operation match and clear 345 Timing of Edge detection noise elimination 346 Block Diagram of Watch 349 Watch Timer Mode Control Register WTM 1 2 seen 350 Operation Timing of Watch Timer Interval Timer 355 Block Diagram of Watchdog Timer essen 357 Watchdog Timer Clock Selection Register 359 Watchdog Timer Mode Register WDTM 360 Watchdog Timer Mode Register WCMD 361 Watchdog Timer Mode Register 361 Asynchronous Serial Interfaces Block Diagram 366 Asynchr
218. 14 19 12 11 00 9 8 7 6 8 4 8 2 1 0 Address ta value Bit Position Bit Name Function Timer Gn Operation control 0 operation Stop the capture registers and TMGSTn register are cleared 15 POWER the TOGnm pins m 1 to 4 are inactive all the time 1 operation enable Remark At least 7 peripheral clocks fpc are need to start the timer function Set Output Delay Operation 0 Don t perform output delay operation 1 Set output delay to n count clocks OLDE Caution When the POWER Bit is set the rewriting of this Bit is prohibited Simultaneously writing with the POWER bit is allowed Remark The delay operation is used for EMI counter measures Selects internal count clock of TMG Count Clock 2 fecu k 4 8 CSEx2 13108 CSEx1 fecu 16 CSEx0 32 fpcik 64 Caution When the POWER Bit is set the rewriting of this Bits are prohibited Simultaneously writing with the POWER bit is allowed Remarks 1 0 1 2 peripheral clock Preliminary User s Manual U15839EE1VOUMOO 313 Chapter 10 Timer Bit Position Figure 10 30 Timer Gn Mode Register TMGMn 2 2 Bit Name CCSG5n CCSGOn Function Specifies the mode of the TMGnO TMGn1 CCSG5n for TMGn1 CCSGOn for TMGn0 0 Free run mode for TMGn1 TMGn0 GCCn5 GCCn0 in capture mode an detected edge at Pin TIGn5 TIGnO stores the value of TMGn1 TMGno0O in GCCn5 GC
219. 15839EE1VOUMOO 541 Chapter 15 A D Converter 15 7 How to read the A D Converter Characteristics Table Here special terms unique to the A D converter are explained 1 2 542 Resolution This is the minimum analog input voltage that can be identified That is the percentage of the ana log input voltage per bit of digital output is called 1LSB Least Significant Bit The percentage of 1LSB with respect to the full scale is expressed by FSR Full Scale Range When the resolution is 10 bits 1LSB 1 210 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by the overall error Overall Error This shows the maximum error value between the actual measured value and the theoretical value Zero scale error full scale error non linearity error and errors which are combinations of these express the overall error Note that the quantization error is not included in the overall error in the characteristics table Figure 15 14 Overall Error je 1 Ideal line 5 Q 5 5 Overall D error 0 T 0 AVREF Analog input Preliminary User s Manual U15839EE1VOUMOO Chapter 15 Converter 3 Quantization Error When analog values are converted to digital values a 1 2 LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2 LSB is converted to the same digital code so a quantization error cannot be avoided Not
220. 16 Mbit 1 M x 16 bits page ROM 4 word page access Internal address latch address PRC register setting ses ves n or ne ara A6 as M as A2 AL A0 Off page address On page address V Continuous reading possible 16 bit data bus width x 4 words V850E CA2 address output Page ROM address b In case of 16 Mbit 1 M x 16 bits page ROM 8 word page access Internal address latch address we is ae PRC register setting Comparison V850E CA2 address output 9 as A6 E AS ae at A0 Off page address On page address V Continuous reading possible 16 bit data bus width x 8 words Page ROM address Preliminary User s Manual U15839EE1VOUMOO 147 Chapter 5 Memory Access Control Function Figure 5 4 On Page Off Page Judgment during Page ROM Connection 2 2 c In case of 32 Mbit 2 M x 16 bits page ROM 16 word page access Internal address latch address MA5 MA4 0 0 1 1 ses nes wn o A e as AS M as 2 at ao Off page address On page address V Continuous reading possible 16 bit data bus width x 16 words PRC register setting V850E CA2 address output Page ROM address 148 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function 5 2 4 Page ROM configura
221. 17 M DATA317 Undefined xxxxn3FCH CAN message ID register L31 M IDL31 Undefined xxxxn3F2H CAN message ID register H31 M IDH31 Undefined xxxxn3FA4H CAN message configuration register 31 M CONFS1 Undefined xxxxn3F5H CAN message status register 31 M_STAT31 Undefined xxxxn3F7H CAN status set cancel register 31 SC STAT31 0000H xxxxn 1000H CAN stop register Note 1 CSTOP 0000H xxxxn 1004H CAN interrupt pending register CCINTP 0000H xxxxn 1010H CAN global status register Note 1 CGST 0100H xxxxn1012H CAN global interrupt enable register Note 1 CGIE 0A00H xxxxn1014H CAN main clock select register CGCS 7F05H xxxxn1016H CAN timer event enable register CGTEN 0000H xxxxn1018H CAN time stop count register CGTSC 0000H xxxxn101AH CAN message find start register CGMSS 0000H xxxxn101AH CAN message find result register CGMSR 0000H xxxxn101CH CAN test bus register CTBR 0000H xxxxn101DH CAN Macro Version Register CGREV Revision xxxxn101EH xxxxn101FH CAN Macro Revision Register CGVER Version xxxxn1020H CAN global interrupt pending register Nete 1 CGINTP 2 x x x x 00H xxxxn1022H CAN local interrupt pending register 1 C1INTP 00H xxxxn1024H CAN local int
222. 182 DWGO ete bot ap oer en poe v aed beeen itg er ee als 145 DWGO DWGH 222 Host Lats ME e ee e v MIR b sa 131 DWGT Situ mud edt o E ae e o uia Ue ii Ue E EPIO 145 E EGRU Ln petite LEM LEE Lee cm uM LAS ME URN LII M aa me 58 59 edge detection circuit essere n aree r a eens 346 Edge noise elimination 346 EIPG eno adda da Me Ga de ee ue rude nb ad eed 58 EIPSW n4 eco LM DIR ESL A Ru DC UE p re ace es yu RE 58 Element pointer oaasi raaa ea a e a E hh 57 Endian configuration register 117 ED exci ne e ar a eee n ENE AE a V aei ah doe Tol 229 escape from power save mode 583 Even Parity ete e ei eel ue CR EE cde E Reb a Peg n qs 368 eventcOuhter 2 2 iure ha tei Reb REIS RE Se be ad Gea LE Te RAI as 274 306 Exception status flag o i rss creare tiee o a o E 229 Preliminary User s Manual U15839EE1VOUMOO 603 Appendix Index exception table E E rns 70 Exceptlondrap edet eee eder ee P re ei ceret abt md epi iet e 230 Externall Qo3 sr ex tS cni uM Se ltd e tM d oe EAD UR D ri A ru ca UN 137 External ROM se ee aia en RUE e se
223. 1VOUMOO Chapter 13 Serial Interface Function 10 Clocked serial interface initial transmission buffer registers Low SOTBFLO to SOTBFL2 The SOTBFLn register is an 8 bit buffer register that stores initial transmission data in the repeat transfer mode n 0 to 2 The transmission operation is not started even if data is written to the SOTBFLn register These registers can be read written in 8 bit units The SOTBFLn register is the same as the lower bytes of the SOTBFn register Figure 13 31 Clocked Serial Interface Initial Transmission Buffer Registers Low SOTBFLO to SOTBFL2 Initial value SOTBFLO SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBFO FFFF FDO8H 00H SOTBFL1 SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBFO FFFF FD48H 00H SOTBFL2 SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBFO FFFF FD88H 00H 7 6 5 4 3 2 1 0 Address ELM to SOTBFO Store initial transmission data in repeat transfer mode Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIMO register 0 and only in the idle state CSOT bit of CSIMn register 0 If the SOTBFLn register is accessed during data transfer the data cannot be guaranteed Preliminary User s Manual U15839EE1VOUMOO 405 Chapter 13 Serial Interface Function 11 Serial I O shift registers SIOO to SIO2 The SIOn register is a 16 bit shift register that converts p
224. 1VOUMOO 327 Chapter 10 Timer c Timing of starting capture trigger edge detection A capture trigger input signal TIGny is synchronized in the noise eliminator for internal use Edge detection starts when 1 count clock period has been input after timer count operation starts This is because masking is performed to prevent the initial TIGny level from being recognized as an edge by mistake The timing chart for starting edge detection is shown below Basic settings x 0 1 and y 0 to 5 Remark Count clock fpc 4 detection of both edges Figure 10 43 Timing of starting capture trigger edge detection Invalid edge input Edge detection start e COUNTx TMGOE TMG1E SS ENFGO ENFG1 count upO count up1 TIGny i INTCCGny GCCny X 0005H 328 Preliminary User s Manual U15839EE1VOUMOO 2 Chapter 10 Timer Compare operation free run Basic settings m 1 to 4 free run mode disable TOGnm Compare mode for GCCnm assign counter for GCCnm 0 TMGnO 1 TMGn1 a Example Interval timer free run Setting method interval timer An usable compare register is one of GCCn1 to GCCn4 and the corresponding counter TMGnO or TMGn1 must be selected with the TBGm bit Sele
225. 2 Transmit operation on page 376 When TXBF bit 1 in the ASIFn register writing must not be performed to TXBn register This register can be read or written in 8 bit or 1 bit units n O 1 Figure 13 6 Transmission Buffer Registers TXBO TXB1 Initial value TXBO FFFFFAO4H FFH TXB1 FFFFFA44H FFH 7 6 5 4 3 2 1 0 Address TXB7 to TXBO Writes transmit data Preliminary User s Manual U15839EE1VOUMOO 373 Chapter 13 Serial Interface Function 13 2 4 Interrupt requests The following three types of interrupt requests are generated from UART50 UART51 Reception error interrupt INTSERn Reception completion interrupt INTSRn Transmission completion interrupt INTSTn The default priorities among these three types of interrupt requests is from high to low reception error interrupt reception completion interrupt and transmission completion interrupt n 0 1 1 2 3 374 Table 13 1 Generated Interrupts and Default Priorities Interrupt Priority Reception error Reception completion Transmission completion Reception error interrupt INTSERO INTSER1 When reception is enabled a reception error interrupt is generated according to the logical OR of the three types of reception errors explained for the ASISn register Whether a reception error interrupt INTSERn or a reception completion interrupt INTSRn is generated when an error occurs can be specified according to the
226. 2 159 MODEO to MODES Re bated et eu he geet Gen duane Pikes i eaten 49 Multiple interrupt processing control 234 N uud ER eat mM 49 NMUpirtinput nh meh betas yen eel ae EROR CHER X RP Ore 203 eter fed ue Metis Og td het Miserere aie cede ares ede 203 207 NMIWDBT E cene bles en ees Aare ote ee A att ttn 203 as Gusta duh ie Gud weld be Lucr Leda eus ange bii 369 Noise elimiriation reas ER ETE EARA LEER ME REIP 583 rioise eliminatiori x Rm ERI Ier MER SU RA e MER VERRE RR ERE ERES 346 rioise ellmliniator x eee netsh DRE ste bunds rn HER QE eu Hg 328 noise eliminatoh 522 e Rer esei9 eee eei esee qe x ue er Gaile date d bI uus 327 Nonlinearity Error vie hoses aA eee dae pex oda potes te DT Rex os 544 Non maskable interrupt sser sia EE E ENAT hr hn 203 Non maskable interrupt status flag 208 Non maskable watchdog timer interrupt request 203 Preliminary User s Manual U15839EE1VOUMOO 605 Appendix Index Nom PINS r Eea ki ne exe Fav ees ve e E RR EGRE IANUE BEER vue P Dev at Seg Re ie E ues 36 INP Lieu borrados efi at ere fies e vata aed 208
227. 29 A1 x 1 to 2 for the derivative uPD703128 A These registers can be read only in 8 bit and 16 bit units Figure 14 36 CAN 1 to 4 Information Registers CTLAST to CALAST Address Initial OffsetNote 1 value CILAST 0 0 0 0 LERR3 LERR2 LERR LERRO LREC7 LREC6 LRECA4 LREC3 LREC2 LRECT LRECO 1054H 00FFH C2LAST 0 0 0 0 JLERR3 LERR2 LERR1 LERRO LREC LREC6 LRECS LREC4 LREC3 LREC2 LREC1 LRECO 1094H OOFFH O3LAST 0 0 0 0 LERR3 LERR2 LERR1 LERRO LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LRECO 1004 OOFFH C4LAST LERR2 1 LREC LREC6 LREC5 LREC4 LREC3 LREC2 1114H OOFFH Code of Last CAN Protocol Error No error reset state only CAN bus bit error CAN bus stuff error CAN bus CRC error CAN bus form error LERRS to LERRO CAN bus acknowledgement error CAN bus arbitration lost Nete 2 CAN module overrun error 0 CAN wake up from CAN bus Others than above Reserved o ojojo Remark The LERR3 to LERRO bits cannot be cleared Thus these bits remain unchanged until the next error occurs Holds the message buffer number of the last received message LREC7 to LRECO Receive Message Buffer Number LRECO 0 to 31 Message buffer number of the last received message LREC7 to 32 to 255 Reserved not possible Notes 1 The register address is c
228. 3 M EVT103 Undefined xxxxn144H CAN message data length register 10 M DLC10 Undefined xxxxn145H CAN message control register 10 M CTRL10 Undefined xxxxn146H CAN message time stamp register 10 M TIME10 Undefined xxxxn148H CAN message data register 100 Preliminary User s Manual U15839EE1VOUMOO M DATA100 Undefined 89 xxxxn149H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 6 18 Function Register Name CAN message data register 101 M DATA101 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn14AH CAN message data register 102 M DATA102 Undefined xxxxn14BH CAN message data register 103 M DATA103 Undefined xxxxn14CH CAN message data register 104 M DATA104 Undefined xxxxn14DH CAN message data register 105 M DATA105 Undefined xxxxn14EH CAN message data register 106 M DATA106 Undefined xxxxn14FH CAN message data register 107 M DATA107 Undefined xxxxn150H CAN message ID register L10 M IDL10 Undefined xxxxn152H CAN message ID register H10 M IDH10 Undefined xxxxn154H CAN message configuration register 10 M CONF10 Undefined xxxxn155H CAN message status register 10 M STAT10 Undefined xxxxn156H CAN status set cancel register 10 SC STAT10
229. 4 8 Preliminary User s Manual U15839EE1VOUMOO 7 10 Forcible 1 195 7 11 Forcible 196 7 12 DMA Transfer 1 197 7 12 1 DMA transfer end 1 197 7 12 2 Terminal count output upon DMA transfer 197 7 139 sed REE RENEE KEE dr ene RARI PS 198 Chapter8 Interrupt Exception Processing Function 199 8 1 Features 252 sted Pt l RARI RI ee ee Ag 199 8 2 Interrupts 203 8 21 Operation ciue nite eet es angie Pad engin Rue 206 8 22 ICI MR IEEE 207 8 2 3 Non maskable interrupt status flag 208 8 2 4 Edge Detection Function 208 8 3 Maskable Interrupts 209 9 3 1 Operation er eh drei be Ro rene nee es 209 8 3 2 He6StOIlG 0 ee ILES 211 8 3 3 Priorities of maskable 1 212 8 3 4 Interrupt control register 216 8 3 5 Interrupt mask regist
230. 4 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSAL2 FFFFF090H undef 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value ssa Bus pes pes pesa SK er SA 996 8 96 96 5 S6 S EM SAO FH andet 15100 15 Sets the DMA source address A15 to AO During DMA transfer it stores the next SAO DMA transfer source address Preliminary User s Manual U15839EE1VOUMOO 171 Chapter 7 DMA Functions DMA Controller 7 2 2 DMA destination address registers to DDAHO to DDAH3 These registers are used to set the DMA destination address 28 bits each for DMA channel n n 0 to 3 They are divided into two 16 bit registers DDAHn and DDAL n Since these registers are configured as 2 stage FIFO buffer registers a new destination address for DMA transfer can be specified during DMA transfer refer to 7 3 Next Address Setting Function 1 DMA destination address registers DDAHO to DDAH3 DDAHO to DDAH3 These registers can be read written in 16 bit units Caution When setting an address of a peripheral I O register for the destination address be sure to specify an address between FFFF000H and FFFFFFFH An address of the peripheral I O register image 3FFF000H to 3FFFFFFH must not be specified Figure 7 3 DMA Destination Address Registers 0H to 3H DDAOH to DDA3H 15 14 13 12 11 0 9 8 7 6 5 4 3 2 1 Address Initial value DDAHO undef 15 14 13 12 1
231. 7150 Ma EE 139008 Controls the clock supply for the complete FCAN system The CSTP flag can be used to reduce the power consumption when the FCAN system is set to SLEEP mode and STOP mode to a minimum 0 FCAN system is supplied with clock fyem 1 Clock supply of the FCAN system is stopped Remark When switching off the clock supply of the FCAN system during SLEEP mode wake up by CAN bus activity is possible But instead of CxINT4 interrupt i e wake up from SLEEP mode interrupt the GINTS interrupt must be used Cautions 1 In case CSTP is set 1 access to the register and buffer of the FCAN system is impossible except access to the CSTOP register Do not set CSTP 1 while the FCAN system is under normal oper ation especially while a CAN module handles messages on the CAN bus A sudden stop of the FCAN system might cause mal functions of the entire CAN network Note The address of an interrupt pending register is calculated according to the following formula effective address PP BASE address offset 454 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 2 main clock select register CGCS The CGCS register controls the internal memory access clock fmem which is used as main clock for each CAN module as well as the global time system clock fas used for the time stamp func tion and event generation For details refer to chapter 14 2 3 Clock structur
232. A x 1 to 4 for the derivatives PD703129 A and 0703129 A1 448 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 2 8 Remote frame handling The FCAN macro offers enhanced features for generating remote frames and for the reaction of a CAN module upon remote frames 1 Generation of a remote frame According to the CAN specification a remote frame has the same format as a data frame except the RTR bit of the control field which has recessive level and the data field which is omitted com pletely By means of a remote frame receiving nodes can request the transmitting node of a particular message for sending an update of that message to the CAN bus Usually remote frames are gen erated from CAN nodes which do not provide the requested message by themselves In the FCAN system a remote frame is automatically sent when setting the transmit request bit TRQ of the M STATm register for a message buffer defined as receive message buffer m 00 to 31 Same as for generating a data frame from a transmit message buffer the ready bit RDY of M STATm register must be set 1 Remote frames can also be generated by means of a transmit message buffer by setting the RTR bit of the M CTRLm register and using the same transmission procedure as for data frames However from application point of view that method is not recommended because it consumes message buffer resources unnecessarily A data frame in
233. A16 to A23 PAHO to PAH7 Port AH PMCAH Chip select CS0 CS3 and CS4 PCSO PCS3 and PCS4 Port CS PMCCS Read write control LWR UWR RD PCTO PCT1 PCT4 Port CT PMCCT Internal system clock WAIT PCMO Port CM PMCCM Preliminary User s Manual U15839EE1VOUMOO 109 Chapter 4 Bus Control Function 4 3 Memory Block Function The 64 MB memory space is divided into memory blocks of 2 MB 4 MB and 8 MB units Figure 4 1 Memory Block Function 3FFF FFFH Block 15 Internal peripheral I O area 4 Kb ytes 3E00 000H 2 Mbytes 1 3FFF tou 3DFF FFFH Block 14 3C00 000H 2 Mbytes CS7 CSE CSE CS4 3FFE 7FFH CS7 099 096 CS4 3BFF FFFH Block 13 Internal RAM area 16 Kbytes 3A00 000H 2 Mbytes 3FF8 000H 39FF FFFH Block 12 ER 3800 0009 2 Mbytes 37FF FFFH 56 54 Block 10 4 Mbytes 3000 OOOH 2FFF FFFH Block 9 8 Mbytes Rem 2800 000H CS4 27FF FFFH l 2000 000H FFFH External memory area ER 1800 000H CS3 17FF FFFH Block 6 8 Mbytes 1000 OOOH OFFF FFFH Block 5 4 Mbytes C81 S3 DEDE Block 4 4 Mbytes 0800 0008 O7FF FFFH Block 3 0600 000H 2 Mbytes OSFF FFFH DE i 0400 000H ytes 50 CS2 CS1 53 FFEH Bock 0200 000H 2 Mbytes O1FF FFFH Block 0 2 Mbytes L 0000 000 I 110 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 3 1 Chip S
234. A2 64 MB physical address space is seen as 64 images in the 4 GB CPU address space The highest bit bit 25 of this 26 bit address is assigned as address sign extended to 32 bits Figure 3 14 Example Application of wrap around uPD703129 0000 7FFFH 7777777777775 External ROM area 32 Kbytes R 0000 0000H Y i Internal peripheral i 4 Kl FFFF F000H I O area bytes FFFF EFFFH 12 Kbytes 32 Kbytes FFFF Y FFFF BFFFH i Internal RAM area 16 Kbytes FFFF 8000H Y 1 When R r0 zero register is specified with the LD ST disp16 R instruction an addressing range of 0000 0000H 32 KB can be referenced with the sign extended 16 bit displacement value The zero register rO is a register set to 0 by hardware and eliminates the need for additional registers for the pointer Preliminary User s Manual U15839EE1VOUMOO 75 Chapter 3 CPU Function 3 5 3 Peripheral I O Registers Table 3 6 List of Peripheral I O Registers 1 7 Bit Units Address Function Register Name for Manipulation 1 bit 8 bit 16 bit FFFF F002 Port AH 00H FFFF F008 Port CS undefined FFFF F00A Port CT undefined FFFF FOOC Port CM undefined FFFF F022 Port AH mode 0000H FFFF F028 Port CS mode 18H FFFF F02A Port CT mode 13H FFFF F02C Port CM mode 01H FFFF F042 Port AH mode control FFH FFFF F048 Port
235. AN message data register 170 M DATA170 Undefined Xxxxn229H CAN message data register 171 M_DATA171 Undefined Xxxxn22AH CAN message data register 172 M_DATA172 Undefined xxxxn22BH CAN message data register 173 M DATA173 Undefined Xxxxn22CH CAN message data register 174 M DATA174 Undefined xxxxn22DH CAN message data register 175 M DATA175 Undefined xxxxn22EH CAN message data register 176 M DATA176 Undefined xxxxn22FH CAN message data register 177 M DATA177 X XJ K XxXxX KL Xx Xx Undefined xxxxn230H CAN message ID register L17 M_IDL17 Undefined xxxxn232H CAN message ID register H17 M_IDH17 Undefined xxxxn234H CAN message configuration register 17 M CONF17 Undefined Xxxxn235H CAN message status register 17 M STAT17 Undefined Xxxxn236H CAN status set cancel register 17 SC_STAT17 0000H xxxxn240H CAN message event pointer 180 M EVT180 Undefined xxxxn241H CAN message event pointer 181 M EVT181 Undefined xxxxn242H CAN message event pointer 182 M EVT182 Undefined xxxxn243H CAN message event pointer 183 M EVT183 Undefined xxxxn244H CAN message data length register 18 M DLC18 Undefined xxxxn245H CAN message control register 18 M CTRL18 Undefined xxxxn246H CAN message time stamp register 18 M TIME18
236. AN message data register 261 M_DATA261 Undefined Xxxxn34AH CAN message data register 262 M DATA262 Undefined xxxxn34BH CAN message data register 263 M DATA263 Undefined xxxxn34CH CAN message data register 264 M DATA264 Undefined xxxxn34DH CAN message data register 265 M DATA265 Undefined xxxxn34EH CAN message data register 266 M DATA266 Undefined xxxxn34FH CAN message data register 267 M DATA267 X XXIX XxX XxX XxX x Undefined xxxxn350H CAN message ID register L26 M_IDL26 Undefined xxxxn352H CAN message ID register H26 M IDH26 Undefined xxxxn354H CAN message configuration register 26 M CONF26 Undefined xxxxn355H CAN message status register 26 M STAT26 Undefined xxxxn356H CAN status set cancel register 26 SC STAT26 0000H Xxxxn360H CAN message event pointer 270 M_EVT270 Undefined xxxxn361H CAN message event pointer 271 M EVT271 Undefined xxxxn362H CAN message event pointer 272 M EVT272 Undefined Xxxxn363H CAN message event pointer 273 Preliminary User s Manual U15839EE1VOUMOO M_EVT273 Undefined 97 Address xxxxn364H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 14 18 Function Register Name CAN message data length register 27 M DLC27 Bit Units for Manipula
237. AO71 Undefined XXxxnOEAH CAN message data register 072 M_DATA072 Undefined XxxxnOEBH CAN message data register 073 M DATAO73 Undefined xxxxnOECH CAN message data register 074 M DATAO74 Undefined xxxxnOEDH CAN message data register 075 M DATAO75 Undefined XxxxnOEEH CAN message data register 076 M DATAO76 Undefined XxxxnOEFH CAN message data register 077 M DATAO77 Undefined xxxxnOFOH CAN message ID register L07 M IDLO7 Undefined XxxxnOF2H CAN message ID register H07 M IDHO7 Undefined xxxxnOFAH CAN message configuration register 07 M CONFO7 Undefined XxxxnOF5H CAN message status register 07 M STATO7 Undefined xxxxnOF6H CAN status set cancel register 07 SC STAT07 0000H xxxxn100H CAN message event pointer 080 M EVTO80 Undefined xxxxn101H CAN message event pointer 081 M EVTO81 Undefined xxxxn102H CAN message event pointer 082 M EVTO082 Undefined xxxxn103H CAN message event pointer 083 M EVTO083 Undefined xxxxn104H CAN message data length register 08 M DLC08 Undefined xxxxn105H 88 CAN message control register 08 M CTRLO08 Preliminary User s Manual U15839EE1VOUMOO Undefined Address xxxxn106H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O
238. BELn register is the same as the lower bytes of the SIRBn register It is used to read the contents of the SIRBLn register Clocked serial interface transmission buffer registers SOTBO to SOTB2 The SOTBn register is a 16 bit buffer register that stores transmit data Clocked serial interface transmission buffer registers Low SOTBLO to SOTBL2 The SOTBLn register is an 8 bit buffer register that stores transmit data Clocked serial interface initial transmission buffer registers SOTBFO to SOTBF2 The SOTBFn register is a 16 bit buffer register that stores the initial transmit data in the repeat transfer mode Preliminary User s Manual U15839EE1VOUMOO 393 Chapter 13 Serial Interface Function 12 Clocked serial interface initial transmission buffer registers Low SOTBFLO to SOTBFL2 The SOTBFLn register is an 8 bit buffer register that stores initial transmit data the repeat transfer mode 13 Selector The selector selects the serial clock to be used 14 Serial clock control circuit Controls the serial clock supply to the shift register Also controls the clock output to the SCKOn pin when the internal clock is used 15 Serial clock counter Counts the serial clock output or input during transmission reception operation and checks whether 8 bit data transmission reception has been performed 16 Interrupt control circuit Controls the interrupt request timing Figure 13 21 Block Diagram of Clocked Serial Inter
239. Bn register When the 8 bit data length CCL bit of CSIMn register 0 has been set read the SIRBLn register 2 When the 16 bit data length CCL bit of CSIMn register 1 has been set write to the SOTBn register When the 8 bit data length CCL bit of CSIMn register 0 has been set write to the SOTBLn register Caution When the CSOT bit of the CSIMn register 1 do not manipulate the CSIOn register 408 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function Figure 13 34 Timing Chart in single Transfer Mode 1 2 a In transmission reception mode data length 8 bits transfer direction MSB first no interrupt delay single transfer mode operation mode CKP bit 0 DAP bit 0 SCKOn input output N SO0n 0 output SIOn input Reg R W ZW AU Write 55H to SOTBLn register SS SOTBLn register AE UB ER NU 55H transmit data meee eae register SIRBLn register AAH CSOT bit INTCSIn interrupt Remarks 1 n 0to2 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed Preliminary User s Manual U15839EE1VOUMOO 409 Chapter 13 Serial Interface Function Figure 13 34 Timing Chart in single Transfer Mode 2 2 b In transmission reception mode data length 8 bits
240. CAN message data register 062 M_DATA062 Undefined xxxxnOCBH CAN message data register 063 M_DATA063 Undefined XxxxnOCCH CAN message data register 064 M_DATA064 Undefined xxxxnOCDH CAN message data register 065 M DATAO65 Undefined XxxxnOCEH CAN message data register 066 M_DATA066 Undefined XxxxnOCFH CAN message data register 067 M_DATA067 Undefined xxxxnODOH CAN message ID register L06 M_IDLO6 Undefined xxxxnOD2H CAN message ID register H06 M IDHO6 Undefined xxxxnOD4H CAN message configuration register 06 M CONFO06 Undefined xxxxnOD5H CAN message status register 06 M STATO6G Undefined xxxxnOD6H CAN status set cancel register 06 SC STATO6 0000H xxxxnOEOH CAN message event pointer 070 M EVTO70 Undefined xxxxnOE 1H CAN message event pointer 071 M EVTO71 Undefined xxxxnOE2H CAN message event pointer 072 M_EVT072 Undefined XxxxnOE3H CAN message event pointer 073 M_EVT073 Undefined xxxxnOE4H CAN message data length register 07 M DLCO7 Undefined xxxxnOE5H CAN message control register 07 M CTRLO7 Undefined xxxxnOE6H CAN message time stamp register 07 M TIMEO7 Undefined XxxxnOE8H CAN message data register 070 M DATAO70 Undefined xxxxnOE9H CAN message data register 071 M DAT
241. CAN message event pointer 293 M_EVT293 Undefined xxxxn3A4H CAN message data length register 29 M DLC29 Undefined Xxxxn3A5H 98 CAN message control register 29 M_CTRL29 Preliminary User s Manual U15839EE1VOUMOO Undefined Address Xxxxn3A6H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 15 18 Function Register Name CAN message time stamp register 29 M TIME29 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined XXxxn3A8H CAN message data register 290 M DATA290 Undefined XXxxn3A9H CAN message data register 291 M DATA291 Undefined XXXxxn3AAH CAN message data register 292 M DATA292 Undefined xxxxn3ABH CAN message data register 293 M DATA293 Undefined XXxxn3ACH CAN message data register 294 M DATA294 Undefined xxxxn3 ADH CAN message data register 295 M DATA295 Undefined Xxxxn3AEH CAN message data register 296 M DATA296 Undefined Xxxxn3AFH CAN message data register 297 M_DATA297 X XJI XJI XIX XxX Xx Xx Undefined xxxxn3BOH CAN message ID register L29 M IDL29 Undefined xxxxn3B2H CAN message ID register H29 M IDH29 Undefined xxxxn3B4H CAN message configuration register 29 M CONF29 Undefined xxxxn3B5H CAN message status register 29 M STAT29 Undef
242. CC coincidence Channel 2 0000 0170H CC coincidence Channel 3 0000 0180H CC coincidence Channel 4 0000 0190H CC coincidence Channel 5 0000 01A0H Time base 0 Overflow 0000 01BOH Time base 1 Overflow 0000 01C0H CC coincidence Channel 0 0000 01D0H CC coincidence Channel 1 0000 01E0H CC coincidence Channel 2 0000 01FOH CC coincidence Channel 3 0000 0200H CC coincidence Channel 4 0000 0210H CC coincidence Channel 5 0000 0220H Time base Overflow 0000 0230H CC coincidence Channel 0 0000 0240H CC coincidence Channel 1 0000 0250H A D conversion end 0000 0260H MAC Interrupt CGINTP 1 2 0000 0270H CAN 1 Receive Interrupt 0000 0280H CAN 1 Transmit Interrupt 0000 0290H CAN1 Error Interrupt 0000 02A0H CAN Receive Interrupt 0000 02B0H CAN Transmit Interrupt 0000 02COH CAN Error Interrupt 0000 02D0H CANS Receive Interrupt 0000 02E0H CANS Transmit Interrupt 0000 02F0H CANS Error Interrupt 0000 0300H CAN4 Receive Interrupt 0000 0310H CAN4 Transmit Interrupt 0000 0320H CAN4 Error Interrupt 0000 0330H Transmission Reception Completion CSIO 0000 0340H Transmission Reception Completion CSI1 0000 0350H Transmission Reception Completion CSI2 0000 0360H Reception Error UART50 0000 0370H Reception Completi
243. CCO00 CCCO1 always set the CAE bit to 1 first When the CAE bit is 0 even if writing to registers and CCC01 the data that is written will be invalid because the reset is asynchronous 3 Perform a write operation to capture compare registers 0 and 1 after setting them to compare registers according to the TMCCO1 register setting If they are set to capture registers CMS1 and CMSO bits of TMCC01 register 0 no data is written even if a write operation is performed to CCC00 and CCCO01 4 When these registers are set to compare registers the INTCCCOO or INTCCCO1 interrupt can not be used for generating interrupts for external inputs edges Preliminary User s Manual U15839EE1VOUMOO 277 Chapter 10 Timer 10 1 4 Control registers 1 Timer C control register 0 TMCCOO The TMCCOO register controls the operation of TMCO This register can be read written in 8 bit or 1 bit units Caution The CAE bit and CE bit cannot be set at the same time Be sure to set the CAE bit prior to setting the CE bit To use an external pin related to the timer function when using Timer C be sure to set the CAE bit to 1 after setting the external pin to the control mode Figure 10 5 Timer C control Register 0 TMCCOO 1 2 7 6 5 4 3 2 1 0 Address ital value Bit Position Bit Name Function Flag that indicates TMCO overflow 0 No overflow 1 Overflow The OVF bit becomes 1 when TMCO changes from FFFFH to 0000H An overflow
244. CCOO register is set to 1 and an overflow interrupt INTTMCO is generated at the same time However if the CCCOO register is set to compare mode CMSO 1 and to the value FFFFH when match clearing is enabled CCLR 1 the TMCO counter register is considered to be cleared and the OVF bit is not set to 1 when the TMCO counter register changes from FFFFH to OOOOH Also the overflow interrupt INTTMCO is not generated When the TMCO counter register is changed from FFFFH to 0000H because the CE bit changes from 1 to the TMCO register is considered to be cleared but the OVF bit is not set to 1 and no INTTMCO interrupt is generated Also timer operation can be stopped after an overflow by setting the OST bit of the TMCCO1 register to 1 When the timer is stopped due to an overflow the count operation is not restarted until the CE bit of the TMCCOO register is set to 1 Operation is not affected even if the CE bit is set to 1 during a count operation Figure 10 9 Timing of interrupt operation after overflow Overflow Overflow TMCO CE lt 1 lt 1 INTTMCO y 284 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 3 Capture operation The TMCO register has two capture compare registers These are the CCCOO register and the CCC01 register A capture operation or a compare operation is performed according to the settings of both the CMS1 CMSO bits of the TMCC01 register If t
245. CE bit of the TMCDn register is cleared to 0 a reset is performed synchronized with the internal clock Similarly a synchronized reset is performed after a match with the CMDn register and after an overflow 3 The count clock must not be changed during a timer operation If it is to be overwritten it should be overwritten after the CE bit is cleared to 0 4 Up to 2 clocks are required after a value is set in the CE bit until the set value is transferred to internal units When a count operation begins the count cycle from 0000H to 0001H differs from subsequent count cycles 5 After a compare match is generated the timer is cleared at the next count clock Therefore if the division ratio is large the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 2 Timer Dn compare register CMDn n 0 1 CMDn and the TMDn registers count value are compared and an interrupt request signal INTTMDn is generated when a match occurs TMDn is cleared synchronized with this match If the CAE bit of the TMCDn register is set to 0 a reset is performed asynchronously and the registers are initialized n 0 1 The CMDn register is configured with a master slave configuration When a write operation to a CMDn register is performed data is first written to the master register and then the master register s da
246. CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 8 27 illustrates the restore processing from a debug trap Figure 8 27 Restore Processing from Debug Trap DBRET instruction Jump to address of restored PC Preliminary User s Manual U15839EE1VOUMOO 233 Chapter8 Interrupt Exception Processing Function 8 7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level and the higher priority interrupt request is received and processed first If there is an interrupt request with a lower priority level than the interrupt request currently being proc essed that interrupt request is held pending Maskable interrupt multiple processing control is executed when an interrupt has an enable status ID 0 Thus if multiple interrupts are executed it is necessary to have an interrupt enable status ID 0 even for an interrupt processing routine If a maskable interrupt enable or a software exception is generated in a maskable interrupt or software exception service program it is necessary to save EIPC and EIPSW This is accomplished by the following procedure 1 Acknowledgmen
247. CSICO to CSIC2 The CSICn register is an 8 bit register that controls the CSIOn transfer operation n 0 to 2 This register can be read written in 8 bit or 1 bit units Figure 13 23 Clocked Serial Interface Clock Selection Registers CSICO to CSIC2 1 2 Initial value 7 6 5 4 3 2 1 0 Address Specifies operation mode DAP Operation Mode SCKOn l l l soon DO7XDO6XDO5XDO4XDO3XDO2XDO1XDO0 Slon X DIS X DIB X DIO SCKOn l l soon _ XDO7XDOSXDO5XDO4XDO3XDO2XDO1XD00 43 CKP DAP o Xp Xo pu o Kon SCKOn l 800 D07XDO6XDOSXDO4XDO3XDO2XDO1XDOO Slon X pis X D14 X Dia X D12 X Dit X DIO Soon __XDO7XDO6XDOSXDO4KDO3XDO2XDO1XDOO sion ADI6 X Dis X D14 X Dis X D12 X D11 X DIO Remark n 0to2 396 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function Figure 13 23 Clocked Serial Interface Clock Selection Registers CSICO to CSIC2 2 2 Specifies input clock CKSO Input Clock Mode 4 Master mode Internal BRG Channel 0 Master mode Internal BRG Channel 1 Master mode f 8 Master mode CKS2 to Rye CKSO 16 Master mode fpcik 32 Master mode fpcik 64 Master mode External clock SCKOn Slave mode Remarks 1 fpc internal peripheral clock frequency 2 0102 Caution The CSICn register be overwritten only when the CSIE bit of the
248. Chapter 10 Timer a When CCCOO0 register is set to 0000H If the CCCOO register is set to 0000H the OOOOH after the TMCO register counts up from FFFFH to 0000H is judged as a match The 0000H when the TMCO register begins counting is not judged as a match b When match clearing is enabled If match clearing is enabled CLR bit 1 for the CCCOO register the TMCO register is cleared when a match with the TMCO register occurs during a compare operation c Example Interval timer By setting the and TMCCO 1 registers as described below Timer C operates as an interval timer that repeatedly generates interrupt requests with the value that was set in advance in the CCCOO register as the interval Setting method set corresponding port pins P5 to Timer C input PM5 to input PMC5 to Timer CO 1 2 set CAE bit to 1 for activate the Timer C peripheral 3 set CLR and CMSO bit of TMCCO 1 register to 1 4 set CE bit to enable the counter and start operation Operation 1 When the counter value of the TMCO register matches the setting value of the CCCOO register the TMCO register is cleared 0000H 2 An interrupt request signal INTCCCOO is generated at the same time that the count operation resumes Figure 10 14 Timing of interval timer operation t E f Count start Clear Clear CCCOO0 p INTCCCOO interrupt Interval time Interval
249. Cn0 and an interrupt INTCCGn5 INTCCGn0 is output 1 Match and Clear mode of the TMGn1 TMGn0 GCCn5 GCCn0 in compare mode when the data of GCCn5 GCCn0 match the count value of the TMGn1 TMGn0 the counter is cleared and the interrupt INTCCGn5 INTCCGnO occurs Caution When the POWER bit is set the rewriting of this Bits are prohibited Simultaneously writing with the POWER bit is allowed Specifies software clear for TMGx x 0 1 0 Continue TMGx operation 1 Clears 0 the count value of TMGx the corresponding TOGx is deactivated Remark TMGx starts 1 peripheral clock after this bit is set this bit is not readable always read 0 314 Specifies TMGx x 0 1 count operation enable disable 0 Stop count operation the counter holds the immediate preceding value the corresponding TOGx is deactivated 1 Enable count operation Remarks 1 the counter needs at least 1 peripheral clock fpc to stop 2 the counter needs at least 4 peripheral clocks fpc to start Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 2 Timer Gn Mode Register Low TMGMnL n 0 1 This register is the low byte of the TMGMn register This register can be read written in 8 bit or 1 bit units Figure 10 31 Timer Gn Mode Register Low TMGMnL 7 6 5 4 3 2 1 0 Address ital value The explanation of the bit 7 to 0 is the same as the bit 7 to 0 of the TMGMn register 3 Timer Gn Mode Register High
250. DDAL2 R W x undefined FFFF F096 DMA destination address register 2H DDAH2 R W x undefined FFFF F098 DMA source address register 3L DSAL3 R W x undefined FFFF F09A DMA source address register 3H DSAH3 R W x undefined FFFF F09C DMA destination address register 3L DDAL3 R W x undefined FFFF FO9E DMA destination address register 3H DDAHS R W x undefined 76 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function Table 3 6 List of Peripheral I O Registers 2 7 Bit Units 22 Address Function Register Name for Manipulation he 1 bit 8 bit 16 bit FFFF FOCO DMA transfer count register 0 undefined FFFF FOC2 DMA transfer count register 1 undefined FFFF FOC4 DMA transfer count register 2 undefined FFFF F0C6 DMA transfer count register 3 undefined FFFF FODO DMA addressing control register 0 0000H FFFF FOD2 DMA addressing control register 1 0000H FFFF FOD4 DMA addressing control register 2 0000H FFFF FOD6 DMA addressing control register 3 0000H FFFF FOEO DMA channel control register 0 00H FFFF FOE2 DMA channel control register 1 00H FFFF FOE4 DMA channel control register 2 00H FFFF FOE6 DMA channel control register 3 00H FFFF FOFO DMA disable status register 00H FFFF FOF2 DMA restart register 00H FFFF F100 Interrupt Mask register 0 DRE FFFF F102 Interrupt Mask register 1 FFFFH
251. DL12 Undefined xxxxn192H CAN message ID register H12 M IDH12 Undefined xxxxn194H CAN message configuration register 12 M CONF12 Undefined xxxxn195H CAN message status register 12 M STAT12 Undefined xxxxn196H CAN status set cancel register 12 SC STAT12 0000H xxxxn1AOH CAN message event pointer 130 M EVT130 Undefined xxxxn1A1H CAN message event pointer 131 M EVT131 Undefined xxxxn1A2H CAN message event pointer 132 M EVT132 Undefined xxxxn1A3H CAN message event pointer 133 M EVT133 Undefined xxxxn1A4H CAN message data length register 13 M DLC13 Undefined xxxxn1A5H CAN message control register 13 M CTRL13 Undefined xxxxn1A6H CAN message time stamp register 13 M TIME13 Undefined xxxxn1A8H CAN message data register 130 M DATA130 Undefined xxxxn1A9H CAN message data register 131 M DATA181 Undefined xxxxn1 AAH CAN message data register 132 M DATA132 Undefined xxxxn1 ABH CAN message data register 133 M DATA133 Undefined xxxxn1ACH CAN message data register 134 M DATA134 Undefined xxxxn1 ADH CAN message data register 135 M DATA135 Undefined xxxxn1 AEH CAN message data register 136 M DATA136 Undefined xxxxn1 AFH CAN message data register 137 M DATA137 X XXIX XxX XxX XxX Xx Undefined xxxxn1BO
252. EE1VOUMOO 4 th Access 31 24 23 16 15 8 Address 7 7 4n 3 0 0 Word data External data bus 4 th Access 31 24 23 16 15 8 Address 7 7 4n 4 0 0 Word data External data bus 129 Chapter 4 Bus Control Function 3 Access to address 4n 2 1 st Access 31 24 23 16 15 8 Address 7 7 4n 2 0 0 Word data External data bus 2 nd Access 31 24 23 16 15 8 Address 7 7 4n 3 0 0 Word data External data bus lt 4 gt Access to address 4n 3 1 st Access 31 24 23 16 15 8 Address 7 7 M 4n 3 0 0 Word data External data bus 130 2 nd Access 31 24 23 16 15 8 Address 7 7 4n 4 0 0 Word data External data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 4 0 0 Word data External data bus 3 rd Access 31 24 23 16 15 8 Address 7 7 4n 5 0 0 Word data External data bus Preliminary User s Manual U15839EE1VOUMOO 4 th Access 31 24 23 16 15 8 Address 7A 7 4n 5 0 0 Word data External data bus 4 th Access 31 24 23 16 15 8 Address 7 7 4n 6 0 0 Word data External data bus Chapter 4 Bus Control Function 4 8 Wait Function 4 8 1 Programmable wait function 1 Data wait control registers 0 1 DWCO DWC1 With the purpose of realizing easy interfacing with low speed memory or with I Os it is possible to insert up to 7 data wait states with respect to the starting bus cycle for each CS area The number of wait states
253. External bus interface control signal input Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Preliminary User s Manual U15839EE1VOUMOO 547 Chapter 16 Port Functions 2 Functions of each port pin on reset and registers that set port or control mode Port Name Pin Name P10 CRXD1 Table 16 2 Port Pin Functions 1 3 Pin Function after Reset P10 Input mode P11 CTXD1 P11 Input mode P12 CRXD2 P13 CTXD2 P13 Input mode P14 CRXD3Nete P12 Input mode P14 Input mode P15 CTXD3Note P15 Input mode P16 RXD1 P16 Input mode P17 TXD1 P17 Input mode Mode Setting Register P20 SIO P20 Input mode P21 S00 P21 Input mode P22 SCKOO SCKIO P22 Input mode 23 511 P23 Input mode P24 SO1 P24 Input mode P25 SCKO1 SCKI1 P25 Input mode P26 RXDO P26 Input mode P27 TXDO P27 Input mode P30 TIGOO INTPOO P30 Input mode P31 TOGO01 TIGO1 P31 Input mode P32 TOG02 TIGO2 P32 Input mode P33 TOG03 TIGO3 P33 Input mode P34 TOG04 TIG04 P34 Input mode P35 TIGOS INTPO5 P35 Input mode P40 TIG10 INTP10 P40 Input mode P41 TOG11 TIG11 P41 Input mode P42 TOG12 TIG12 P42 Input mode P43 TOG13 TIG13 P43 Input mode P44 TOG14 TIG14 P44 Input mode P45 TIG15
254. FCAN Interface Function Table 14 14 Inner Storage Priority Within a Priority Class Priority First Criteria Priority Second Criteria 1 high lowest physical message buffer number DN flag not set 2 low next physical message buffer number 1 high lowest physical message buffer number DN flag set 2 low next physical message buffer number Example When the very first message is received which fits into several message buffer of the same prior ity class the DN flag in all buffers is not set hence that message is stored in the buffer with the lowest physical buffer number Subsequent messages are stored to the message buffers in ascending message buffer number order as long the DN flags remains as set into the buffer of the previous message storage As soon the CPU reads one of the message buffer with DN flag set and then clears the DN flag the storing in ascending message buffer number order is interrupted Due to the storage priority for receive messages it is possible to design multiple buffer arrays for a CAN message while not all message buffers assigned to the same identifier contain new data DN flag set the FCAN system will store the data in the next free message buffer DN flag cleared Preliminary User s Manual U15839EE1VOUMOO 447 Chapter 14 FCAN Interface Function 14 2 7 Mask handling The FCAN system supports two concepts of message reception the BasicCAN concept and the Full CAN
255. Format 1 data frame DGGE V a v Character bits Start bit 1 bit e Character bits 7 bits or 8 bits Parity bit Even parity odd parity 0 parity or no parity Stop bits 1 bit or 2 bits Preliminary User s Manual U15839EE1VOUMOO 375 2 Chapter 13 Serial Interface Function Transmit operation When Power bit is set to 1 in the ASIMn register a high level is output from the TXD5n pin Then when TXE bit is set to 1 in the ASIMn register transmission is enabled and the transmit operation is started by writing transmit data to transmission buffer register TXBn n 0 1 a Transmission enabled state This state is set by the TXE bit in the ASIMn register 1 Transmission enabled state 0 Transmission disabled state Since UART5n does not have a CTS transmission enabled signal input pin a port should be used to confirm whether the destination is in a reception enabled state b Starting a transmit operation In transmission enabled state a transmit operation is started by writing transmit data to transmission buffer register TXBn When a transmit operation is started the data in TXBn is transferred to transmission shift register Then the transmission shift register outputs data to the TXD5n pin the transmit data is transferred sequential starting with the start bit The start bit parity bit and stop bits are added automatically c Tran
256. Function Register Name CAN message event pointer 020 M_EVT020 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn041H CAN message event pointer 021 M_EVT021 Undefined xxxxn042H CAN message event pointer 022 M EVTO22 Undefined xxxxn043H CAN message event pointer 023 M_EVT023 Undefined xxxxn044H CAN message data length register 02 M_DLC02 Undefined xxxxn045H CAN message control register 02 M_CTRL02 Undefined xxxxn046H CAN message time stamp register 02 M TIMEO2 Undefined xxxxn048H CAN message data register 020 M DATAO20 Undefined Xxxxn049H CAN message data register 021 M_DATA021 Undefined xxxxn04AH CAN message data register 022 M_DATA022 Undefined Xxxxn04BH CAN message data register 023 M DATAO23 Undefined xxxxn04CH CAN message data register 024 M DATAO24 Undefined xxxxn04DH CAN message data register 025 M DATAO25 Undefined xxxxnO4EH CAN message data register 026 M DATAO26 Undefined xxxxnO4FH CAN message data register 027 M DATAO27 X XxXxX XxX Xx Undefined xxxxn050H CAN message ID register L02 M IDLO2 Undefined xxxxn052H CAN message ID register H02 M IDHO2 Undefined xxxxn054H CAN message configuration register 02 M CONFO2 Undefined xxxxn055H CAN mess
257. G11 output Timer G 1 compare output 2 P42 TIG12 output Timer G 1 compare output 3 P43 TIG13 output Timer G 1 compare output 4 P44 TIG14 input Timer C 0 capture input 0 P54 INTP20 input Timer C 0 capture input 1 P55 INTP21 output Timer CO compare output P56 Data bus of external bus output Address bus of external bus PAHO PAH7 output Write strobe signal for lower byte bit O bit 7 PCTO output Write strobe signal for upper byte bit O bit 7 PCT1 output Read strobe signal for external bus PCT4 input Control signal input for external bus PCMO output 38 Chip select output for external bus PCSO All Vpps pins have to be connected to each other On each pin of Vpp3 a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin On CVpp a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin and CVy must be connected to each other CAN module and CAN module 4 are available in the derivatives uPD703129 A and pgPD703129 A1 only Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions 3 Pin status in RESET and STANDBY mode Table 2 3 Pin Status in Reset and Standby Mode Operating Status Idle state 1 DO to 015 operate operate to A23
258. H CAN message ID register L13 M IDL13 Undefined xxxxn1B2H CAN message ID register H13 M IDH13 Undefined xxxxn1B4H CAN message configuration register 13 M CONF13 Undefined xxxxn1B5H CAN message status register 13 M STAT13 Undefined xxxxn1B6H CAN status set cancel register 13 SC STAT13 0000H xxxxn1COH CAN message event pointer 140 M EVT140 Undefined xxxxn1C1H CAN message event pointer 141 M EVT141 Undefined xxxxn1C2H CAN message event pointer 142 M EVT142 Undefined xxxxn1C3H CAN message event pointer 143 M EVT143 Undefined xxxxn1C4H CAN message data length register 14 M DLC14 Undefined xxxxn1C5H CAN message control register 14 M CTRL14 Undefined xxxxn1C6H CAN message time stamp register 14 M TIME14 Undefined xxxxn1C8H CAN message data register 140 M DATA140 Undefined xxxxn1C9H CAN message data register 141 M DATA141 Undefined xxxxn1CAH CAN message data register 142 M DATA142 Undefined xxxxn1CBH CAN message data register 143 M DATA143 Undefined xxxxn1CCH CAN message data register 144 Preliminary User s Manual U15839EE1VOUMOO M DATA144 Undefined 91 xxxxn1CDH Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 8 18 Function Register Name CAN message data register
259. H3 These registers can be read written in 16 bit units Caution When setting an address of a peripheral I O register for the source address be sure to specify an address between FFFF000H and FFFFFFFH An address of the periph eral I O register image 3FFF000H to 3FFFFFFH must not be specified Figure 7 1 DMA Source Address Registers DSAH0 to DSAH3 DSAHO0 to DSAHS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSAHO FFFFF082H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSAH1 FFFFF08AH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSAH2 FFFFF092H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSAH3 FFFFF09AH undef Bit Position Function Specifies the DMA source address 0 External memory or On chip peripheral I O 1 Internal RAM SA2710 Sets the DMA source addresses 27 to A16 During DMA transfer it stores the next SA16 DMA transfer source address 170 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 2 DMA source address registers LO to L3 DSALO to DSAL3 These registers can be read written in 16 bit units Figure 7 2 DMA Source Address Registers DSALO to DSAL3 DSALO to DSAL3 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSALO FFFFF080H undef 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DSAL1 FFFFF088H undef 15 1
260. INT6 bit is set 1 Others No change in E INT6 bit value Sets clears the E_INT5 bit ST E INT5 CL E INT5 Status of E INT5 bit 0 1 1 E INT5 bit is cleared 0 0 E INT5 bit is set 1 Others No change in E INT5 bit value Sets clears the E_INT4 bit CL E INT4 Status of E INTA bit 1 E INTA4 bit is cleared 0 0 E_INT4 bit is set 1 Others No change in E_INT4 bit value Sets clears the E INT3 bit ST E INTS CL E INT3 Status of E INT3 bit 0 1 E INT3 bit is cleared 0 1 0 E INT bit is set 1 Others No change in E INT3 bit value ST E INT3 CL E INT3 Sets clears the E_INT2 bit CL_E_INT2 Status of E_INT2 bit 1 E_INT2 bit is cleared 0 0 E_INT2 bit is set 1 Others No change in E_INT2 bit value Sets clears the E_INT1 bit ST_E_INT1 CL_E_INT1 Status of E_INT1 bit 0 1 E_INT1 bit is cleared 0 1 0 E INT1 bit is set 1 Others No change in E_INT1 bit value ST_E_INT1 CL_E_INT1 ST E INTO Sets clears the E INTO bit CL E INTO ST E INTO CL E INTO Status of E INTO bit 1 E INTO bit is cleared 0 0 E INTO bit is set 1 Others No change in E INTO bit value 500 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 7 CAN 104 bus activity registers C1BA to The CxBA registers indicate the status of the CAN bus activities of the corresponding CAN
261. ISRM bit of the ASIMn register When reception is disabled no reception error interrupt is generated Reception completion interrupt INTSRO INTSR1 When reception is enabled a reception completion interrupt is generated when data is shifted in to the reception shift register and transferred to the reception buffer register RXBn A reception completion interrupt request can be generated in place of a reception error interrupt according to the ISRM bit of the ASIMn register even when a reception error has occurred When reception is disabled no reception completion interrupt is generated Transmission completion interrupt INTSTO INTST1 A transmission completion interrupt is generated when one frame of transmit data containing 7 bit or 8 bit characters is shifted out from the transmission shift register Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 2 5 Operation 1 Data format Full duplex serial data transmission and reception can be performed The transmit receive data format consists of one data frame containing a start bit character bits a parity bit and stop bits as shown in Figure 13 7 The character bit length within one data frame the type of parity and the stop bit length are specified according to the asynchronous serial interface mode register ASIMn n 0 1 Also data is transferred with LSB first Figure 13 7 Asynchronous Serial Interface Transmit Receive Data
262. M This is an 8 bit register that control the power save mode and sub oscillator control This register can be read or written in 8 bit or 1 bit units Figure 9 16 Power Save Mode Register PSM 7 6 5 4 3 2 1 0 Address e Function Bit name Calibration mode control bit CMODE 0 Calibration timer clock is fpc 1 Calibration timer clock is output from Main oscillator clock input Main clock oscillator enable control bit 1 Main oscillator remains stopped after sub Watch mode release The CPU will start from sub clock 0 Main oscillator will be enabled after sub Watch mode release and used for CPU clock gener ation after the oscillation stabilization counter expires If this bit is cleared after sub Watch mode release the main oscillator will start After the oscilla tion stabilization time expires the main oscillator can be used as system clock source by setting the PCC register accordingly OSCDIS Standby mode specification bits PSM1 PSMO Standby Mode IDLE STOP PSM1 PSMO WATCH Sub oscillator WATCH mode Main oscillator shut down This mode can only be enabled if SUBEN is 1 Otherwise normal WATCH mode is forced 270 Preliminary User s Manual U15839EE1VOUMO00 Chapter 10 Timer 10 1 Timer C 10 1 1 Features Timer C One channel of Timer C is implemented Timer C TMCO is a 16 bit timer counter that can perform the following operations 2cap
263. MA Functions DMA Controller 7 11 Forcible Termination In addition to the forcible interruption operation by means of the NMI input DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register The following is an example of the operation of a for cible termination Figure 7 28 Transfer Forcible Termination Example 1 on page 196 shows a block transfer of channel 3 which begins during the DMA block transfer of DMA channel 2 The block transfer of DMA channel 2 is forcibly terminated by setting the INIT2 bit of its DCHC2 control register Figure 7 28 DMA Transfer Forcible Termination Example 1 DSAL2 DSAH2 DCHC2 DDAL2 DDAH2 INIT2 bit 1 Set register Set register DMA Transfer Request CH2 EN2 bit 1 EN bit 0 TC2 bit 0 TC2 bit 0 DSAL3 DSAHS DDAL3 DDAH3 Set register DMA Transfer Request CH3 ENS bit 1 ENS bit gt 0 TC3 bit 0 TC3 bit gt 1 DMA channel 3 terminal count DMA channel 3 transfer begins DMA channel 2 transfer is forcibly terminated and the bus is released Remarks 1 The next condition can be set even during DMA transfer because the DSAn DDAn and DBCn registers are buffered registers However the setting to the DADCn register is invalid refer to 7 3 Next Address Setting Function and 7 2 4 DMA addressing control registers 0 to DADCO to DADC3 2 nz 0103 196 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 Functions Controll
264. MOO Chapter 10 Timer 5 Timer Gn Channel Mode Register Low TMGCMnL This register is the low byte of the TMGCMn register This register can be read written in 8 bit or 1 bit units Figure 10 34 Timer Gn Channel Mode Register TMGCMnL 7 6 5 4 3 2 1 0 Address itial value The explanation of the bit 7 to 0 is the same as the bit 7 to 0 of the TMGCMnH register 6 Timer Gn Channel Mode Register Low TMGCMnH This register is the high byte of the TMGCMnH register This register can be read written in 8 bit or 1 bit units Figure 10 35 Timer Gn Channel Mode Register TMGCMnH 7 6 5 4 3 2 1 0 Address 18 value The explanation of the bit 7 to 0 is the same as the bit 15 to 8 of the TMGCMnH register Preliminary User s Manual U15839EE1VOUMOO 317 Chapter 10 Timer 7 Timer Gn output control register OCTLGn This register controls the timer output from the TOGm pin m 1 to 4 and the capture or compare modus for the GCCnm register This register can be read written in 16 bit 8 bit or 1 bit units Cautions 1 When the POWER bit is set the rewriting of CCSGm is prohibited 2 When the POWER bit and TMGOE bit TMG1E bit are set at the same time the rewriting of the ALVGm bits is prohibited Figure 10 36 Timer Gn Output Control Register OCTLGn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Address a value EWES ICO v pwespuspese v presos v purs pergo FE enm en SWF Neo pwespuspese v v pure
265. MOO 385 Chapter 13 Serial Interface Function b Baud rate generator control registers BRGCO BRGC1 The BRGOCm register is an 8 bit register that controls the baud rate serial transfer speed of UART5n This register can be read or written in 8 bit or 1 bit units m 0 1 Figure 13 18 Baud Rate Generator Control Registers BRGCO BRGC1 Initial value 7 6 5 4 3 2 1 0 Address Divisor Value Serial Clock Setting prohibited foLk 8 fcuk 9 fcuk 10 MDL7 to MDLO 1 250 251 fo 252 fo 253 254 fo 255 Caution If the MDL7 to MDLO bits be overwritten bit and RXE bit should be set to 0 in the ASIMn register first Remarks 1 Frequency Hz of basic clock selected according to TPS3 to TPSO bits of CKSRm register 2 k Value set according to MDL7 to MDLO bits k 8 9 10 255 The baud rate is the output clock for the 8 bit counter divided by 2 gt x don t care 386 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function c Baud rate The baud rate is the value obtained according to the following formula fcLk Baud rate b aud rate 2 k bps folk Frequency Hz of basic clock selected according to TPS3 to 50 bits of CKSRm register k Value set according to MDL7 to MDLO bits of BRGCm register 8 9 10 255 d Bau
266. M_EVT262 Undefined Xxxxn263H CAN message event pointer 263 M_EVT263 Undefined Xxxxn264H CAN message data length register 19 M DLC19 Undefined Xxxxn265H CAN message control register 19 M_CTRL19 Undefined Xxxxn266H CAN message time stamp register 19 M_TIME19 Undefined Xxxxn268H CAN message data register 190 M_DATA190 Undefined Xxxxn269H CAN message data register 191 M DATA191 Undefined XXxxn26AH CAN message data register 192 M DATA192 Undefined xxxxn26BH CAN message data register 193 M DATA193 Undefined xxxxn26CH CAN message data register 194 M DATA194 Undefined xxxxn26DH CAN message data register 195 M DATA195 Undefined xxxxn26EH CAN message data register 196 M DATA196 Undefined xxxxn26FH CAN message data register 197 M DATA197 Undefined xxxxn270H CAN message ID register L19 M IDL19 Undefined xxxxn272H CAN message ID register H19 M IDH19 Undefined xxxxn274H CAN message configuration register 19 M CONF19 Undefined xxxxn275H CAN message status register 19 M STAT19 Undefined xxxxn276H CAN status set cancel register 19 SC STAT19 0000H Xxxxn280H CAN message event pointer 200 M EVT200 Undefined xxxxn281H CAN message event pointer 201 M EVT201 Undefined Xxxxn282H
267. Madrid Spain 091 504 27 87 Fax 091 504 28 60 Succursale Frangaise V lizy Villacoublay France 01 30 67 58 00 Fax 01 30 67 58 99 Filiale Italiana Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 Branch The Netherlands Eindhoven The Netherlands Tel 040 244 58 45 Fax 040 244 45 80 Branch Sweden Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 United Kingdom Branch Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd Singapore 65 6253 8311 Fax 65 6250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos Brasil Tel 55 11 6465 6810 Fax 55 11 6465 6829 Preliminary User s Manual U15839EE1VOUMOO Readers Purpose Organization Legend Preliminary Users Manual U15839EE1VOUMOO Preface This manual is intended for users who want to understand the functions of the V850E CA2 nickname Jupiter This manual presents the hardware manual of V850E CA2 This system specification describes the following sections e Pin function CPU function Internal peripheral function Symbols and notation are used as follows Weight in data notation Left is high order co
268. NB85E 156 Preliminary User s Manual U15839EE1VOUMOO Chapter6 Instruction Cache 6 2 1 Four Kbytes 2 way set associative Instruction Cache The data memory of a 4 KBytes 2 way set associative instruction cache has two ways each consisting of a block of 128 entries of 4 words per line for a total capacity of 4 KB Figure 6 2 Configuration of 4 KB 2 Way Set Associative Instruction Cache 25 11 10 43210 Data part 4 words tries A Internal bus Comparator Way selection control signal on hit WHIT Instruction data Preliminary Users Manual U15839EE1VOUMOO 157 Chapter 6 Instruction Cache 6 3 Control Registers 1 Instruction Cache Control Register ICC The ICC register is the register that sets two types of functions tag clear and autofill The ICC reg ister can be read or written in 16 bit 8 bit or 1 bit units Figure 6 3 Instruction Cache Control Register ICC 15 14 18 12 d 10 9 8 7 6 8 4 8 2 1 0 Address EA value e TT ERR TS T3 T2 T9 T Pp on This bit shows the cache lock status of way 0 When way O is filled the cache is locked and this bit is set 1 automatically Clearing 0 this bit releases the cache lock of way 0 0 Way 0 is not locked 1 Way 0 is locked This bit sets way 0 autofill Setting 1 this bit autofills way
269. O Count Direction Increment Decrement Fixed Setting prohibited Preliminary User s Manual U15839EE1VOUMOO 175 Chapter 7 DMA Functions DMA Controller Figure 7 6 DMA Addressing Control Registers 0 to 3 DADCO to DADC3 2 2 Bit Position Bit Name Function Sets the count direction of the destination address for DMA channel n n 0 to 3 Count Direction Increment Decrement Fixed Setting prohibited TM1 TMO Transfer Mode Single transfer mode Single step transfer mode Line transfer mode Block transfer mode Caution These registers cannot be accessed during DMA operation Remark nz0to3 176 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 2 5 DMA channel control registers 0 to 3 DCHCO to DCHC3 These 8 bit registers are used to control the DMA transfer operating mode for DMA channel n These registers can be read written in 8 bit or 1 bit units However bit 7 is read only and bits 2 and 1 are write only If bits 2 and 1 are read the read value is always O Figure 7 7 DMA Channel Control Registers 0 to DCHCO0 to DCHC3 7 6 5 4 3 2 1 0 Address Initial value 7 6 5 4 3 2 1 0 Address Initial value 7 6 5 4 3 2 1 0 Address Initial value 7 6 5 4 3 2 1 0 Address Initial value Bit Position Bit Name Function This status bit indicates whether DMA transfer through DMA channel n has ended or
270. O Chapter 15 A D Converter a Conversion time setting In order to prevent a drastic change of A D conversion time even when the oscillation frequency is changed the conversion speed of an A D conversion can be adjusted By the selection bits FR3 to FRO in the ADM register the number of the conversion clocks can be set in the range of 84 to 216 However the settings modifying the conversion time Tcony must keep the following relation Example Provided that fPcLK 16 MHz A setting of bits FR3 to FRO 0101B will be chosen The conversion time is es NR T conv Conversion Clocks FR3 to FRO FF NTP By this the conversion time results in Tooma 5 25 Preliminary User s Manual U15839EE1VOUMOO 529 Chapter 15 A D Converter 2 converter register ADS The ADS register is an 8 bit register that selects the analog input channel for the A D conversion It can be read or written in 1 bit or 8 bit units Writing to the ADS register during A D conversion operation interrupts the conversion operation and the data is lost The conversion operation restarts from the beginning Figure 15 3 A D Converter Register ADS 7 6 5 4 3 2 1 0 Address Initial value The bits ADS3 to ADSO specify the analog input channel for which the A D conversion is performed Analog input channel AINO AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 0 1 AIN11 Others than above Setting prohibited
271. O 00H FFFF FD02 Reception data buffer register FFFF FD04 Transmission data buffer register FFFF 008 First transmission data buffer register FFFF FDOA Shift register FFFF FD40 CSI operation mode register CSIM1 00H FFFF FD41 Clock selection register CSIC1 00H SIRB1 0000H SIRBL1 00H SOTB1 0000H SOTBL1 00H SOTBF1 0000H SOTBFL1 00H SIO1 0000H SIOL1 00H FFFF FD42 Reception data buffer register FFFF FD44 Transmission data buffer register FFFF FD48 First transmission data buffer register FFFF FD4A Shift register FFFF FD80 CSI operation mode register CSIM2 FFFF FD81 Clock selection register CSIC2 SIRB2 0000H SIRBL2 00H SOTB2 0000H SOTBL2 00H SOTBF2 0000H SOTBFL2 00H SIO2 0000H SIOL2 00H FFFF FDCO BRGO Prescaler mode register PRSMO 00H FFFF FDC1 BRGO Prescaler compare register PRSCMO 00H FFFF FDEO BRG1 Prescaler mode register PRSM1 00H FFFF FDE1 BRG1 Prescaler compare register PRSCM1 00H FFFF FD82 Reception data buffer register FFFF FD84 Transmission data buffer register FFFF FD88 First transmission data buffer register FFFF FD8A Shift register 82 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 5 4 Programmable peripheral I O registers In the V850E CA2 the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I O area In this area the
272. OOH is set in GCCn0 or 5 the value of the counter is fixed at OOOOH and does not operate Moreover or INTCCGn5 continues to be active c When FFFFH is set in GCCn0 or GCCn5 match and clear When FFFFH is set in GCCn0 or GCCn5 operation equivalent to the free run mode is performed When an overflow occurs INTTMGnO or INTTMGn1 is generated but INTCCGnO or INTCCGn5 is not generated d When 0000H is set in GCCnm m 1 to 4 match and clear INTCCGnm is activated when the value of the counter becomes 0001H Note however that even if no data is set in GCCnm INTCCGnm is activated immediately after the counter starts e When a value exceeding the value of GCCn0 or GCCn5 is set in GCCnm m 1 to 4 match and clear INTCCGnm is not generated 338 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer f When GCCnm m 1 to 4 is rewritten during operation match and clear When the value of GCCn1 is changed from 0555H to OAAAH the operation described below is performed TMGn0 is selected as the counter and OFFFH is set in GCCn0 Figure 10 52 Timing when GCCnm is rewritten during operation match and clear TMGnO GCOCn1 Slave register GCCn1 Master register INTCCGn1 Caution To perform successive write access during operation for rewriting the GCCny register n 1 to 4 you have to wait for minimum 7 peripheral clocks periods fpc
273. OP mode current consumption When this mode is released the oscillation stabilization time for the oscillator should be secured until the system clock is stabilized However when the external clock operates this product securing the oscillation stabilization time for the oscillator until the system clock is stabilized is unnecessary In the direct mode as well the lock up time does not have to be secured This mode is entered by setting the PSM amp PSC register In this mode the program execution stops but the contents of all registers and internal RAM prior to entering this mode are retained V850E CA2 peripherals operations are also stopped except Sub oscillator and Watchdog timer in case of SOSTP bit 1 The state of the various hardware units in the software STOP mode is tabulated below Table 9 11 Operating States in STOP Mode Items Operation Clock generator Stopped Sub OSC operates if SOSTP bit 1 SSCG PLL Stopped Internal system clock Stopped WT clock Stopped WDT clock Stopped if SOSTP bit 0 CPU Stopped I O lineNote Unchanged Peripheral function Stopped datgNote Retains all previous internal data such as CPU registers status nternal data data and on chip RAM D 15 0 A 23 0 Hi Z RD WR1 WRO CSO CS 42 H CLKOUT L WAIT Input value is not sampled Note When the Vpp value is within the operating range However even if Vpp falls bel
274. OUMOO Chapter 16 Port Functions 2 Setting in input output mode and control mode Port 4 is set in input output mode using the port 4 mode register PM4 In control mode it is set using the port 4 mode control register PMC4 a Port 4 mode register PM4 This register can be read or written in 8 bit or 1 bit units Figure 16 17 Port 4 Mode Register PM4 0 Address At Reset 7 6 5 4 3 2 1 PM4n Specifies input output mode of P4n pin 7100 n 7 to 0 0 Output mode Output buffer on E 1 Input mode Output buffer off b Port 4 mode control register PMC4 This register can be read or written in 8 bit or 1 bit units Figure 16 18 Port 4 Mode Control Register PMC4 7 3 2 1 0 Address At Reset 6 5 4 Bit Position Bit Name Function Specifies operation mode of P45 pin 0 Input output port mode 1 TIG15 input mode or external interrupt request INTP15 input mode Specifies operation mode of P44 pin 0 Input output port mode 1 TIG14 TOG14 input output mode Specifies operation mode of P43 pin 0 Input output port mode 1 TIG13 TOG13 input output mode Specifies operation mode of P42 pin 0 Input output port mode 1 TIG12 TOG12 input output mode Specifies operation mode of P41 pin 0 Input output port mode 1 TIG11 TOG11 input output mode Specifies operation mode of P40 pin 0 Input output port mode 1 TIG10 input mode or external interrupt request INTP10 input mode
275. P register returns the status of the CxDINF register Defines the single shot mode for a CAN module 0 Normal operating mode 1 Single shot mode Remarks 1 In single shot mode the CAN module tries to transmit a message only once and the TRQ flag of the corresponding message is cleared regardless whether the transmission was successful no error occurred or not In case of an error frame caused during a transmission in single shot mode the CAN module does not launch a re transmission However error management according to the CAN Protocol is executed i e gen eration of error interrupt incrementing of error counters The CPU can switch between the normal operating mode and the sin gle shot mode while the CAN module is active without causing any error on the CAN bus Caution According to the CAN protocol upon a loss of arbitration a transmit ter attempts to re transmit the message though loss of arbitration is not defined as an error When single shot mode is set SSHT 1 a loss of arbitration is sig naled by setting the BERR flag 1 Since the BERR flag signals a bus error in normal operation the user must check it in conjunction with the values of the error counter in order to judge whether it was caused by an error or a loss of arbitration Preliminary User s Manual U15839EE1VOUMOO 493 Chapter 14 FCAN Interface Function Figure 14 35 CAN 1 to 4 Definition Registers C1DEF to CADEF 3 4 Read 2 2 Define
276. PU registers status data and on chip RAM CLKOUT pin Clock output when not inhibited by port setting D 15 0 23 0 RD WRT operates WPO CS 0 CS 3 4 WAIT p Internal data Remark Even after the HALT instruction is executed instruction fetch operations continue until the internal instruction pre fetch queue is full After the queue becomes full the CPU stops with the items set as tabulated above HALT mode release The HALT mode can be released by a non maskable interrupt request an unmasked maskable inter rupt request or RESET signal input 1 Release by interrupt request The HALT mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level However if the HALT mode is entered during execution of an interrupt handler the operation differs on interrupt priority levels as follows a If an interrupt request less prioritized than the currently serviced interrupt request is gener ated the HALT mode is released but the interrupt is not acknowledged The interrupt request itself is retained b If an interrupt request including a non maskable one prioritized than the currently serviced interrupt request is generated the interrupt request is acknowledged along with the HALT mode release 256 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator Table 9 5 Operation after HALT mode release by interrupt request NMI request Branches
277. RCMD 104 3 6 2 Peripheral Command Register 105 3 6 8 Peripheral Status Register 5 106 3 6 4 Internal peripheral function wait control register 107 Chapter 4 Bus Control Function 0002 c cece eee ee eee eee 109 FO ATU OS gt ORAE Bieta arene eaten 109 42 Bus Control Pins oe e rr ee Rer eee 109 4 3 Memory Block 110 4 3 1 Chip Select Control Function 111 4 4 Programmable peripheral I O 113 45 Bus Cycle Type Control Function 0 200 e eee eee 115 4 5 1 Bus cycle type 115 4 6 BUS ACCeSS ce Se esa a ag eren 116 4 6 1 Number of access clocks eee 116 4 6 2 BUS SIZINGTUNCHON ict eset ed cee heed cee we ee ee be eee Paes 116 4 6 3 Endian control function 0 0 0 0 eee ee 117 4 7 Cache 118 4 71 gt Bus width coeurs ege e deed as hem pete pe Ou es ets 119 4 8 WaitF ncllon ee te ES ate 131 4 8 1 Pro
278. SR register Notes 1 The register address is calculated according to the following formula effective address PP BASE address offset 2 Ifa message search finds several message buffers meeting the search option the MM flag is set In that case the MFND5 to MFNDO bits return number of the message buffer with the lowest number 3 Value of Bits 6 and 7 is undefined after search function Preliminary User s Manual U15839EE1VOUMOO 465 Chapter 14 FCAN Interface Function 9 CAN test bus register CTBR For test purposes an internal test bus is available The CTBR register controls this test bus capa bility This register can be read and written in 8 bit and 16 bit units Figure 14 19 CAN Test Bus Register CTBR Address Initial 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OffsetNote value oer oo Beppe ow Enables the receive line 0 CAN module receive lines are input from the corresponding CANxRX pins 1 CAN module receive lines are input from to the internal test bus Presets the transmit lines 0 No preset on the transmit lines 1 Error injection into the internal test bus by forcing all transmit pins to a dominant level Enables internal test bus 0 Internal test bus is disabled 1 Internal test bus is enabled The figure below shows the structure of the internal CAN test bus Figure 14 20 Internal CAN Test Bus Structure TXPRE OJ CTXD1 Internal Test Bus CTXD2 CT
279. ST C4ERC CAN4 information register read only CAN4 error counter register read only CAIE CANA interrupt enable register bit set clear function C4BA CAN4 bus activity register bit set clear function J 2 2 D D 20 2 CABRP CANA bit rate prescaler register in initialisation state only ISTAT bit 1 bus diagnostic in diagnostic mode information register only z C4DINF D CAN4 synchronization control C4SYNC i register Notes 1 CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only 2 The address of an interrupt pending register is calculated according to the following for mula effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO 437 Chapter 14 FCAN Interface Function 14 2 3 Clock structure All functional blocks within the FCAN system are supplied by a unique clock fmem derived from the internal system clock fp Figure 14 3 Clock Structure of the FCAN System General Time System Time System Prescaler Prescaler Counter CAN 1 Baudrate f cat Generator CAN 2 Baudrate Generator fcAN2 CAN 3 Note Baudrate Generator CAN 4 Note Baudrate Generator fcan4 Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only A functional block for a
280. Selec tion Register WDCS on page 359 Watchdog Timer Mode 2 RESET Set WDTMA bit and WDTMS bit of the watchdog timer mode register WDTM to 1 to operate as a watchdog timer RESE T request mode to detect program runaway Setting RUN bit of WDTM to 1 starts the count After counting starts if RUN bit is set to 1 again within the set time interval for runaway detection the watchdog timer is cleared and counting starts again If RUN bit is not set to 1 and the runaway detection time has elapsed a RESET functions is gen erated The watchdog timer stops running in the STOP mode Consequently set RUN to 1 and clear the watchdog timer before entering the STOP mode Do not set the watchdog timer when operating the HALT mode since the watchdog timer running in HALT mode For details of the possible time settings please refer to Figure 12 2 Watchdog Timer Clock Selec tion Register WDCS on page 359 Caution The actual runaway detection time may be up to 2 2 fxx seconds less than the set 362 time Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 1 Features The serial interface function provides three types of serial interfaces combining a total of 9 transmit receive channels All channels can be used simultaneously The three interface formats are as follows Asynchronous serial interfaces UART50 UART51 2 channels Clocked serial interface
281. Selects active edge for interrupt generation Edge selection Falling edge Rising edge Reserved Both edges Edge selection for INTP20 to interrupt controller Edge selection 0 0 Falling edge 1 0 Reserved Edge selection for INTP15 to interrupt controller Edge selection Falling edge Rising edge Reserved Both edges 10 to interrupt controller Edge selection Falling edge Rising edge Reserved Both edges Note Programming edge detection or port mode register can trigger unintended interrupt requests Therefore be sure to mask the respective interrupt requests Preliminary User s Manual U15839EE1VOUMOO 225 Chapter 8 Interrupt Exception Processing Function 4 Interrupt mode register 3 INTM3 Figure 8 20 Interrupt Mode Register 3 IMTMS 7 6 5 4 3 2 1 0 Address value INTM3 ESNO FFFFF886H 00H Edge selection for NMI Selects active edge for interrupt generation ESNO S 0 Falling edge 1 Rising edge Notes 1 NMI functionality is masked by PMC6O Selection of valid edge for NMI must be performed while PMC60 is 0 2 Install appropriate interrupt handler for NMI before reprogramming edge detection or port function 226 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function 8 5 Software Exception A software exception is generated when the CPU executes the TRAP instruction and can be
282. Switching to an unstable clock source is not protected by hardware SSCG frequency dithering enable bit 0 SSCG uses fixed multiplication factor of SCFC1 DEN 1 SSCG uses multiplication factor of SCFCO and SCFC1 alternately Caution The DEN bit can be toggled only in case that the SCEN bit is 0 SSCG disabled Peripheral clock source select bit PERIC 0 Main oscillator x1 is clock source for peripherals 1 PLL x4 is clock source for peripherals Preliminary User s Manual U15839EE1VOUMOO 241 Chapter 9 Clock Generator Figure 9 2 Clock Control Register 2 2 Bit name Function Sub clock source select bit WTSEL1 0 Main oscillator 128 is clock source for sub clock 1 Sub oscillator is clock source for sub clock Sub clock divider select for fokseL2 WTSELO 0 fcksgr o sub clock 4 1 cksEL2 sub clock 32 Cautions 1 Data is set to the CKC register by the following sequence Write the set data to the command register PHCMD see Chapter 3 6 2 Peripheral Command Register PHCMD on page 105 Write the set data to the destination register 2 If PLL or SSCG operation is required the PLLEN bit and the SCEN bit are allowed to be set 1 when the system remains in the main oscillation mode CPU and peripherals are using the main oscillator as the clock supply To write data to the CKC register use the store instruction ST SST and bit manipulation instruction SET1 CLR1 NOT
283. T WDT clock Operating CPU Stopped I O line Unchanged Peripheral function Stops exclude Watch timer Watchdog timer calibration input Main Clock available Internal data Retains all internal data before entering IDLE mode such as CPU registers status data and on chip RAM D 15 0 A 23 0 Hi Z RD WR1 WRO CS 0 CS 4 2 H CLKOUT L WAIT IDLE mode release Input value is not sampled Release operation is same as release from HALT mode The IDLE mode is released by NMI RESET signal input or an unmasked maskable interrupt request a Release by Interrupt input When the IDLE mode is released the NMI request is acknowledged If the IDLE mode is entered during the execution of NMI handler the IDLE mode is released but the interrupt is not acknowledged The interrupt itself is retained b Release by RESET input This operation is the same as normal reset operation 258 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 4 6 WATCH mode In this mode fcpy clock is stopped while the oscillator continue to operate to achieve low power though only oscillator amp Watch timer Watchdog timer continue to operate This mode compensates the HALT modes concerning the oscillator stabilization time and power con sumption As it is not necessary to secure the oscillation stabilization time it is possible immediately t
284. T1 f RXD1 Receive data Input This pin input serial receive data of UART1 Note CAN module is available in the derivatives PD703129 A and PD703129 A1 only 40 Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions 2 P20 to P27 Port 2 Input output Port 2 is an 8 bit input output port in which input or output can be set in 1 bit units Besides functioning as an input output port in control mode P20 to P27 operate as the serial interface UARTO CSIO CS1 input output An operation mode of port or control mode can be selected for each bit and specified by the port 2 mode control register PMC2 a Port mode P20 to P27 can be set to input or output in 1 bit units using the port 2 mode register PM2 b Control mode P20 to P27 can be set to port or control mode in 1 bit units using PMC2 c SOO SO1 Serial output Output These pins output CSIO and CSI1 serial transmit data d SIO SI1 Serial input Input These pins input CSIO and CSI1 serial receive data e SCKO SCK1 Serial clock Input output These are CSIO and CSI1 serial clock input output pins f TXDO Transmit data Output This pin output serial transmit data of UARTO g RXDO Receive data Input This pin input serial receive data of UARTO Preliminary User s Manual U15839EE1VOUMOO 41 3 42 Chapter 2 Pin Functions P30 to P35 Port 3 Input output Port 3 is a 6 bit input output
285. TMGMnH n 0 1 This register is the high byte of the TMGMn register This register can be read written in 8 bit or 1 bit units Figure 10 32 Timer Gn Mode Register Low TMGMnH 7 6 5 4 3 2 1 0 Address ital value The explanation of the bit 7 to 0 is the same as the bit 15 to 8 of the TMGMn register Preliminary User s Manual U15839EE1VOUMOO 315 Chapter 10 Timer 4 Timer Gn Channel Mode Register TMGCMn This register specifies the assigned counter TMGnO or TMGn1 for the GCCnm register Furthermore it specifies the edge detection for the TIGy input pins y 0 to 5 This register can be read written in 16 bit 8 bit or 1 bit units Figure 10 33 Timer Gn Channel Mode Register TMGCMn i5 14 13 12 11 10 9 8 7 5 4 3 2 1 0 Address a value Bit Position Bit Name Function Assigns Capture Compare registers GCCn1 to GCCn4 to one of the 2 counters TMGn0 or TMGn1 0 Set TMGn0 as the corresponding counter to GCCnm register and TIGm 15 to 12 TOGnm pin 1 Set TMGn1 as the corresponding counter to GCCnm register and TIGM TOGnm pin Specifies the valid edge of external capture signal input pin TIGm for the capture register performing capture match with the assigned counter TMGn0 or TMGn1 Valid Edge Falling edge Rising edge No edge detection performed Both rising and falling edges Remarks 1 0 5 2 1104 316 Preliminary User s Manual U15839EE1VOU
286. Timing Chart SCKOn input output SOOn output 510 input SOTBFLn register SOTBLn register SIOLn register SIRBLn register Reg WR Reg RD CSOT bit INTCSIn interrupt rq cir trans rq Remarks 1 din 3 din 4 4 dout dout 2 dout 3 dout 4 dout 5 din 1 din 2 dout 1 din 5 dz des ana ums n d1 SOTBn d2 OTBn d SOTBn d4 OTBn d5 SIRBn d1 SIRBn d2 SIRBn d3 SIRBn d4 Period during which next transfer can be reserved 0 2 2 Reg Wh Internal signal This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written Reg RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq cir Internal signal Transfer request clear signal trans rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the first transfer Following the transmission reception completion interrupt request INTCSIOn transfer is continued if the SOTBn register can be written within the next transfer reservation period If the SOTBn register cannot be written transfer ends and the SIRBn register does not receive the new value of the SlOn register The last receive data can be obtained by reading the SIOn register following completion of the transfer Prelimi
287. WPHS 0 Address R W After reset WPHS CORPER S L 582 R W 00H WPRERR WDTM register Protection Error Flag 0 no WDTM register writing error has occurred 1 an WDTM register writing error has occurred Preliminary User s Manual U15839EE1VOUMOO 361 Chapter 12 Watchdog Timer Function 12 4 Operation 12 4 4 Operating as watchdog timer Once the watchdog timer is started RUN 1 after reset the RUN WDTM4 and WDTMSG bits cannot be changed These bits can be cleared only by reset input 1 2 Watchdog Timer Mode 1 Interrupt Set WDTMA bit of the watchdog timer mode register WDTM 1 and WDTM3G bit to 0 to oper ate as a watchdog timer in interrupt request mode to detect program runaway Setting RUN bit of WDTM register to 1 starts the count After counting starts if RUN bit is set to 1 again within the set time interval for runaway detection the watchdog timer is cleared and counting starts again If RUN is not set to 1 and the runaway detection time has elapsed a non maskable interrupt INTWDT is generated no reset functions The watchdog timer stops running in the STOP mode Consequently set RUN to 1 and clear the watchdog timer before entering the STOP mode Do not set the watchdog timer when operating the HALT mode since the watchdog timer is running in HALT mode For details of the possible time settings please refer to Figure 12 2 Watchdog Timer Clock
288. XD1 FCTXD2 FCRXD2 FCTXD3 FCRXD3 4 FCRXD4 Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only 428 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 2 2 CAN memory and register layout All buffers and registers of the FCAN system are arranged within a memory layout of 4 5 KB Figure 14 2 Memory Area of the FCAN System Address Offset 113FH canaNote register section 2 bytes register 1100H 10FFH canghote register section 2 bytes register 10C0H 10BFH CAN module section CAN register section 2 bytes register 1080H 107FH register section 2 bytes register 1040H 103FH illegal addresses 1030H 102FH CAN interrupt pending and operation control register section 1000H O9FFH illegal addresses 0400H CAN message buffer section with 32 message buffer 32 bytes message buffer 0000H Note CAN module and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Remarks 1 Effective address PP BASE address offset 2 The memory area is located in the 16 KB programmable peripheral I O area of the V850E CA2 The base address PP BASE of the programmable peripheral I O area is set by the BPC register 3 The memory area of the FCAN system is divided into certain functional sections The start and end addresses of those secti
289. XD3 CRXDx RXEN TEN CAN module x receive logic Remarks 1 Both TEN bit and RXEN bit must be set 1 to use the internal CAN bus 2 Using the internal CAN bus connects all CAN modules CAN module 1 to CAN module 4Note to one internal CAN bus The internal CAN bus is used to operate the FCAN sys tem without any external hardware e g CAN transceiver bus harness etc 3 1104 Note CAN module 3 and CAN module 4 are available in the derivatives uPD703129 A and uPD703129 A1 only Caution The internal test bus must only be used when none of the CAN modules are con nected to a CAN bus 466 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 3 3 CAN interrupt pending registers 1 CAN interrupt pending register CCINTP The CCINTP register summarizes all grouped interrupt pending signals Each of them is assigned to an unambiguous interrupt vector of the V850E CA2 This register is read only and can be read in 8 bit and16 bit units Figure 14 21 CAN Interrupt Pending Registers CCINTPL CCINTPH Address Initial 15 14 13 12 11 1009 8 7 6 5 4 3 2 1 OifsetNote 1 value o 7 To DEI a om Address Initial OffsetNote value Bit Name i Bit Position Note 2 3 Function 2 Indicates an error interrupt of CAN module x OR function of CxINT6 to CxINT2 bits of CCINTPH CGINTP register 8 5 2 GANXEBES 0 No Interrupt pending CCINTPL 1 Interrupt pending 1 Ind
290. a des 211 Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Processed 1 2 sse 213 Example of Processing Interrupt Requests Simultaneously Generated 215 Interrupt Control Register 216 Interrupt Mask Registers 0 to IMRO to IMR3 219 In Service Priority Register ISPR ssssssssssseseeeeren nennen 220 Maskable Interrupt Status Flag ID sse 220 Port Interrupt Input Circuit P52 P53 P61 P62 P63 64 221 Timer Input Circuit P30 P35 P40 P45 P54 55 221 NME put CitGuities 3 2 t piod edet se ee 221 Interrupt Mode Register 0 IMTMO sesseeennne nme 223 Interrupt Mode Register 1 IMTM1 eese 224 Interrupt Mode Register 2 IMTM2 _ mmn 225 Interrupt Mode Register IMTM8 mmn 226 Software Exception Processing sse nne 227 RETI Instruction Processing nnne 228 Exception Status Flag EP cc cccssseeceeseeeeeeeeeeeeeeeceaeeeseaaesecaeeesaaaeeseneeeseaaeeseaeeseaes 229 Exception Trap 88
291. able one priorities than the currently serviced interrupt request is generated the interrupt request is acknowledged along with the SUB WATCH mode release Table 9 10 Operation after SUB WATCH mode release by interrupt request NMI request Branches to handler address Maskable interrupt Branches to handler address or Executes the next instruction request executes the next instruction Remark If SUB WATCH mode is entered during execution of a particular interrupt handler and an unmasked interrupt request with a higher priority than the previous one is subsequently generated the program branches to the vector address for the later interrupt 262 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 2 When released by RESET input This operation is the same as normal reset operation The Oscillator stabilization time must be ensured by reset input Figure 9 11 Sub Watch mode released by RESET input Sub Watch mode setting Main Oscillation circuit dat System clock S css FU Main OSC STOP state T n i RESET signal E Internal system reset signal Ensuring elapse of oscillation Main Oscillation circuit stop stabilization time by RESET at I Preliminary User s Manual U15839EE1VOUMOO 263 Chapter 9 Clock Generator 3 When released by Watchdog Timer RESET input CPU operation starts after main oscillation stabilization time has been secured
292. ace Function 4 Clocked serial interface reception buffer registers Low SIRBLO to SIRBL2 The SIRBLn register is an 8 bit buffer register that stores receive data n 0 to 2 When the receive only mode is set TRMD bit of CSIMn register 0 the reception operation is started by reading data from the SIRBLn register These registers are read only in 8 bit units In addition to reset input these registers can also be initialized by clearing 0 the CSIE bit of the CSIMn register The SIRBLn register is the same as the lower bytes of the SIRBn register Figure 13 25 Clocked Serial Interface Reception Buffer Registers Low SIRBLO to SIRBL2 7 6 5 4 3 2 1 0 Address Initial value SIRBLO SIRB7 SIRBO FFFF FDO2H SIRB7 to SIRBO Stores receive data Read the SIRBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOT bit of CSIMn register z O If the SIRBL n register is read during data transfer the data cannot be guaranteed Cautions 1 Preliminary User s Manual U15839EE1VOUMOO 399 Chapter 13 Serial Interface Function 5 Clocked serial interface read only reception buffer registers SIRBEO to SIRBE2 The SIRBEn register is a 16 bit buffer register that stores receive data n 0 to 2 These registers are read only in 16 bit units In addition
293. address 2n lt 2 gt Access to odd address 2n 1 Address Address 7 7 7 7 2n 2 1 0 0 0 0 Byte data External Byte data External data bus data bus Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 2 Halfword access 16 bits a When the bus width is 16 bits Little Endian 1 Access to even address 2n Address 15 15 2n 1 8 8 7 7 2n 0 0 Halfword External data data bus 2 Access to odd address 2n 1 1 st Access Address 15 15 2n 1 8 8 7 Ya 0 0i Halfword External data data bus b When the data bus width is 8 bits Little Endian 1 Access to even address 2n 1 st Access 15 8 Address 7 7 2n 0 0 Halfword External data data bus 2 nd Access 15 8 Address 7 7 2n 1 0 0 Halfword External data data bus 2 Access to odd address 2n 1 1 st Access 15 8 Address 7 7 2n4 1 0 0 Halfword External data data bus Preliminary User s Manual U15839EE1VOUMOO 2 nd Access Address 15 154 71 8 7 7 2 2 0 0 Halfword External data data bus 2 nd Access 15 8 Address 7 7 2n 2 0 0 Halfword External data data bus 121 Chapter 4 Bus Control Function c When the data bus width is 16 bits Big Endian 1 Access to even address 2n 2 Access to odd address 2n 1 1 st Access 2 nd Access Address Address Address 15 15 15 i5 3 15 15 2n Lt 2 2 8 8 8 8 1 8 8 7 7 7 7 7 Tu xt Band 2n 4 1 0
294. advertent write access so that the system does not stop in case of a program hang up This register can be only written in 8 bit units undefined data is used when this register is read Only the first write access to a specific on chip register hereafter referred to as a specific register after data has been written to the PHCMD register is valid In this way the value of the specific register can be rewritten only in a specified sequence and an illegal write access is inhibited Figure 3 18 Peripheral Command Register PHCMD Format 6 5 4 3 2 1 0 Address RAW At Reset 7 REG7 0 registration code any 8 bit data Caution The register must be written with store instruction execution by CPU DMA transfer is prohibited If an illegal store operation takes place it can be checked by the PRERR flag of the peripheral status register PHS Caution Write to this register by DMA transfer is prohibited Preliminary User s Manual U15839EE1VOUMOO 105 Chapter 3 CPU Function 3 6 3 Peripheral Status Register PHS The flag PRERR in the peripheral status register PHS indicates protection error occurrence This register can be read written in 8 bit units or bit wise Figure 3 19 Peripheral Status Register PHS Format 4 3 0 Address R W At Reset T 6 5 2 1 Protection error detection If an incorrect write operation in a sequence without accessing the command register is performed to a protected internal register the reg
295. ag is set when GCOny is read Correct capture data by checking the value of CCFGy Preliminary User s Manual U15839EE1VOUMOO 335 Chapter 10 Timer b Example Capture where both edges of TIGm are valid match and clear For the timing chart TMGn0 is selected as the counter corresponding to TOGn1 and OFFFH is set in GCCnO Figure 10 50 Timing when both edges of TIGm are valid match and clear ED Son Count start Clear ad gt INTCCGn1 No match and clear Match and clear No match and clear Remark The figure above shows an image In actual circuitry 3 to 4 periods of the count up signal are required from the input of a waveform to TOGn1 until a capture interrupt is output See Figure 10 42 Timing of capture trigger edge detection free run on page 327 Caution If two or more match and clear events occur between captures a software based measure needs to be taken to count INTCCGnO or INTCCGn5 c When OOOOH is set in GCCn0 or GCCn5 match and clear When OOOOH is set in GCCn0 GCCn5 the value of the counter is fixed at 0000H and does not operate Moreover INTCCGn0 INTCCGn5 continues to be active d When FFFFH is set in GCCn0 or GCCn5 match and clear When FFFFH is set in GCCn0 GCCn5 operation equivalent to the free run mode is performed When an overflow occurs INTTMGnO INTTMGn1 is generated but INTCCGnO INTCCGn5 is not generated 336 Preliminary User s
296. age event pointer 011 M EVTO011 RAN X Undefined xxxxn022H message event pointer 012 M EVTO12 R W X Undefined Xxxxn023H message event pointer 013 M EVTO13 RW X Undefined xxxxn024H CAN message data length register 01 M DLCO1 RAN X Undefined xxxxn025H message control register 01 M CTRLO1 R W X Undefined xxxxn026H CAN message time stamp register 01 M TIMEO1 R W x Undefined Xxxxn028H message data register 010 M DATAO10 R W X Undefined Xxxxn029H message data register 011 M DATAO11 R W X Undefined Xxxxn02AH message data register 012 M DATAO12 R W X Undefined xxxxn02BH message data register 013 M DATAO13 R W X Undefined Xxxxn02CH message data register 014 M DATAO14 R W X Undefined xxxxn02DH message data register 015 M DATAO15 R W X Undefined Xxxxn02EH message data register 016 M DATAO16 R W X Undefined Xxxxxn02FH message data register 017 M DATAO17 R W X Undefined xxxxn030H message ID register L01 M IDLO1 R W x Undefined Xxxxn032H CAN message ID register H01 M IDHO1 RAN x Undefined xxxxn034H CAN message configuration register 01 M CONFO1 R W X Undefined xxxxn035H message status register 01 M STATO1 R x Undefined xxxxn036H status set cancel register 01 SC STATO W 0000 Preliminary User s Manual U15839EE1VOUMOO 85 Address xxxxn040H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 2 18
297. age status register 02 M STATO2 Undefined xxxxn056H CAN status set cancel register 02 SC STAT02 0000H Xxxxn0O60H CAN message event pointer 030 M EVTO030 Undefined xxxxn061H CAN message event pointer 031 M_EVT031 Undefined xxxxn062H CAN message event pointer 032 M_EVT032 Undefined XxxxnO63H CAN message event pointer 033 M EVTO33 Undefined xxxxn064H CAN message data length register 03 M DLCO3 Undefined Xxxxn065H CAN message control register 03 M CTRLOS Undefined Xxxxn066H CAN message time stamp register 03 M TIMEO3 Undefined Xxxxn068H CAN message data register 030 M DATAO30 Undefined Xxxxn069H CAN message data register 031 M DATAOS1 Undefined xxxxnO6AH CAN message data register 032 M_DATA032 Undefined xxxxnO6BH CAN message data register 033 M_DATA033 Undefined Xxxxn06CH CAN message data register 034 M_DATA034 Undefined xxxxnO6DH CAN message data register 035 M DATAO035 Undefined XxxxnO6EH CAN message data register 036 M_DATA036 Undefined XxxxnO6FH CAN message data register 037 M_DATA037 X K kK kK Undefined xxxxn070H CAN message ID register L03 M IDLO3 Undefined xxxxn072H CAN message ID register H03 M IDHO3 Undefined xxxxn074H CAN message configuration register 03 M CONFOS
298. al HALT SUB important bits IDLE STOP WATCH WATCH WATCH Main OSCDIS 0 Oscillator OSCDIS 1 Sub SOSTP 1 Oscillator SOSTP 0 SSCG PLL CLS CKS 000 CLS CKS 001 CLS CKS 01x CLS CKS 1xx Peripheral PERIC 0 clock PERIC 1 TMC CMODE 0 clock CMODE 1 CLS CKS 000 CLS CKS 001 CLS CKS 01x CLS CKS 1xx WDTSEL x0 WDTSEL 01 WTSEL1 0 WTSEL1 1 Remarks fy main oscillator frequency foc SSCG output frequency fxxp PLL output frequency fy sub oscillator frequency fpcik peripheral clock frequency Pa Bw N A not available Note The functionality of the SSCG or the PLL depends on the setting of the according bit 254 Preliminary User s Manual U15839EE1VOUMO00 Chapter 9 Clock Generator Table 9 3 Power Saving Mode Functions Pin Function operate operate operate operate operate operate HIGH operate INTPO5 INTPOO INTP15 INTP10 INTP21 INTP20 INTP5 to INTPO NMI TOG04 to TOGO1 TOG14 to TOG11 A operate TOCO 5002 SO01 SO00 A operate 102 S101 S100 A operate operate operate operate operate operate SCK02 SCK01 SCK00 A operate RXD51 RXD50 A operate TXD51 TXD50 A operate FCRXD4 1Note 3 A operate FCTXD4 1Note 3 A operate ANI11 to ANIO operate P1 P2 P3 P4 P5 P6 P9 i operate PAH 7 0 PCS 4 3 0 PCT 1 0 PCT 4
299. al interrupt 1 P55 TICO1 input Timer G 0 capture input 0 P30 INTPOO input Timer G 0 capture input 1 P31 TOGO01 input Timer G 0 capture input 2 P32 TOGO02 input Timer G 0 capture input 3 P33 TOGO03 input Timer G 0 capture input 4 P34 TOG04 input Timer G 0 capture input 5 P35 TOGO05 output Timer G 0 compare output 1 P31 TIGO1 output Timer G 0 compare output 2 P32 TIGO2 output Timer G 0 compare output 3 P33 TIGO3 output Timer G 0 compare output 4 P34 TIGOA input Timer G 1 capture input O P40 INTP10 input Timer G 1 capture input 1 P41 TOG11 input Timer G 1 capture input 2 P42 TOG12 input Timer G 1 capture input 3 P43 TOG13 input Timer G 1 capture input 4 P44 TOG14 All Vpp3 pins have to be connected to each other On each pin of Vpps a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin On CVpp a capacitor containing a very low serial impedance has to be attached as tight as possible to the pin Vpp3 and CVy must be connected to each other CAN module and CAN module 4 are available in the derivatives uPD703129 A and PD703129 A1 only Preliminary User s Manual U15839EE1VOUMOO 37 Pin Name I O Chapter 2 Pin Functions Table 2 2 Non Port Pins 3 3 Function Alternate input Timer G 1 capture input 5 P45 TOG15 output Timer G 1 compare output 1 P41 TI
300. al operating mode 0 Access to CAN module registers is prohibited except mask registers and tempo rary buffers Note 1 1 Operation of all CAN modules are enabled Temporary buffers can be read only Note 1 Caution To ensure that resetting the CAN modules do not cause any unex pected behaviour on the CAN bus the GOM flag can only be cleared if all CAN modules are set into initialisation state exception forced shut down see EFSD flag If the software clears the flag while at least one CAN module is still not in initialisation state ISTAT flag of CxCTRL register x 1 to 4 is set 1 the GOM flag remains set 458 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 12 CAN Global Status Register CGST 3 3 Write Sets clears the EFSD bit CL EFSD Status of EFSD Bit ST EFSD EFSD bit is cleared 0 CL EFSD EFSD bit is set 1 No change in EFSD bit value Status of TSM Bit TSM bit is cleared 0 TSM bit is set 1 No change in TSM bit value Status of EVM Bit EVM bit is cleared 0 EVM bit is set 1 No change in EVM bit value Status of GOM Bit bit is cleared 0 Note 2 GOM bit is set 1 Others No change in GOM bit value Clears the MERR bit CL MERR 0 No change of MERR bit 1 MERR bit is cleared 0 Notes 1 Access to the message buffer area is not affected 2 Refer t
301. alculated according to the following formula effective address PP BASE address offset 2 This error code only occurs in single shot mode SSHT bit of the CxDEF register 1 496 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 5 CAN 1 to 4 error counter registers C1ERC to CAERC The CxERC registers reflect the status of the transmit and the receive error counters of the corresponding CAN module x x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A These registers can be read only in 8 bit and 16 bit units Figure 14 37 CAN 1 to 4 Error Counter Registers C1ERC to C4ERC Address Initial OffsetNote value C1ERC REC7 REC6 REC5 REC4 REC3 REC2 Rec Reco rec TEC6 recs reca reco TEC2 rec1 reco 1056H 0000H C2ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 RECO TEC7 reco recs reca reco TEC2 TEC1 TECO 1096H 0000H C3ERC REc7 REce RECS REC REC3 2 1 6 recs reca recs TEC2 rec1 reco 10D6H 0000H 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 REC7 to The receive error counter REC holds the status of the error counter of reception RECO errors as defined in the CAN protocol TEC7to The transmit error counter TEC holds the status of the error counter of transmission TECO errors as defined in the CAN protocol Note The register addres
302. an be reset asynchronously 2 When CAE 0 the TMDn unit is in a reset state To operate TMDn first set CAE 1 3 When the CAE bit is changed from 1 to 0 all the registers of the TMDn unit are initialized When again setting CAE 1 be sure to then again set all the registers of the TMDn unit Caution The CAE bit and CE bit cannot be set at the same time Be sure to set the CAE bit prior to setting the CE bit Preliminary User s Manual U15839EE1VOUMOO 301 Chapter 10 Timer 10 2 5 Operation 1 Compare operation TMDn can be used for a compare operation in which the value that was set in a compare register CMDn is compared with the TMDn count value n 0 1 If a match is detected by the compare operation an interrupt INTTMDn is generated The generation of the interrupt causes TMDn to be cleared to 0 at the next count timing This function enables Timer Dn to be used as an interval timer CMDn can also be set to 0 In this case when an overflow occurs and TMDn becomes 0 a match is detected and INTTMDn is generated Although the TMDn value is cleared to 0 at the next count timing INTTMDn is not generated according to this match Figure 10 23 Timing of Compare Operation 1 2 a When CMDn is set to m non zero foount Count up TMDn clear TMDn CMDn Match detected INTTMDn MM Remarks 1 Interval time m 1 x Count clock cycle 2 m 1 to 65536 FFFFH 3 nz0 1 302 Prelimin
303. an be started by the TRAP instruction software exception or by generation of an exception event i e fetching of an illegal opcode exception trap Eight levels of software programmable priorities can be specified for each interrupt request Interrupt servicing starts after no fewer than 11 system clocks 343 ns 32 MHz following the generation of an interrupt request 8 1 Features Interrupts Non maskable interrupts 2 sources Maskable interrupts 63 sources 8 levels of programmable priorities maskable interrupts Multiple interrupt control according to priority Masks can be specified for each maskable interrupt request Noise elimination edge detection and valid edge specification for external interrupt request sig nals Exceptions Software exceptions 32 sources Exception traps 2 sources illegal opcode exception and debug trap Interrupt exception sources are listed in Table 8 1 Interrupt Exception Source List on page 200 Preliminary User s Manual U15839EE1VOUMOO 199 Chapter 8 Interrupt Exception Processing Function Table 8 1 Interrupt Exception Source List 1 3 Interrupt Exception Source Classifi Default Exception Handler cation Controlling Generating Source Generating Priority Code Address Register Unit Interrupt RESET RESET input Pin 00000000H undef NMIO P60 NMI Input Port Module 00000010H nextPC Interrupt NMIWDT Watchdog timer WDT 00000020H nextPC NMI2 Unused 0000
304. and Register Access 420 Interrupt Request and Register Access Contention 421 Baud Rate Generators 0 1 BRGO BRG1 Block 423 Prescaler Mode Registers 0 1 PRSMO 1 424 Prescaler Compare Registers 0 1 PRSCMO 1 425 Functional Blocks of the FCAN Interface 428 Memory Area of the FCAN 429 Clock Structure of the FCAN System sss 438 FCAN Interrupt Bundling of V850E CA2 439 Time Stamp Capturing at Message 441 Time Stamp Capturing at Message 442 16 Bit Data Write Operation for Specific Registers 453 CAN Stop Register CSTOP ssssssssseeeneeen nennen enemies 454 CAN Main Clock Select Register CGSC 1 2 sss 455 Configuration of FCAN System Main Clock 456 Configuration of FCAN Global Time System 456 CAN Global Status Regi
305. ansmission reception completion interrupt request INTCSIOn read the SIRBn register and the SIOn registerNete Note When transferring n number of data receive data is loaded by reading the SIRBn register from the first data to the n 2 th data The n 1 th data is loaded by reading the SIRBEn register and the n th last data is loaded by reading the SlOn register Figure 13 37 Repeat Transfer Receive Only Timing Chart SCKOn input output l l l Slon input dnf din 2 din 3 din Lans EEEEEEPEPESEDEEEEEESEREREETEDEEEEEDEETE Trin register pon m m SIRBEn d4 Reg RD SIRBn dummy SIRBn d1 SIRBn d2 SIRBn d3 SIOn d5 CSOT bit INTCSIn T i i i interrupt SOO0n output L rq cir trans rq IL F Y d 2 3 lt 4 gt d 4 lt 3 gt 4 5 Period during which next transfer can be reserved Remarks 1 n 0to2 2 Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq cir Internal signal Transfer request clear signal trans rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the first transfer Following the transmission reception completion interrupt request INTCSIOn transfer is continued if the SIRBn register can b
306. apter 17 RESET 17 7 Initialization Initialize the contents of each register as needed within a program Table 17 2 shows the initial values of the CPU internal RAM and on chip peripheral I O s after reset Table 17 2 Initial Values of CPU and Internal RAM After Reset Initial Value After Reset General purpose register rO 00000000H Program registers General purpose registers r1 to r31 Undefined Program counter PC 00000000H Status save registers during interrupt EIPC EIPSW Undefined Status save registers during NMI FEPC FEPSW Undefined Interrupt cause register ECR 00000000H System registers Program status word PSW 00000020H Status save registers during CALLT execution CTPC CTPSW Undefined On Chip Hardware Register Name Status save registers during exception debug trap DBPC DBPSW Undefined CALLT base pointer CTBP Undefined Internal RAM Undefined Caution In the table above Undefined means either undefined at the time of a power on reset or undefined due to data destruction when RESET J input and data write timing are synchronized On a RESET J other than this data is maintained in its previous status 588 Preliminary User s Manual U15839EE1VOUMOO Appendix A List of Instruction Sets Figure A 1 How to Read Instruction Set List This column shows instruction groups Instructions are divided into each instruciton group and described This column s
307. arallel data into serial data n O to 2 The transfer operation is not started even if the SlOn register is read These registers are read only in 16 bit units In addition to reset input this register can also be initialized by clearing 0 the CSIE bit of the CSIMn register Figure 13 32 Serial I O Shift Registers SIOO to SIO2 Initial value 5100 51015 51014 81013 S112 18101181010 SIO9 S108 8107 106 S105 5104 8103 102 SIO1 15100 FFFF FDOAH 0000H 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 15 0 SIO15 to Data is shifted in reception or shifted out transmission from the MSB or 5100 LSB side Caution Access the SlOn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register 0 If the SIOn register is accessed during data transfer the data cannot be guaranteed 406 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 12 Serial I O shift registers Low SIOLO to SIOL2 The SIOLn register is an 8 bit shift register that converts parallel data into serial data n 0 to 2 The transfer operation is not started even if the SIOL n register is read These registers are read only in 8 bit units In addition to reset input this register can also be initialized by clearing 0 the CSIE bit of the CSIMn register The SIOLn register is the same as the lower bytes of the SlOn register
308. architecture and supports up to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 5 shows the CPU address space Figure 3 5 CPU Address Space CPU address space FFFF FFFFH 4 Data area 4 Gbyte linear 0400 0000H 03FF FFFFH Program area 64 Mbyte linear 0000 0000H Preliminary User s Manual U15839EE1VOUMOO 65 Chapter 3 CPU Function 3 4 2 Image 64 MB physical address space is seen as 64 images in the 4 GB CPU address space In actuality the same 64 MB physical address space is accessed regardless of the values of bits 31 to 26 of the CPU address Figure 3 6 shows the image of the virtual addressing space Physical address x000 0000H can be seen as CPU address 0000 0000H and in addition can be seen as address 0400 0000H address 0800 OOOOH address F800 0000H or address FC00 0000H FFFF FCOO FBFF F800 F7FF 0800 07FF 0400 O3FF 0000 66 Figure 3 6 Image on Address Space CPU address space FFFFH 0000H FFFFH Physical address space 0000H Peripheral 1 0 x3FF FFFFH FFFFH Internal RAM External memory 0000H FFFFH x000 0000H Image Pd 0000H d FFFFH Image 0000H Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 4 3 Wrap around of CPU address space 1
309. areas whose initialization has been finished 134 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 10 Bus Priority Order There are three external bus cycles DMA cycle operand data access and instruction fetch As for the priority order the highest priority has the DMA cycle instruction fetch and operand data access in this order An instruction fetch may be inserted between read access and write access during read modify write access Also an instruction fetch may be inserted between bus access and bus access during CPU bus clock Table 4 2 Bus Priority Order Priority Order External Bus Cycle Bus Master DMA cycle DMA controller Operand data access CPU Instruction fetch CPU Preliminary User s Manual U15839EE1VOUMOO 135 Chapter 4 Bus Control Function 4 11 Boundary Operation Conditions 4 11 1 Program space 1 Branching to the peripheral I O area or successive fetch from the internal RAM area to the internal peripheral I O area is inhibited In terms of hardware fetching the NOP opcode continues and fetching from the external memory is not performed 2 If a branch instruction exists at the upper limit of the internal RAM area a pre fetch operation invalid fetch that straddles over the internal peripheral I O area does not occur when instruction fetch is performed 4 11 2 Data space The V850E CA2 Jupiter is provided with an address misalign function Through this fun
310. ary User s Manual U15839EE1VOUMOO foount Count up TMDn clear TMDn CMDn Match detected INTTMDn Overflow Chapter 10 Timer Figure 10 23 Timing of Compare Operation 2 2 b When CMDn is set to 0 Remark Interval time FFFFH 2 x Count clock cycle Preliminary User s Manual U15839EE1VOUMOO 303 Chapter 10 Timer 10 2 6 Application example 1 1 2 lt 3 gt lt 4 gt lt 5 gt 304 Interval timer This section explains an example in which Timer Dn is used as an interval timer with 16 bit precision Interrupt requests INTTMDn are output at equal intervals refer to Figure 10 23 Timing of Com pare Operation 1 2 on page 302 The setup procedure is shown below n 0 1 Set the CAE bit to 1 Set each register Select the count clock using the CS2 to CSO bits of the TMCDn register Set the compare value in the CMDn register Start counting by setting the CE bit to 1 If the TMDn register and CMDn register s values match an INTTMDn interrupt is generated INTTMDn interrupts are generated thereafter at equal intervals Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 2 7 Precautions for Timer Dn Various precautions concerning Timer Dn are shown below 1 2 7 To operate Timer Dn first set to 1 the CAE bit of the TMCDn register Up to fpc 2 clocks are required after a value is set the CE bit of the TMCDn register unt
311. ase Note The internal system reset signal keeps its active level for at least four system clock cycles after a RESET pin is released Preliminary Users Manual U15839EE1VOUMOO 585 Chapter 17 RESET 2 Resetat power on A low level for the oscillator stabilization time has to be applied to the RESET pin This is to secure the clock stabilization time that is necessary after the power is turned on and before a reset signal can be acknowledged Please refer to the Electrical Data Sheet for Jupiter Figure 17 2 Reset at power on RESET pin Oscillation Analog stabilization time delay Pt m A Reset release 586 Preliminary User s Manual U15839EE1VOUMOO Chapter 17 RESET 17 5 Reset by Watchdog Timer Jupiter s watchdog timer can be configured to generate a Reset in case watchdog time expires This signal is expanded by the clock controller An output from clock controller is input into the Reset circuit Oscillation stabilization time is not required after this reset Except WDT reset was triggered in sub watch mode or stop mode This case is handled by the clock controller 17 6 Reset Output Jupiter has an output RESOUT pin to indicate an internal system reset caused by RESET pin or Watch dog timer This reset output is used to terminate any ongoing internal erasing or programming operation in the external FLASH memory connected to the Jupiter device Preliminary Users Manual U15839EE1VOUMOO 587 Ch
312. ase by RESET NMI or maskable interrupt Set STOP mode ete 1 HALT mode Set IDLE mode ete 1 IDLE mode Notes 1 The SSCG and PLL is deactivated per hardware 2 Enable SSCG and PLL manual Software STOP mode 252 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 4 2 Power Save Modes Outline V850E CA2 Jupiter is provided with the following standby modes HALT IDLE WATCH and software STOP Application systems which are designed so that these modes are switched appropriately according to operation purposes reduce power consumption efficiently 1 2 3 4 5 HALT mode In this mode supply of the operating clock to the CPU is stopped whereby other on chip peripheral functions continue to operate Combining this mode with the normal operating mode to provide intermittent operations enables the overall system power consumption to be reduced This mode is entered by executing the dedicated instruction HALT IDLE mode In this mode the clock generator continues to operate but stopping the supply of internal system clock stops the overall system As it is not necessary to secure the oscillation stabilization time it is possible to switch to the normal operating mode quickly in response to a release signal This mode provides low power consumption where the power is only consumed from the OSC Main oscillator Sub Oscillator and Watch timer Watchdog timer This mode is ente
313. assumption that lt 3 gt and lt 4 gt above are executed by the pro gram with consecutive store instructions If another instruction is set between 3 and 4 the above sequence may become ineffective when the interrupt is accepted by that instruction and a malfunction of the program may result Although the data written to the PHCMD register is dummy data use the same register as the general register used in specific register setting lt 4 gt for writing to the PHCMD register 3 The same method should be applied when using a general register for addressing At least 5 NOP instructions must be inserted after executing a store instruction to the PSC register to set software STOP or IDLE mode Do not perform a write operation to the PRCMD and specific registers using DMA transfer To write data to the PSC register use the store instruction ST SST and bit manipula tion instruction SET1 CLR1 NOT1 The contents of this register can be read in the nor mal sequence It is recommended to monitor the status of the clock sources after a power save mode has been released If a power save mode release condition happened after setting the STP bit but before the system has entered the related power save mode the clock source may not be changed already to the main oscillator In this case PLL SSCG still remains operating Preliminary User s Manual U15839EE1VOUMOO 269 Chapter 9 Clock Generator 9 5 2 Power Save Mode Register PS
314. ata register 154 M DATA154 Undefined xxxxn1EDH CAN message data register 155 M DATA155 Undefined xxxxn1 EEH CAN message data register 156 M_DATA156 Undefined xxxxn1 EFH CAN message data register 157 M_DATA157 Undefined xxxxn1FOH CAN message ID register L15 M IDL15 Undefined xxxxn1F2H CAN message ID register H15 M IDH15 Undefined xxxxn1F4H CAN message configuration register 15 M CONF15 Undefined xxxxn1F5H CAN message status register 15 M STAT15 Undefined xxxxn1F6H CAN status set cancel register 15 SC STAT15 0000H xxxxn200H CAN message event pointer 160 M_EVT160 Undefined xxxxn201H CAN message event pointer 161 M EVT161 Undefined xxxxn202H CAN message event pointer 162 M EVT162 Undefined Xxxxn203H CAN message event pointer 163 M EVT163 Undefined xxxxn204H CAN message data length register 16 M DLC16 Undefined xxxxn205H CAN message control register 16 M CTRL16 Undefined xxxxn206H CAN message time stamp register 16 M TIME16 Undefined Xxxxn208H CAN message data register 160 M DATA160 Undefined Xxxxn209H CAN message data register 161 M_DATA161 Undefined xxxxn20AH CAN message data register 162 M_DATA162 Undefined xxxxn20BH CAN message data register 163 M DATA163 Undefi
315. ation of the CAN Message Buffer Section Address OffsetNote Name 800H to 81FH Message buffer 0 820H to 83FH Message buffer 1 840H to 85FH Message buffer 2 3COH to 3DFH Message buffer 30 to SFFH Message buffer 31 Note The address of a message buffer entry is calculated according to the following formula effective address PP BASE address offset Each message buffer has the same register layout refer to Table 14 2 CAN Message Buffer Registers Layout on page 431 430 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Table 14 2 CAN Message Buffer Registers Layout A T Address Offset ccess lype Note 1 2 1 bit 8bit 16 bits m x 20H M EVTmO Message event register Note 3 m x 20H M EVTm1 Message event register 1Note 3 m x 20H M EVTm2 Message event register 2Note 3 m x 20H M EVTm3 Message event register 3Note 3 m x 20H M DLCm Message data length code register m x 20H M CTRLm Message control register m x 20H M TIMEm Message time stamp register m x 20H M DATAmO Message data byte 0 m x 20H M_DATAm1 Message data byte 1 m x 20H M_DATAm2 Message data byte 2 m x 20H 80BH M_DATAm3 Message data byte 3 m x 20H 80CH M_DATAm4 Message data byte 4 m x 20H 80DH M_DATAm5 Message data byte 5 m x 20H 80EH DATAm6 Message data byte 6 m x 20H 80FH DATAm7 Message data byte 7
316. baud rate generators 0 1 BRGO BRG1 1 Selecting the baud rate generator The CSIOO to CSIO2 serial clocks can be selected between dedicated baud rate generator output or internal peripheral clock fpc The serial clock source is specified by bits CKS2 to CKSO of registers CSICO and CSIC1 refer to 12 3 3 2 Clocked serial interface clock selection registers 0 1 CSICO CSIC1 If the dedicated baud rate generator output is specified BRGO or BRG1 respectively is selected as the clock source Since the same serial clock can be shared for transmission and reception baud rate is the same for the transmission reception Figure 13 42 Baud Rate Generators 0 1 BRG0 BRG1 Block Diagram fpcik 2 fpoik 4 2 8 8 bit timer counter 8 B fpcik 16 aL 1 2 CSIOn Match detector PRSCMn Remarks 1 fpc y internal peripheral clock BGCS1 BGCSO 2 nz 0to2 Preliminary User s Manual U15839EE1VOUMOO 423 Chapter 13 Serial Interface Function 2 Configuration BRGn is configured of an 8 bit timer counter that generates the baud rate signal a prescaler mode register n PRSMn that controls baud rate signal generation a prescaler compare register n PRSCMnh that sets the value of the 8 bit timer counter and a prescaler 0 to 2 a Input clock The internal peripheral clock fpc is input to BRGn b Prescaler mode registers 0 1 PRSMO PRSM1 The PRSMnh register controls the generatio
317. be set to 0 Specifies active level of external pulse output TOCO 0 Active level is low level 5 ALV 1 Active level is high level Caution The initial value of the ALV bit is 1 280 Preliminary User s Manual U15839EE1VOUMOO Bit Position Chapter 10 Timer Figure 10 6 Timer C control Register 1 TMCCO1 2 2 Bit name Function Enables disables TMCO clearing during compare operation 0 Disable clearing 1 Enable clearing TMCO is cleared when CCC00 and TMCO match during com pare operation Selects operation mode of capture compare register CCCO1 0 Register operates as capture register 1 Register operates as compare register Selects operation mode of capture compare register 0 Register operates as capture register 1 Register operates as compare register Preliminary User s Manual U15839EE1VOUMOO 281 Chapter 10 Timer 3 Valid edge selection register SESCO This register specifies the valid edge of external interrupt requests from an external TICmn pin n to 1 The rising edge the falling edge or both rising and falling edges can be specified as the valid edge independently for each pin This register can be read written in 8 bit or 1 bit units Caution Do not change the bits of SESCO register during timer operation If they have to be changed they must be changed after setting the CE bit of the TMCCOO register to 0 If the SESCO register is
318. by interrupt request 260 Operating States in WATCH Mode sse enne nnns 261 Operation after SUB WATCH mode release by interrupt request 262 Operating States in STOP Mode sse nennen nnns 265 Timer C Configuration ai 274 TOGO O tp t or eme t Ere 291 Timer Dn Configuration List n 0 1 eee 297 Timer Gn Configuration List nnne 309 Interrupt output and timer output states dependent on the register setting values ssseeene 322 Interrupt output and timer output states dependent on the register setting values sseeeen 323 Configuration of Watch Timer ssssssssssssssses eene 350 Selection of the Watch Timer Clock sssssssssssseeeen enne nnns 352 Example for Interval Time of Watch Timer essem 353 Example for Interval Time of Interval Timer seem 354 Watchdog Timer Configuration 358 Generated Interrupts and Default Priorities sssssseneee 374 Transmission Status and Whether or Not Writing Is Enabled 377 Reception Error Causes eene nennen snnt nnns 381 Baud Rate Generator Setting Data
319. ccess CS7 active during block 13 access CS7 active during block 12 access 112 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 4 Programmable peripheral I O registers In the V850E CA2 the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I O area In this area the area between x0000H and x11FFH is used exclusively for the FCAN controller The internal bus of the V850E CA2 becomes active when the peripheral I O register area FFFFOOOH to FFFFFFFH or the programmable peripheral I O register area xxxxm000H to xxxxnFFFH is accessed m xx0OB xx11B Note that when data is written to the peripheral I O register area the written contents is reflected on the peripheral I O register since peripheral I O register area is allocated to the last 4 KB of the programmable peripheral I O register area Cautions Remark Figure 4 3 Programmable Peripheral I O Register Outline 3FFFFFFH Peripheral Internal local bus 3FFFOOOH I O register 3FFEFFFH XxxxNFFFH XxxxxM000H 0000000H Programmable Peripheral nem peripheral I O area x3000H VO register x2FFFH Programmable E peripheral EH VO area a Dedicated area for e x0000H FCAN controller 1 The programmable peripheral area must not be located above the address X1FFFFFFH 2 Once the address of the programmable peripheral area is se it cannot be changed 3 If the p
320. cese pi DRE wah eas EA tea eee TRAE 374 re initlaliZ6 2 5 xe LI EIDEM EIE Pd MM UI imi Gra 583 RESET 124 hesstewdsmeehetes Sia MULA Nen denas V Ra Eds 49 RESET mode 3 cs Sect aac aic ue e reti m obe be iR be Eie 357 Reset signal acknowledgment eg cece te tee tenets 585 ROM esee hant mne AE EE D dt E MA LM Lt te Gant Are ru eg 30 DENM 145 ROMJE SS iret cbe stie det ire eH i eaae tcs ciere tes edere cera aee EA 62 RXBO RXBT acces ed ian Med ve xe ga Ad hub be RR Eas 372 S Sample and hold circ it iio De ui coe Uk Exe PR AU MAE ERR NK EA E E Mn 524 SAB e setae e Mettre A auch ts e ode S def arabe is a Tr Re ku eoi he a ages 524 Saturated operation instructions nen 24 Saturation e sade diet ns tia Nace GRE DEINDE aaa elses Ru nbi ehe a UE ee 61 Serial O shift register o emus eee up Seu ER MR BOUE Gee METER DES 406 Serial I O shift registers LOW ues eel ier uert whee ene Na 407 SES M UE Ef tA deu es heat aan oon ayn Reda r LAE 282 Signed load Instructions is ed side vut alt RE E Rer RE Xen Natal aon Paid 24 Sigried m ltiplicatiori se it e rte ertet ea e Mer ER RU E Re eg ie Mice e Ra e 24 SIOOMO SIO c Grasset ee cari ee Reg eg A eee A Berta 406 can toh oaiae Stared Re UE MES 407 SIRBO
321. cheme about which data bytes of the data field are replaced with the time stamp capture value according to the setting of the M DL Cm register m 00 to 31 M DLC m Figure 14 6 Time Stamp Capturing at Message Transmission Time stamp transmission CAN Global Time System Counter SOF Message ACK Bus Data 1 M DATAm 0 Temporary Buffer transmisson as last two data bytes Table 14 9 Transmitted Data On the CAN Bus ATS 1 Bus Data 2 Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note M DATAm 0 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note M DATAm 0 M DATAm 1 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note M DATAm 0 M DATAm 1 M DATAm 2 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note M DATAm 0 M DATAm 1 M DATAm 2 M DATAm 3 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note M DATAm 0 M DATAm 1 M DATAm 2 M DATAm 3 M DATAm 4 lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note M DATAm 0 M DATAm 1 M DATAm 2 Note CGTSC value captured at SOF Remark 442 m 00 to 31 M DATAm 3 M DATAm 4 M DATAm 5 Preliminary User s Manual U15839EE1VOUMOO lower 8 bit of CGTSC Note upper 8 bit of CGTSC Note Chapte
322. ck 5 system clock 6 system clock 7 system clock default Caution With respect to the specified operation frequency the following register settings for VSWC are recommended Preliminary User s Manual U15839EE1VOUMOO 107 Chapter 3 CPU Function Table 3 8 The Values of VSWC Register depending on System Clock System Clock Setup Wait Strobe Wait 4 0 MHz lt fopy lt 16 6 MHz 16 6 MHz lt fcpu lt 25 0 MHz 25 0 MHz fopy lt 32 0 MHz 108 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function The V850E CA2 Jupiter is provided with an external bus interface function by which external memories such as ROM and RAM and I O can be connected 4 1 Features e 16 bit 8 bit data bus sizing function 8 chip areas select function chip area select signals externally available C80 CS3 and CS4 Wait function Programmable wait function capable of inserting up to 7 wait states for each memory block External wait function through WAIT pin dle state insertion function External device connection can be enabled via bus control port alternate function pins 4 2 Bus Control Pins The following pins are used for connecting to external devices Register for Port Control Mode Switching Bus Control Pin Function when in Control Mode Function when in Port Mode Address data Data bus DO to D15 Address bus 0 to A15 Address bus
323. concept In the Full CAN concept a particular message buffer accepts only one single message hence there is no further sorting and filtering required by software As a consequence only one unambiguous identifier is assigned to a message buffer In the BasicCAN concept a receive message buffer operates as a channel which can accept several messages After reception software must sort respectively filter which particular message has been received By the usage of hardware masks the range of receive messages can be limited to reduce the CPU load caused by message sorting In the FCAN system each CAN module provides 4 different masks For a receive message buffer assigned to a CAN module one of the 4 masks can be selected when the BasicCAN concept is used When using a mask a certain identifier value must be written into the identifier register M IDm equals 32 bit value build by M IDHm and M IDL m of the receive message buffer at initialisation Then the linked mask CXMASKn composed from CXMASKHn and CxMASKLn determines which iden tifier bits of a received message must match exactly to accept the received message for the message buffer The mask facilitates that certain identifier bits of the received message will not be compared with the corresponding identifier bits of the message buffer thus several messages might be accepted for the receive message buffer Remarks 1 n 0to3 2 m 00 to 31 3 x21 to 2 for the derivative UPD703128
324. concerned CAN global status register CGST CAN global interrupt enable register CGIE CAN global interrupt pending register CGINTP CAN x interrupt pending registers CxINTP CAN x control registers CXCTRL CAN x definition registers CxDEF e CAN x interrupt enable registers CxIE CAN x bus activity registers CxBA Remark 1 to 2 for the derivative PD703128 A x 1 to 4 for the derivatives uPD703129 A and 0703129 A1 Registers like above where bit access and direct write operations are prohibited are organized in such a way that all bits allowed for manipulation are located in the lower byte bits 7 to 0 while in the upper byte bits 15 to 8 either no or read only information is located The registers can be read in the usual way to get all 16 data bits in their actual setting ref to appropri ated register description For setting or clearing any of the lower 8 bits the following mechanism is implemented When writing 16 bit data to the register address each of the lower 8 data bits indicates whether the cor responding register bit should be cleared data bit set or remain unchanged data bit not set Each of the upper 8 data bits indicates whether the corresponding register bit should be set data bit set or remain unchanged data bit cleared The organization of 16 bit data write for such registers is shown in Figure 14 7 16 Bit Data Write Oper ation for Specific Registers on
325. configuration 116 Byte access 8 bits ene ee 119 Preliminary User s Manual U15839EE1VOUMOO 601 Appendix Index C Cache configuration register BHC 0 cece nn 118 GABET 32 a seb A SE LE er GT d tO 58 Capture operation irisi sequere eEiR pp pe x ed a ea et qe ep nk e ry 285 capture trigger edge detection 327 Capture compare registers l lilslleseel hrs 276 COCOO 25 a veste t tL Um a tod s LU Cn Me fe DCUM iU E Ci LLL e 276 Conan LE niche peer Eee epu i i Nep DER Hen ete eis du 276 Chip area selection control registers 0 1 CSCO CSC1 111 prende der Pret Tele bet ier desti e SE 241 243 244 245 247 248 249 250 GKSROGKSRU 2 2 t Lebe b Ee vp LA emt 385 Clock Control Register lille hh 241 Clock control register 241 243 244 245 247 248 249 250 Clock select registers liliis hh rn 385 GIOCK SOUICES iE b dern n bet e p eed SERE 239 clock stabilization time te hn 586 Clocked serial interface clock selection registers 396 Clocked serial interface initial transmission buffer register 404 Clocked serial
326. ct a count clock cycle with the CSE12 to CSE10 bits TMGn1 register or CSE02 to CSEO0 bits TMGn0 register Write data to GCCnm Start timer operation by setting POWER and TMGOE or TMG1E Compare Operation When the value of the counter matches the value of GCCnm m 0 to 4 a match interrupt INTCCGnm is output When the counter overflows an overflow interrupt INTTMGnO INTTMGn 1 is generated Figure 10 44 Timing of compare mode free run ENFGO HEN TMGnO GCCn1 INTCCGn1 INTTMGnO Data N is set in GCCn1 and the counter TMGn0 is selected Preliminary User s Manual U15839EE1VOUMOO 329 Chapter 10 Timer b When the value 0000H is set in GCCnm INTCCGnm is activated when the value of the counter becomes 0001H INTTMGnO INTTMGn is activated when the value of the counter changes from FFFFH to OOOOH Note however that even if no data is set in GCCnm INTCCGnm is activated immediately after the counter starts c When the value FFFFH is set in GCCnm INTCCGnm INTTMGn0 INTTMGn1 are activated when the value of the counter changes from FFFFH to 0000H d When GCCnm is rewritten during operation When 1 is rewritten from 5555H to AAAAH TMGn0 is selected as the counter The following operation is performed Figure 10 45 Timing when GCCn1 is rewritten during operation free run GCCn1 Slave register GCCn1 Master register 5555H
327. ction regardless of the data format word data halfword data or byte data data can be placed in all addresses However in the case of word data and halfword data if data are not sub jected to boundary alignment the bus cycle will be generated a minimum of 2 times and bus efficiency will drop 1 In the case of halfword length data access When the address s LSB bit is 1 the byte length bus cycle will be generated 2 times 2 In the case of word length data access a When the address s LSB is 1 bus cycles will be generated in the order of byte length bus cycle halfword length bus cycle and word length bus cycle b When the address s lowest 2 bits are 10 the halfword length bus cycle will be generated 2 times 136 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function 5 1 SRAM External ROM External I O Interface 5 1 1 Features Access to SRAM takes a minimum of 2 states Upto 7 states of programmable data waits can be inserted through setting of the DWCO and DWC1 registers Data wait can be controlled with input pin WAIT Up to 3 idle states can be inserted after the read write cycle through setting of the BCC register Upto 3 address set up wait states can be inserted through setting of the ASC register Preliminary User s Manual U15839EE1VOUMOO 137 Chapter 5 Memory Access Control Function 5 1 2 SRAM connections An example of connection to SRAM is shown below
328. d I O or among I Os based on DMA requests issued by the on chip peripheral I O or software triggers memory refers to internal RAM 7 1 Features Four independent DMA channels Transfer units 8 16 and 32 bits Maximum transfer count 65 536 216 Two types of transfer two cycle transfer e Four transfer modes Single transfer mode Single step transfer mode Line transfer mode Four bus cycle transfer mode Block transfer mode Transfer requests Request by interrupts from on chip peripheral I O Requests by software trigger Transfer objects Between internal RAM and I O Between internal RAM and external I O Between internal RAM and internal RAM Between external memory and I O Between external memory and external memory Between I O and I O DMA transfer completion flag Next address setting function Preliminary User s Manual U15839EE1VOUMOO 169 Chapter 7 DMA Functions DMA Controller 7 2 Control Registers 7 2 1 DMA source address registers HO to DSAHO to DSAH3 These registers are used to set the DMA source addresses 28 bits each for DMA channel n n 0 to 3 They are divided into two 16 bit registers DSAHn and DSALn Since these registers are configured as 2 stage FIFO buffer registers a new source address for DMA transfer can be specified during DMA transfer refer to 7 3 Next Address Setting Function 1 DMA source address registers DSAHO to DSAH3 DSAHO to DSA
329. d bits are undefined Remark 00 31 472 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 2 Message configuration registers 00 to 31 M CONFOO to M CONF31 The M CONFm registers specify the message type mask link and CAN module assignment of the corresponding message m m 00 to 31 These registers can be read written 8 bit units Figure 14 25 Message Configuration Registers 00 to 31 CONFO00 to M CONF31 1 2 Address ih 6 5 4 3 2 1 OttsetNote 1 Initial value m x 20H Bit Position Bit Name Function Specifies the message type and mask link Message type and mask link Transmit message Receive message no mask linked Receive message mask 0 linked Nete 2 MT2 to MTO Receive message mask 1 linked Note 2 Receive message mask 2 linked Note 2 Receive message mask 3 linked Note 1 Reserved Note 3 Receive message in diagnostic mode type 7 Note 4 Preliminary User s Manual U15839EE1VOUMOO 473 Chapter 14 FCAN Interface Function Figure 14 25 Message Configuration Registers 00 to 31 CONFO00 to M CONF31 2 2 Assigns the message buffer to a CAN module CAN module assignment Message buffer is not assigned to a CAN module Nete 5 Message buffer is assigned to CAN module 1 MA1 MAO Message buffer is assigned to CAN module 2 Message buffer is assigned to CAN module 3Nete 6 Message buffer is assigned t
330. d directly to each memory block SRAM external ROM external I O Page ROM Connected external devices are specified by the bus cycle type configuration registers 0 1 BCTO BCT1 4 5 1 Bus cycle type configuration 1 Bus cycle configuration registers 0 1 BCTO BCT1 These registers can be read written in 16 bit units Initial value FFFFF480H 8888H 15 14 18 12 11 10 99 8 7 6 5 4 3 2 1 0 Address CS3 52 CS1 CS0 15 14 19 2 11 10 9 8 7 6 5 4 83 2 1 0 Address 118 Bort 0 BT70 MEG o o o o BTSO ME4 o BTAO FFFFA02H 8888H L l L L L CS7 CS6 CS5 CS4 15 11 7 3 Memory Controller Enable BCTO Sets memory controller operation enable for each chip select signal CSn 15 11 7 3 BCT1 Memory Controller Operation Enable Operation disable 1 Operation enable Bus Cycle Type Specifies the device to be connected to the CSn signal External Device Connected Directly to CSn signal 0 SRAM external I O 1 Page ROM Cautions 1 Write to the and BCT1 registers after reset and then do not change the set value Also do not access an external memory area other than that for this initial ization routine until initial setting of the and BCT1 registers is finished However it is possible to access external memory areas whose initialization has been finished 2 The bits marked as 0 are reserved They have to leave to 0
331. d rate error The baud rate error is obtained according to the following formula icc Actual baud rate baud rate with error _ 1 x100 96 Desired baud rate normal baud rate Cautions 1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable baud rate range during reception which is described in chapter 13 2 6 3 Allowable baud rate range during reception on page 389 Example Basic clock frequency 10 MHz Settings of MDL7 to MDLO bits in BRGCO register 01000001B 65 Target baud rate 76800 bps Baud rate 10 108 2 x 65 76923 bps Error 76923 76800 1 x 100 0 160 Preliminary User s Manual U15839EE1VOUMOO 387 Chapter 13 Serial Interface Function e Baud rate setting example Table 13 4 Baud Rate Generator Setting Data BaudRate PcLk 20 MHz 5 MHz 4 MHz EE k j ERR k ERR k ERR fpcLK 128 fpeLK 32 fpeLK 32 1200 fperg 64 fpc 64 2400 2 fpoLK 32 Lk 8 fpc k 8 4800 foci i6 fpoLK 16 PT fpcuk 4 9600 P L Kile 19200 1 4 L 1 2 fpoLk 2 31250 LK 2 L LK 2 2 38400 K 2 L K 2 fotki 76800 L 1 2 2 153600 L 1 2 fpoLk 2 Remark System c
332. data f Receive data for controller area network Input This pin inputs FCAN serial receive data g INPT20 INTP21 INTP4 INTP5 Interrupt request from peripherals Input These are external interrupt request input pins Note CAN module 4 is available in the derivatives PD703129 A and PD703129 A1 only 44 Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions 6 P60 to P67 Port 6 Input Output Port 6 is an 8 bit input output port in which input or output can be set in 1 bit units Besides functioning as an input output port in control mode P60 to P67 operate as the serial interface CSI2 or as an external interrupt request input An operation mode of port or control mode can be selected for each bit and specified by the port 6 mode control register PMC6 a Port mode P60 to P67 can be set to input or output in 1 bit units using the port 6 mode register PM6 b Control mode P60 to P67 can be set to port or control mode in 1 bit units using PMC6 c SO2 Serial output Output This pin output CSI2 serial transmit data d SI2 Serial input Input This pin input CSI2 serial receive data e SCK2 Serial clock Input output This pin is the CSI2 serial clock input output pin f INTPO INTP3 Interrupt request from peripherals Input These are external interrupt request input pins g NMI Non maskable interrupt request Input This pin is the n
333. data register 236 M DATA236 Undefined xxxxn2EFH CAN message data register 237 M DATA237 Undefined xxxxn2F0H CAN message ID register L23 M IDL23 Undefined xxxxn2F2H CAN message ID register H23 M IDH23 Undefined Xxxxn2F4H CAN message configuration register 23 M_CONF23 Undefined xxxxn2F5H CAN message status register 23 M STAT23 Undefined xxxxn2F6H CAN status set cancel register 23 SC STAT23 0000H xxxxn300H CAN message event pointer 240 M EVT240 Undefined xxxxn301H CAN message event pointer 241 M EVT241 Undefined xxxxn302H CAN message event pointer 242 M EVT242 Undefined xxxxn303H CAN message event pointer 243 M EVT243 Undefined xxxxn304H CAN message data length register 24 M DLC24 Undefined xxxxn305H CAN message control register 24 M CTRL24 Undefined xxxxn306H CAN message time stamp register 24 M TIME24 Undefined xxxxn308H CAN message data register 240 M DATA240 Undefined xxxxn309H CAN message data register 241 M DATA241 Undefined Xxxxn30AH CAN message data register 242 M DATA242 Undefined xxxxn30BH CAN message data register 243 M DATA243 Undefined xxxxn30CH CAN message data register 244 M DATA244 Undefined xxxxn30DH CAN message data register 245 M DATA245 Undefin
334. derations on page 509 Preliminary User s Manual U15839EE1VOUMOO 507 Chapter 14 FCAN Interface Function 10 CAN 1 to 4 bus diagnostic information registers C1DINF to CADINF The CxDINF registers reflect the last transmission on CAN bus of the corresponding CAN module X 1 to 4 for the derivatives UPD703129 A and 0703129 1 x 1 to 2 for the derivative uPD703128 A These registers can be read only in 1 bit 8 bit and 16 bit units It is only accessible when diagnos tic mode is set CxDEF registers MOM bit 1 Figure 14 43 1 to 4 Bus Diagnostic Information Registers C1DINF to CADINF Address Initial OffsetNot value C1DINF DINF15DINF14 DINF13 DINFT2 DINF1 t DINF0 DINF9 DINF8 DINF7 DINF6 DINF5 DINFA DINF3 DINF2 DINF1 DINFO 105CH 0000H C2DINF DINF15 DINF14 DINF13 DINF12 DINF1 1 DINF10 DINF9 DINF8 DINF7 DINF6 DINF5 DINF4 DINF3 DINF2 DINF1 DINFO 109CH 0000H C3DINF DINF15DINF14 DINF13 DINFT2 DINF1 1 DINF10 DINF9 DINF8 DINF7 DINF6 DINF5 DINF4 DINF3 DINF2 DINF1 DINFO 0DCH 0000H C4DI 111CH 0000H DINF15 to DINF8 DINF7 to Reflects the value of the last 8 bits transmitted on the CAN bus where DINFO ho
335. do not access an external memory area other than that for this initialization rou tine until initial setting of the BSC register is finished However it is possible to access external memory areas whose initialization has been finished 2 When the data bus width is specified as 8 bits only the LWR signal becomes active 116 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 6 3 Endian control function The endian control function can be used to set processing of word data in memory either by the Big Endian method or the Little Endian method for each CS area selected with the chip select signal CSO to CS7 Switching of the endian method is specified with the endian configuration register BEC 1 Endian configuration register BEC This register can be read written in 16 bit units se s pen v Tee v eem v eo v fw v Rem v v e L L L l L L L L 11 40 9 8 7 6 5 4 8 2 1 0 Address a value FFFFFOGBH 0000H CS7 CS6 CS5 CS4 CS3 CS2 CS1 CSO Bs mre 14 12 10 8 6 4 2 0 Cautions 1 Big Endian Specifies the endian method Endian Control 0 Little Endian method 1 Big Endian method Bits 15 13 11 9 7 5 3 and 1 of the BEC register must be cleared 0 If these bits are set to 1 the operation is not guaranteed Set the CSn area specified as the programmable peripheral I O area to Little Endian format n 0 to 7 In the fo
336. dule 00000430H nextPC nterrupt INTP15 P151C P45 Port Module 00000440H nextPC nterrupt INTP20 P20IC P54 Port Module 00000450H nextPC nterrupt INTP21 P21IC P55 Port Module 00000460H nextPC nterrupt reserved PIC63 reserved reserved 00000470H nextPC Notes 1 n 0 to FH 2 INTFC3RX INTFC3TX INTFC3ER INTFC4RX and INTFCAER are available only in the derivatives PD703129 and uPD703129 A1 Remarks 1 Default priority The priority order when two or more maskable interrupt requests are generated at the same time The highest priority is O 2 Restored PC The value of the PC saved to EIPC or FEPC when interrupt exception processing is started However the value of the PC saved when an interrupt is acknowledged during division DIV DIVH DIVU DIVHU instruction execution is the value of the PC of the current instruction DIV DIVH DIVU DIVHU 3 nextPC The PC value that starts the processing following interrupt exception processing 4 The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by Restored PC 4 202 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function 8 2 Non Maskable Interrupts A non maskable interrupt request is acknowledged unconditionally even when interrupts are in the interrupt disabled DI status
337. dules while the CPU tries to read data The copy of the message is automatically started whenever the data length code from the M DLOCm register is read by the CPU and the data is copied from the message buffer into the temporary buffer As long as the CPU reads 16 bit data from consecutive addresses that means 16 bit burst read sequence M DLCm M CTRLm gt M TIMEm gt M DATAmO0 m1 M DATAm2 m3 gt M DATAm4 m5 gt M DATAm6 m7 gt M IDLm M IDHm the data is read from the tem porary buffer Caution The burst read requires consecutive 16 bit read accesses to the memory area Any 8 bit access byte read operation even if not violating the linear address rule causes that the read is performed from the register instead of the temporary buffer Preliminary User s Manual U15839EE1VOUMOO 513 Chapter 14 FCAN Interface Function 14 4 4 Operating states of the CAN modules The different operating states and the state transitions of the CAN modules are shown in the state transition diagram in Figure 14 45 Figure 14 45 State Transition Diagram for CAN Modules Initialisation Mode INIT 0 CxCTRL ISTAT 1 PowerOn RESET Power Off or or RESET RESET INIT 1 and STOP 0and CAN bus idle SLEEP 0 Power Offor FORESTS RESET CAN bus idle Inter mediate State CAN bus busy INIT 1 and CAN bus busy STOP Mode CxCTRL ISTAT 0 CxCTRL SLEEP
338. dy to be handled by the assigned CAN module Remark Transmit as well as receive messages are only handled by the assigned CAN module if the RDY flag is set refer to Table 9 16 Notes 1 The register address is calculated according to the following formula effective address PP BASE address offset V850E CA2 Jupiter has no CAN bridge implemented CAN module and CAN module 4 are available in the derivatives PD703129 A and uPD703129 A1 only Remark 00 31 Preliminary User s Manual U15839EE1VOUMOO 475 Chapter 14 FCAN Interface Function Processing of a transmit or receive message by TRQ and RDY flags is summarized in 14 16 Table 14 16 CAN Message Processing by TRQ and RDY Bits Message Type Message Processing Message buffer is disabled for any processing by the Any assigned CAN module Message buffer is ready for reception Receive message Request for sending a remote frame No processing of the transmit message Transmit message Request for message transmission 476 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 4 Message set clear status registers 00 to 31 SC STATO to SC STAT31 The SC STATm registers set clear the flags of the corresponding M STATm registers m 2 00 to 31 By means of this register transmission can be requested and reception can be con firmed These registers can be written only in 16 bit units F
339. e on page 438 This register can be read written in 1 bit 8 bit and16 bit units Figure 14 9 CAN Main Clock Select Register CGSC 1 2 Address Initial OffsetNote value CGCS CGTS7 CGTS6 CGTS5 CGTS4 CGTS3CGTS2 CGTStICGTSOIGTSCO GTSCO 0 MCS MCP3 MCP2 MCP1 1014H 7FO5H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Specifies the 8 bit prescaler compare value for the global time system clock fas ref to Fig 9 11 CGTS7 to CGTSO Prescaler Global Time System Clock 1 fats farsi 1 fats farsi CGTS7 to fets fars1 2 CGTSO fars farsi fats fare 256 Remark The global time system clock is the source clock for the 16 bit timer used for the time stamp functionality This clock is common for all CAN modules Selects the global time system basic clock from the memory clock fmem ref to Fig 9 11 Global Time System Basic Clock fars farsi fem 2 f rst 4 farsi fmem 8 fars1 fmem 16 Selects input clock for the memory access clock prescaler fren ref to Fig 9 10 0 internal system clock fep 1 external clock input fey7 Note Note V850E CA2 doesn t offer an external clock fmem supply pin Therefore the MCS must not be set at any time Note The address of an interrupt pending register is calculated according to the following formula effective address PP BASE addres
340. e 3 adr lt GR reg1 sign extend disp16 GR reg2 lt sign extend Load memory adr Halfword disp16 reg1 reg2 rrrrrll110 OIRRRRR ddddddddd ddddddi Note 3 adr lt GR reg1 sign extend disp16 GR reg2 Load memory adr Word reg2 disp7 ep rrrrr0111 ddddddd adr lt ep zero extend disp7 Store memory adr GR reg2 Byte reg2 disp8 ep rrrrr1001 ddddddd Note 1 adr lt ep zero extend disp8 Store memory adr GR reg2 Halfword reg2 disp8 ep rrrrr1010 ddddddi Note 2 adr lt ep zero extend disp8 Store memory adr GR reg2 Word reg2 disp16 regt rrrrr1110 10RRRRR ddddddddd ddddddd adr lt GR reg1 sign extend disp16 Store memory adr GR reg2 Byte ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Only the lower half word data is valid dddddddddddddddadadad is the higher 21 bits of dip22 dddddddd is the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification Preliminary Users Manual U15839EE1VOUMOO 593
341. e A D input channels ANI11 to P77 to P70 ns Dn P77 to P70 holds the digital input values of the A D input channels ANI7 to Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0to 11 Preliminary User s Manual U15839EE1VOUMOO 573 Chapter 16 Port Functions 16 3 9 Port 9 Port 9 is an 8 bit input output port in which input or output can be specified in 1 bit units Port mode con trol is not available for port 9 This register can be read or written in 1 bit and 8 bit units Figure 16 27 Port 9 P9 0 Address At Reset 7 6 5 4 3 2 1 P9n n 7 to 0 Input output port Remark In Input Mode When the P9 register is read the pin levels at that time are read Writing to the P9 register writes the values to that register This does not affect the input pins In Output Mode When the P9 register is read the values of P9 are read Writing to the P9 register writes the values to that register and those values are immediately output Note The reset value of register P9 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Setting in input output mode Port 9 is set in input output mode using the port 9 mode register PM9 a Port 9 mode register PM9 This register can be read or written in 8 bit or 1 bit units Figure 16 28 Port 9 Mode Register PM9 Address At Reset 7 6 5 4 3 2 1 0
342. e address of an interrupt pending register is calculated according to the following for mula effective address PP BASE address offset 2 CAN module and CAN module 4 are available in the derivatives UPD703129 A and uPD703129 A1 only Remark 00 31 464 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 8 CAN message search result register CGMSR The CGMSR register returns the result of a message search started by writing the CGMSS regis ter This register is read only and can be read in 16 bit units Figure 14 18 CAN Message Search Result Register CGMSR Address Initial OffsetNote value 101AH 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cousa o Ts preesse per Indicates the match result of the preceding message search Number of Hits No match 1 message meets the search criteria Note 2 Several message meet the search criteria Indicates the number of the message buffer which was found by the message search 0 to 31 Note 2 Remarks 1 Any search will start from the message number defined by STRT5 to MFND5 to STRTO and end at the highest available message buffer If a search MFNDO results in multiple matches the lowest buffer number is returned To get the next match without modifying the search criteria the STRT5 to STRTO bits must be set to the succeeding number of the found one in MFND5 to MFNDO of the CGM
343. e disable settings are possible only for those CSn areas in which no instruction for setting the BHC register exists For example if a BHC register setting instruction exists in the CSO area the instruction cache of the CSO area cannot be set cache enable disable settings In this case only the instruction cache settings for areas CS1 to CS7 are possible Preliminary Users Manual U15839EE1VOUMOO 167 5 168 Chapter 6 Instruction Cache Access to memory boundary If adjacent chip select CSn areas are a cacheable area and an uncacheable area continuous access across the memory boundary is possible only by using a branch instruction Operation is not guaranteed if the memory boundary is continuously accessed by instruction other than a branch instruction An example is shown below Suppose that the cache area settings are as shown in figure iCache Area Setting Example In this case access to the memory areas is as follows From CSO area to CS1 area access is possible only by using a branch instruction From CS1 area to CS2 area continuous access is possible Figure 6 9 iCache Area Setting Example CS2 area Cacheable area CS1 area CSO area Uncacheable area Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller The V850E CA2 includes a direct memory access DMA controller DMAC that executes and controls DMA transfer The DMAC controls data transfer between memory an
344. e implementation of low power systems The device provides the following power saving functions These modes can be combined and switched to suit the target application which enables effective implementation of low power systems Table 9 1 Power Saving Modes Overview Operation of Clock Supply to Clock Source Oscillator Peripherals Main Osc Sub Osc Initial Mode Normal Normal HALT SSCG PLL IDLE enabled WATCH SUB WATCH STOP Remarks 1 x Operates 2 Stopped Notes 1 If the OSCDIS bit 1 than the Main Oscillator is stopped 2 Ifthe SOSTP bit 0 than the Sub Oscillator operates Preliminary User s Manual U15839EE1VOUMOO 251 Chapter 9 Clock Generator Figure 9 10 shows the operation of the clock generator in normal operation mode HALT mode IDLE mode WATCH mode SUB WATCH mode and software STOP mode An effective low power consumption system can be realized by combining these modes and switching modes according to the required use Figure 9 10 Power Save Mode State Transition Diagram Watch mode E Sub Watch mode Set WATCH mode ete 1 Release by RESET NMI or maskable interrupt Set Sub WATCH mode 91 a a Release by RESET NMI or maskable interrupt Release by RESET NMI or maskable interrupt Notes Note 2 Normal operation mode Set HALT mode Release by RESET NMI or maskable interrupt Note 2 Rele
345. e lock is released it again operates as an instruction cache Instruction cache autofill performs the following procedure 1 2 3 4 5 Remarks Caution Clear invalidate the tags of way 0 see Tag Clear Function on page 163 Set the address corresponding to the memory area to be autofilled in the instruction cache data configuration register ICD Branch to the cacheable area corresponding to the tag information set in the ICD register Set bit 4 FILLO of the instruction cache control register ICC When autofill is complete bit 12 LOCKO of the ICC register is automatically set 1 and the way 0 is locked At that same time read bit FILLO of the ICC register and confirm that bit is cleared 0 1 Alock is released by clearing bit LOCKO of the ICC register 2 While the iCache autofill operation is ongoing neither interrupt nor NMI will be served by CPU until the iCache autofill procedure is finished Even for the situation that a required interrupt service function is by chance already available in the second way of iCache CPU can not access these opcodes until the autofill operation of the iCache way 0 is completed Direct opcode execution from the VSB is also not possible in gen eral during the processing time of the autofill operation 3 Since the autofill operation is performed from the external memory to the instruction cache via the VSB other processing can be performed at the same time bu
346. e of CxINT2 bit 1 CxINT2 bit is cleared 0 Clears the interrupt pending bit CxINT1 CL CxINT1 0 No change of CxINT1 bit 1 CxINT1 bit is cleared 0 Remarks Caution Clears the interrupt pending bit CxINTO CL CxINTO 0 No change of CxINTO bit 1 CxINTO bit is cleared 0 x 1 to 2 for the derivative uPD703128 x 1 to 4 for the derivatives uPD703129 A and PD703129 A1 1 The interrupts CxINT1 to CxINT6 are only generated when the corresponding interrupt enable bit in the CGIE register is set 2 The interrupt pending bits must be cleared by software in the interrupt service routine In case the interrupt pending bit is not cleared by software in the interrupt service routine no subsequent interrupt is generated anymore Preliminary User s Manual U15839EE1VOUMOO 471 Chapter 14 FCAN Interface Function 14 3 4 CAN message buffer registers 1 Message identifier registers LOO to L31 and to H31 M IDLOO to M_IDL31 M IDHOO to M_IDH31 The M_IDLm M_IDHm registers specify the identifier and format of the corresponding message m m 00 to 31 These registers can be read written 16 bit units Figure 14 24 Message Identifier Registers L00 to L31 to H31 M IDLOO to M IDL31 M IDHOO to M_IDH31 Address Initial We da OffsetNete 1 value 15 12 0 9 8 7 6 5 4 3 2 IDE ID28 ID27 ID26 1D25 ID24 ID23 1022 1021110 20 1019 1 18 1 17 1 16 8124 under m x 20H
347. e port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register P4 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 3 CAN module 4 is available in the derivatives uPD703129 A and PD703129 A1 only 566 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 2 Setting in input output mode and control mode Port 5 is set in input output mode using the port 5 mode register PM5 In control mode it is set using the port 5 mode control register PMC5 a Port 5 mode register PM5 This register can be read or written in 8 bit or 1 bit units Figure 16 20 Port 5 Mode Register PM5 0 Address At Reset 7 6 5 4 3 2 1 pies 50s LPSa EMSS EMSA PMSS PMER PMST FERRHABBHL EH PM5n Specifies input output mode of P5n pin 7to0 n 7 to 0 0 Output mode Output buffer on k 1 Input mode Output buffer off Preliminary User s Manual U15839EE1VOUMOO 567 Chapter 16 Port Functions b Port 5 mode control register PMC5 This register can be read or written in 8 bit or 1 bit units Figure 16 21 Port 5 Mode Control Register PMC5 3 2 1 0 Address At Reset 7 6 5 4 5 0 56 PMC55 PMC54 PMC53 PMC52 PMC51 50 FFFFF448H Specifies operation mode of P55 pin 0 Input outpu
348. e read within the next transfer reservation period If the SIRBn register cannot be read transfer ends and the SIRBn register does not receive the new value of the SIOn register The last data can be obtained by reading the SIOn register following completion of the transfer Preliminary User s Manual U15839EE1VOUMOO 415 Chapter 13 Serial Interface Function b Usage transmission reception 1 Set the repeat transfer mode AUTO bit of CSIMn register 1 and the transmission reception mode TRMD bit of CSIMn register 1 2 Write the first data to the SOTBFn register 3 Write the 2nd data to the SOTBn register start transfer 4 Wait for transmission reception completion interrupt request INTCSIOn 5 When the transmission reception completion interrupt request INTCSIOn has been set to 1 write the next data to the SOTBn register reserve next transfer and read the SIRBn register to load the receive data 6 Repeat steps 4 and 5 as long as data to be sent remains 7 Wait for the INTCSIOn interrupt When the interrupt request signal is set to 1 read the SIRBn register to load the n 1 th receive data 8 Following the last transmission reception completion interrupt request INTCSIOn read the SlOn register to load the n th last receive data 416 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function Figure 13 38 Repeat Transfer Transmission Reception
349. e reset value of register PCT is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Alternate Pin Name Remarks Block Type Read strobe output Port CT Upper write strobe signal output Lower write strobe signal output Caution In case that a port pin PCTO PCT1 or PCT4 operates as a control signal for the exter nal memory interface LWR UWR or RD it is recommended to plug in an external pull up resistor to that pin Preliminary User s Manual U15839EE1VOUMOO 579 Chapter 16 Port Functions 2 Setting in input output mode and control mode Port CT is set in input output mode using the port CT mode register PMCT In control mode it is set using the port CT mode control register PMCT a Port CT mode register PMCT This register can be read or written in 8 bit or 1 bit units Figure 16 36 Port CT Mode Register PMCT 0 Address At Reset 7 6 5 4 3 2 1 Specifies input output mode of PCT4 pin 0 Output mode Output buffer on 1 Input mode Output buffer off Specifies input output mode of PCT1 pin 0 Output mode Output buffer on 1 Input mode Output buffer off Specifies input output mode of PCTO pin 0 Output mode Output buffer on 1 Input mode Output buffer off b Port mode control register PMCCT This register can be read or written in 8 bit or 1 bit units Figure 16 37 Port
350. e set 1 when a reception error occurs and are reset 0 when the ASISn register is read Asynchronous serial interface transmission status registers ASIFO ASIF1 The ASIFn register is an 8 bit register that indicates the status when a transmit operation is performed This register consists of a transmission buffer data flag which indicates the hold status of TXBn data and the transmission shift register data flag which indicates whether transmission is in progress Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register A check for parity errors is also performed during a receive operation and if an error is detected a value corresponding to the error contents is set in the ASISn register Reception shift register This is a shift register that converts the serial data that was input to the RXD5n pin to parallel data One byte of data is received and if a stop bit is detected the receive data is transferred to the reception buffer register RXBn This register cannot be directly manipulated Reception buffer registers RXBO RXB1 RXBn is an 8 bit buffer register for holding receive data When 7 characters are received 0 is stored in the MSB During a reception enabled state receive data is transferred from the reception shift register to the RXBn synchronized with the end of the shift in processing of one frame Also the reception completion interrupt requ
351. e specified for the source and destination address of DMA transfer Be sure to specify an address between FFFFOOOH and FFFFFFFH Preliminary User s Manual U15839EE1VOUMOO 193 Chapter 7 DMA Functions DMA Controller 7 8 DMA Channel Priorities The DMA channel priorities are fixed as follows DMA channel 0 DMA channel 1 DMA channel 2 DMA channel 3 These priorities are valid in the TI state only In the block transfer mode the channel used for transfer is never switched In the single step transfer mode if a higher priority DMA transfer request is issued while the bus is released in the TI state the higher priority DMA transfer request is acknowledged 7 9 DMA Transfer Start Factors There are two types of DMA transfer start factors as shown below 1 Request from on chip peripheral I O If the ENn and the TCn bits of the DCHCn register are set as shown below and an interrupt request is issued from the on chip peripheral I O that is set the DTFRn register the DMA trans fer starts ENn bit 1 TCn bit 2 0 2 Request from software If the STGn the ENn and the TCn bits of the DCHCn register are set as follows the DMA transfer starts STGn bit 1 ENn bit 1 e TCn bit 0 Remark nz0to3 194 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 Functions Controller 7 10 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer At such a t
352. e that the quantization error is not included in the overall error zero scale error full scale error and non linearity error in the characteristics table Figure 15 15 Quantization Error Digital output Ue AVREF Analog input 4 Zero scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 1 2 LSB when the digital output changes from 0 000 to 0 001 If the actual measurement value is greater than the theoretical value it shows the difference between the actual measurement value of the analog input voltage and the theoretical value 3 2 LSB when the digital output changes from 0 000 to 0 010 Figure 15 16 Zero Scale Error er tt renee ae 001 SEE Zero scale error Digital output Lower order 3 bits 000 1 LA 1 y 0 1 2 3 vae Analog input LSB Preliminary User s Manual U15839EE1VOUMOO 543 Chapter 15 A D Converter 5 Full scale Error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 3 2 LSB when the digital output changes from 1 110 to 1 111 Figure 15 17 Full Scale Error Full scale error 111 Mp z ve 1014 ff Ideal line Digital output Lower order 3 bits il 0 AVner 3 AVner 2 AVnaer 1 AVREF Analog input LSB 6 Nonlinearity Error T
353. e the DMAC has released the bus the higher priority DMA transfer request always takes precedence However if a lower priority DMA transfer request is generated within one clock after the end of a line transfer even if the previous higher priority DMA transfer request signal stays active this request is not prioritized and the next DMA transfer after the bus is released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figure 7 22 Line Transfer Example 1 on page 190 shows a DMA transfer example in line transfer mode Figure 7 22 Line Transfer Example 1 DMA Transfer Request CH3 Note Note DMA channel 3 terminal count Figure 7 23 Line Transfer Example 2 on page 190 shows DMAC transfers in line transfer mode in which a higher priority DMA transfer request is generated DMA channels 0 to 2 are used for a block transfer and channel 3 is used for a line transfer Figure 7 23 Line Transfer Example 2 DMA Transfer Request CHO Transfer Request 1 Transfer Request CH2 DMA Transfer Request CH3 channel 1 DMA channel 3 terminal count terminal count DMA channel 0 DMA channel 2 terminal count terminal count Note The bus is always released 190 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller Figure 7 24 Line Transfer Example 3 on page 191 and Figure 7 25 Line Transfer Example 4 on page 191
354. e used as CSO CS3 CS4 by using PMCCS c CS0 CS3 CS4 Chip select Output This is the chip select signal for external SRAM external ROM or external peripheral I O The signal CSn is assigned to memory block n n 0 3 4 This is active for the period during which a bus cycle that accesses the corresponding memory block is activated It is inactive in an idle state TI Preliminary User s Manual U15839EE1VOUMOO 47 11 12 48 Chapter 2 Pin Functions PCTO PCT1 PCT4 Port CT Input output Port CT is a 3 bit input output port in which input or output can be set in 1 bit units Besides functioning as a port in control mode it operates as control signal output when memory is accessed externally An operation mode of port or control mode can be selected for each bit and specified by the port CT code control register PMCCT a Port mode PCTO PCT1 PCT4 can be set to input or output in 1 bit units using the port CT mode register PMCT b Control mode uu PCTO PCT1 PCT4 can be used as LWR UWR RD by using PMCCT c LWR Lower byte write strobe Output This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM external ROM or an external peripheral I O area d UWR Upper byte write strobe Output This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM external ROM or an external peripheral I O area e RD Read strobe
355. e values mentioned above must not be changed after initialization Caution This register can only be written if the SSCG enable bit SCEN is cleared Preliminary User s Manual U15839EE1VOUMOO 249 Chapter 9 Clock Generator 9 3 8 SSCG Frequency Control Register 1 SCFC1 This is an 8 bit register that controls the second frequency divider of the SSCG It determines the SSCG output frequency in fixed frequency mode and the upper SSCG output frequency in dithering mode This register can be read or written in 8 bit or 1 bit units Figure 9 9 SSCG Frequency Control Register 1 SCFC1 7 6 5 4 3 2 1 0 Address nitial value Bit Position Bit Name Function Specifies the second frequency divider of the SSCG fy 4 MHz SCFC17 to SCFC10 Fixed or Upper SSCG frequency fy 003FH 128 MHz fy 5 MHz SCFC17 to SCFC10 Fixed or Upper SSCG frequency fy 0032H 127 5 MHz SCFC17 to SCFC10 The initialization of the SCFC1 register depends to the output frequency supplied by the main oscillation circuit The values mentioned above must not be changed after initialization Caution This register can only be written if the SSCG enable bit SCEN is cleared 250 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 4 Power Saving Functions 9 4 1 General The device provides the following power saving functions These modes can be combined and switched to suit the target application which enables effectiv
356. e width measurement both edges TMCO count values TMCO Overflow OVF lt 1 Count start TICO1 Remark DO to D2 TMCO count values 286 Preliminary User s Manual U15839EE1VOUMOO aans N 5 aH an A Chapter 10 Timer c Example Cycle measurement By setting the TMCCOO TMCC01 registers as described below Timer C can measure the cycle of signals input to the TICnO pin The valid edge of the TICOO pin is selected according to the IESO1 and IESOO bits of the SESCO register Similar the valid edge of the TICO1 pin is selected according to the IES11 and IES10 bits of the SESCO register Either the rising edge the falling edge or both edges can be selected as the valid edges of both pins Setting method set corresponding port pins P5 to Timer C input PM5 to input PMC5 to Timer CO set CAE bit of TMCCOO register to 1 for activating the Timer C peripheral set the valid edge of the TICnO pin with the IESO1 and IESOO bits of the SESCO register here for rising edge IESO1 0 IESOO 1 set CMS1 and CMSO bits of TMCCO 1 register to 0 set CE bit to enable the counter and start operation Operation the valid edge input of the TICnO pin is set as the trigger for capturing the TMCO register value in the CCCOO register When this value is captured an INTCCCOO interrupt is generated Similarly the valid edge input of the TICnO pin is set as the trigger for captu
357. ed XxxxnO8FH CAN message data register 047 M_DATA047 X XXXIX XxX XxX Xx Undefined Xxxxn090H CAN message ID register L04 M IDLO4 Undefined Xxxxn092H CAN message ID register H04 M IDHO4 Undefined xxxxn094H CAN message configuration register 04 M_CONF04 Undefined Xxxxn095H CAN message status register 04 M STATO4 Undefined xxxxn096H CAN status set cancel register 04 M STATO4 0000H XxxxnOAOH CAN message event pointer 050 M EVTO50 Undefined xxxxn0A1H CAN message event pointer 051 M EVTO51 Undefined XxxxnOA2H CAN message event pointer 052 M_EVT052 Undefined XxxxnOA3H CAN message event pointer 053 M EVTO053 Undefined XxxxnOA4H CAN message data length register 05 M DLCO05 Undefined Xxxxxn0OA5H CAN message control register 05 M DTRLO05 Undefined XxxxnOA6H CAN message time stamp register 05 M TIMEO5 Undefined XxxxnOA8H CAN message data register 050 M_DATA050 Undefined XXxxnOA9H CAN message data register 051 M DATA051 Undefined XXXXhOAAH CAN message data register 052 M_DATA052 Undefined XxxxnOABH CAN message data register 053 M DATA053 Undefined XxxxnOACH CAN message data register 054 M_DATA054 Undefined XxxxnOADH CAN message data register 055 M_DATA055 Undefined XXXxnOAEH CAN message data re
358. ed xxxxn30EH CAN message data register 246 M DATA246 Undefined xxxxn30FH CAN message data register 247 M DATA247 X K kK kK Undefined Xxxxn310H CAN message ID register L24 M_IDL24 Undefined Xxxxn312H CAN message ID register H24 M IDH24 Undefined xxxxn314H CAN message configuration register 24 M CONF24 Undefined xxxxn315H CAN message status register 24 M STAT24 Undefined xxxxn316H CAN status set cancel register 24 SC STAT24 0000H Xxxxn320H CAN message event pointer 250 M_EVT250 Undefined Xxxxn321H 96 CAN message event pointer 251 M_EVT251 Preliminary User s Manual U15839EE1VOUMOO Undefined Address Xxxxn322H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 13 18 Function Register Name CAN message event pointer 252 M EVT252 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn323H CAN message event pointer 253 M EVT253 Undefined Xxxxn324H CAN message data length register 25 M_DLC25 Undefined Xxxxn325H CAN message control register 25 M_CTRL25 Undefined Xxxxn326H CAN message time stamp register 25 M_TIME25 Undefined Xxxxn328H CAN message data register 250 M DATA250 Undefined Xxxxn329H CAN message data register 251
359. eeeeeeeeeeeeeseeeeeeeaeeeeeeeeesaeeneeeeeees 528 A D Converter Register ADS enne nennen nnne 530 A D Conversion Result Register ADCR sssssseeeeeeeeeenn 531 A D Conversion Result Register ADCRL sese 531 A D Conversion Result Register ADCRH 532 Port Function Register PORT7 PORTS 533 Port Function Register 7 PORT 534 Relation between Analog Input Voltage and A D Conversion Result 536 No write operation is made to ADM or ADS register during A D conversion operation sess nennen 538 ADCS bit is cleared 0 during A D conversion 539 A write operation is made to the ADS register during A D conversion operation 540 Analog Input Pin Flandling 2n tnde 541 Overall Error o et pite oe e ee ru e d pede Tu ag ve eR de e Te e EDT d un 542 Q antization Error ie ione pera nte d beber binder et detta 543 Zero Scale EITOr 2 it et p e ae end te te 543 F ll Scale Error apaa SERGE EEan 544 EE pe ee ee eee 544 Port Configuratii iier testes endete e eb et re In Rp 546 Type A Block Diagram
360. eg2 sign extend imm5 ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Only the lower half word data is valid Adddddddddddddddddddd is the higher 21 bits of dip22 dddddddd is the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification 594 Preliminary User s Manual U15839EE1VOUMOO Instruction Group Appendix A List of Instruction Sets Operand Opcode Table A 6 Instruction Set List 3 7 Operation Arithmetic operation imm16 reg1 reg2 rrrrr110 OO0RRRRR AD 33 Tl GR reg2 GR reg1 sign extend imm16 regi reg2 rrrrr001 101RRRRR GR reg2 GR reg2 GR reg1 regi reg2 rrrrr001 100RRRRR GR reg2 GR reg1 GR reg2 reg1 reg2 rrrrr000 111RRRRR GR reg2 GR 2 Note4 GR reg1 Note 4 Signed multiplication imm5 reg2 rrrrr010 GR reg2 GR reg2 Note4 sign extend imm5 Signed multiplication imm16 reg1 reg2 rrrrr110 111RRRRR ote ge Jg GR reg2 GR reg1 Note4 imm16 signed multiplication regi reg2
361. egister Note 2 C4BRP 0000H xxxxn11DDH bus diagnostic information register Note 2 C4DINF 0000H xxxxn11DEH Notes 1 CAN4 synchronization control register Note 2 C4SYNC can be accessed in 16 bit units only during write 2 CAN2 and CANS are available only in uPD703129 16 Kbytes RAM Remark 102 n xx00b Preliminary User s Manual U15839EE1VOUMOO This registers can be accessed in 8 bit or 16 bit units during read and 0218H Chapter 3 CPU Function 3 6 Specific Registers Specific registers are registers that are protected from being written with illegal data due to erroneous program execution etc The write access of these specific registers is executed in a specific sequence and if abnormal store operations occur it is notified by the peripheral status register PHS The V850E CA2 Jupiter has five specific registers the clock control register the watchdog timer clock control register WCC the processor clock control register PCC and the power save control register PSC For details of the WCC and PCC register please refer to the chapter 9 3 1 Clock Control Reg ister CKC on page 241 For details of the PSC register please refer to the chapter 9 4 3 Power Saving Mode Functions on page 254 The access sequence to the specified registers is shown below The following sequence shows the data setting of the specific registers
362. el 4 gt Level 5 gt Level 6 gt Level 7 Low Interrupt processing that has been suspended as a result of multiple processing control is resumed after the processing of the higher priority interrupt has been completed and the RETI instruction has been executed A pending interrupt request is acknowledged after the current interrupt processing has been com pleted and the RETI instruction has been executed Caution In a non maskable interrupt processing routine time until the RETI instruction is exe cuted maskable interrupts are suspended and not acknowledged Preliminary User s Manual U15839EE1VOUMOO 235 Chapter 8 Interrupt Exception Processing Function 8 8 Interrupt Response Time The following table describes the V850E CA2 interrupt response time from interrupt generation to start of interrupt processing Except in the following cases the interrupt response time is a minimum of 5 clocks To input interrupt requests continuously leave a space of at least 5 clocks between interrupt request inputs During software or hardware STOP mode When an external bus is accessed When there are two or more successive interrupt request non sampling instructions see 8 9 Periods in Which Interrupts Are Not Acknowledged on page 237 When the interrupt control register is accessed Figure 8 28 Pipeline Operation at Interrupt Request Acknowledgment Outline 5 system clocks VBCLK Input i LILI Interrupt request
363. elect Control Function The 64 MB memory area can be divided into 2 MB 4 MB and 8 MB memory blocks by the chip area selection control registers 0 and 1 CSCO CSC1 to control the chip select signals The memory area can be effectively used by dividing the memory area into memory blocks using the chip select control function The priority order is described below 1 Chip area selection control registers 0 1 5 0 CSC1 These registers can be read written in 16 bit units Valid by setting each bit to 1 If different chip area select signals are set to the same block the priority order is controlled as follows CSCO Peripheral I O area gt CS0 gt CS2 gt CST gt CS3 Note CSC1 Peripheral I O area gt CS7 gt CS5 gt CS6 gt CS4 Note Notes 1 Not all the chip area select signals are externally available on output pins Even so enabling chip area select signals other than CSO CS3 or CS4 the setting for the corresponding memory blocks will be effective too regardless of an external chip select output pin 2 After reset Jupiter fetches the boot vector from CSO area Figure 4 2 Chip Area Select Control Registers 0 1 1 2 15 14 13 12 4 10 9 8 7 6 5 4 3 2 1 0 Address Ia 0533 0532 C831 0830 0823 05220521 C820 70813 C812 0511 0510 0503 S02 6501 CS00 3FFFFFOGOH 2011H L l L L CS3 CS2 CS CS0 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Address 18 CSC1 3FFFFF062H 2C11H Es rea r
364. en en esr creer esr e cer eer proe en L L l L CS4 CS5 CS6 CS7 Preliminary User s Manual U15839EE1VOUMOO 111 Chapter 4 Bus Control Function Figure 4 2 Chip Area Select Control Registers 0 1 2 2 Chip Select Enables chip select 50 active during block 0 access SO active during block 1 access SO active during block 2 access SO active during block 3 access S1 active during block 0 or 1 access S1 active during block 2 or 3 access S1 active during block 4 access S1 active during block 5 access S2 active during block 0 access S2 active during block 1 access S2 active during block 2 access S2 active during block 3 access S3 active during block 0 1 2 or 3 access S3 active during block 4 or 5 access S3 active during block 6 access S3 active during block 7 access S4 active during block 12 13 14 or 15 access S4 active during block 10 or 11 access S4 active during block 9 access S4 active during block 8 access S5 active during block 15 access S5 active during block 14 access CS5 active during block 13 access CS5 active during block 12 access CS6 active during block 14 or 15 access CS6 active during block 12 or 13 access CS6 active during block 11 access S6 active during block 10 access CS7 active during block 15 access CS7 active during block 14 a
365. en if interrupts are Roc enabled because its priority is the same as that of g Processing of h Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts When returning from multiple interrupt servicing restore the values of EIPC and EIPSW after executing the DI instruction Remarks 1 lt a gt to lt u gt in the figure are the temporary names of interrupt requests shown for the sake of explanation 2 The default priority in the figure indicates the relative priority between two interrupt requests Preliminary User s Manual U15839EE1VOUMOO 213 Chapter 8 Interrupt Exception Processing Function Figure 8 8 Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Processed 2 2 Main routine Processing of i El Processing of k Interrupt Interrupt request i Eos level 2 ficu E Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Processing of j Processing of interrupt Interrupt requests m and n are held pending request m because processing of is performed in the level 3 interrupt disabled status Interrupt request n level 1 Interrupt request level 2 f Pending interrupt requests are acknowledged after Processing of n processing of interrupt request 1 At
366. enerated NMIWDT request is executed NMIO servicing is halted Remark PSW NP The NP bit of the PSW register Cautions 1 Although the values of the PC and PSW are saved to an NMI status save register FEPC FEPSW when a non maskable interrupt request is generated only the NMIO can be restored by the RETI instruction at this time Because NMIWDT can not be restored by the RETI instruction the system must be reset after servicing this interrupt 2 If PSW NP is cleared to 0 by the LDSR instruction during non maskable interrupt servicing a NMIO interrupt afterwards cannot be acknowledged correctly Preliminary User s Manual U15839EE1VOUMOO 203 Chapter 8 Interrupt Exception Processing Function Figure 8 1 Example of Non Maskable Interrupt Request Acknowledgement Operation 1 2 a Multiple NMI requests generated at the same time NMIO and NMIWDT requests generated simultaneously Main routine NMIWDT servicing NMIO and NMIWDT gt requests generated simultaneously System reset 204 Preliminary User s Manual U15839EE1VOUMO00 C Figure 8 1 NMI being serviced hapter 8 Interrupt Exception Processing Function Example of Non Maskable Interrupt Request Acknowledgement Operation 2 2 b NMI request generated during NMI servicing NMI request generated during NMI servicing NMIO NMIO request generated during NMIO servicing Main routine NMIO servicing request NMIO request V
367. er Figure 7 29 DMA Transfer Forcible Termination Example 2 on page 197 shows a forcible termination of a block transfer operation of DMA channel 1 A transfer containing a new configuration is executed Figure 7 29 DMA Transfer Forcible Termination Example 2 DSAL1 DSAH1 DSAL1 DSAH1 DCHC1 DADC1 DDAL1 DDAH1 DDAL1 DDAH1 INIT1 bit 1 DCHC1 Set register Set register Set register Set register DMA Transfer Request CH1 EN1 bit 1 EN1 bit 0 EN1 bit gt 1 EN1 bit 0 TC1 bit 0 TC1 bit 0 TC1 bit 2 0 TC1 bit 1 DMA channel 1 transfer is forcibly DMA channel 1 terminated and the bus is released terminal count Remarks 1 Since the DSALn DSAHn DDALn DDAHn and DBCn registers are buffered registers the next transfer condition can be set even during a DMA transfer However a setting in the DADCn register is ignored refer to 7 3 Next Address Setting Function 2 n 0to3 7 12 DMA Transfer Completion 7 12 1 DMA transfer end interrupt When DMA transfer ends and the TCn bit of the DCHCn register is set a DMA transfer end interrupt INTDMAn is issued to the interrupt controller INTC Remark nz0to3 7 12 2 Terminal count output upon DMA transfer end The terminal count signal becomes active for one clock during the last DMA transfer cycle Preliminary User s Manual U15839EE1VOUMOO 197 Chapter 7 DMA Functions DMA Controller 7 13 Precautions 1 2 3 4 5 198 Memory boundary The
368. er gt cksEL2 32 fy Watch timer clock frequency BON interval times change accordingly if fy 4 MHz Preliminary User s Manual U15839EE1VOUMOO 353 Chapter 11 11 4 3 Operation as interval timer Watch Timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance The Interval Timer and the Watch Timer can used at the same time The interval time of the interval timer is smaller than the interval time of the Watch Timer every time It is a sub interval of the Watch Timer The interval time can be selected by the WTM4 through WTM6 bits of the watch timer mode control register WTM Table 11 4 Example for Interval Time of Interval Timer Interval Time fw foxseL2 1 4096 fw fcksgL1 fr 32 KHz WTSEL1 0 16 4 ms WTSEL1 1 32 8 ms 65 5 ms 131 ms 262 ms 524 ms 1048 ms Remarks 1 fy 4 MHz 2096 ms 2 WTSELO bit 1 CKC register gt fCKSEL2 fxxT 32 3 fw Watch timer clock frequency 4 interval times change accordingly if fy 4 MHz 354 Preliminary User s Manual U15839EE1VOUMOO Chapter 11 Watch Timer Figure 11 3 Operation Timing of Watch Timer Interval Timer 5 bit counter OH start Overflow Overflow Interrupt time of watch timer Note
369. er PMC6 ssssssssssseeseeneneeen eene 571 Port Function Register 7 P7 nnns 572 Port Function Register 7 8 P7 P8 essen eene 573 wende 574 Port 9 Mode Register PM9 nennen nennen 574 Port AH BABY iicet rene ime ie Ere erede ag a eens 575 Port AH Mode Register PMAH sssssseeeeneenerenen nnne nennen 576 Port AH Mode Control Register PMCAH sse 576 Pont CS POS sicat sedie d dee ee pe Rae cor 577 Port CS Mode Register PMCS 578 Port CS Mode Control Register PMCCS sse 578 POCO T estat erotismo retta das 579 Port CT Mode Register PMCT 580 Preliminary User s Manual U15839EE1VOUMOO Figure 16 37 Figure 16 38 Figure 16 39 Figure 16 40 Figure 17 1 Figure 17 2 Figure A 1 Port CT Mode Control Register PMCCT 580 Port GM ge E 581 Port CM Mode Register PMCM sss nennen nennen 582 Port CM Mode Control Register PMCOM sse 582 Reset signal ss seende Es ends 585 Reset cc 586 How to Read Instruc
370. er CO control register 0 TMCCOO R W x x 00H FFFF F608 Timer CO control register 1 TMCCO1 R W x 20H FFFF F609 Timer CO signal edge select register SESCO R W x x 00H TMGMO RW x x x 0000H FFFF F640 Timer mode register TMGMOL R W x x 00H FFFF F641 TMGMOH R W x x 00H TMGCMO R W x x x 0000H FFFF F642 Channel mode register TMGCMOL R W x x 00H FFFF F643 TMGCMOH RW x x 00H OCTLGO RW x x x 0000H FFFF F644 Output control register OCTLGOL R W x x 00H FFFF F645 OCTLGOH R W x x 00H FFFF F646 State register TMGSTO R x x 00H FFFF F648 Timer Count Register 0 TMGO00 R x 0000H FFFF F64A Timer Count Register 1 TMG01 R x 0000H FFFF F64C Capture Compare register 0 GCCO0 R W x 0000H FFFF F64E Capture Compare register 1 GCCO01 R W x 0000H FFFF F650 Capture Compare register 2 GCCO02 R W x 0000H FFFF F652 Capture Compare register 3 GCC03 R W x 0000H FFFF F654 Capture Compare register 4 GCC04 R W x 0000H FFFF F656 Capture Compare register 5 GCCO05 R W x 0000H TMGM1 RW x x x 0000H FFFF F680 Timer mode register TMGM1L R W x x 00H FFFF F681 TMGM1H R W x x 00H TMGCM1 RW x x x 0000H FFFF F682 Channel mode register TMGCM1L R W x x 00H FFFF F683 TMGCM1H RW x x 00H OCTLG1 RW x x x 0000H FFFF F684 Output control register OCTLG1L R W x x 00H FFFF F685 OCTLG1H R W x x 00H FFFF F686 State register TMGST1 R x x 00H FFFF F688 Timer Count Register 0 TMG10 R x 0000H 80 Preliminary User s Manual U15839EE1VOUMOO Cha
371. er and those values are immediately output Besides functioning as a port in control mode it also can operate as the serial interface UARTO CSI0 CS1 input output Notes 1 lf using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register P2 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Alternate Pin Name Remarks Block Type Serial interface UART1 CSIO CSI1 input out put Preliminary User s Manual U15839EE1VOUMOO 559 Chapter 16 Port Functions 2 Setting in input output mode and control mode Port 2 is set in input output mode using the port 1 mode register PM2 In control mode it is set using the port 2 mode control register PMC2 a Port 2 mode register PM2 This register can be read or written in 8 bit or 1 bit units Figure 16 11 Port 2 Mode Register PM2 0 Address At Reset 7 6 5 4 3 2 1 PM2n Specifies input output mode of P2n pin 7100 n 7 to 0 0 Output mode Output buffer on 1 Input mode Output buffer off 560 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions b Port 2 mode control register PMC2 This register can be read or wri
372. er can be read written in 8 bit 1 bit units Figure 7 11 DMA Trigger Factor Registers 1 DTFR1 7 6 5 4 3 2 1 0 Address Initial value DTFR1 DOFL IFC2 IFC1 IFCO FFFFF842H 00H E Bit Position Bit Name Function D RQNote DOFL Note pies Sets the interrupt source that serves as the DMA start factor Interrupt Source Peripheral Source INTIN1 CSIO INTIN2 CSI INTIN3 CSI2 INTIN4 UARTO Reception INTIN6 UART1 Reception INTIN8 ADC INTIN11 TMGO0 2 INTIN12 TMC 0 Note DRQ DOFL are set by hardware and reset by software Setting these bits by software is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR1 register set tings 2 An interrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor 180 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 2 10 DMA trigger factor register 2 DTFR2 This 8 bit registers is used to control the DMA transfer start trigger of DMA channel 2 through interrupt requests from on chip peripheral I O The interrupt requests set with these registers serve as DMA transfer start factors This register can be read written in 8 bit 1 bit units Figure 7 12 DMA Trigger Factor Registers 2 DTFR2 7 6 5 4
373. er details refer to chapter 14 2 5 Time stamp on page 441 Note The register address is calculated according to the following formula effective address PP_BASE address offset Remark 00 31 Preliminary User s Manual U15839EE1VOUMOO 481 Chapter 14 FCAN Interface Function Figure 14 30 Message Control Registers 00 to 31 M_CTRLOO to M CTRL31 2 2 Enables message buffer m related interrupts 0 Interrupts related to message buffer m disabled 1 Interrupts related to message buffer m enabled Remark f the message related interrupt is enabled an interrupt is generated for any of the following conditions Condition Related Interrupt Data frame or remote frame is transmitted from CANXTRX transmit message buffer Data frame or remote frame is received on receive message buffer CANxREC Remote frame is received on transmit message without auto answering set RMDEO 0 An interrupt is not generated even if enabled for any of the following con ditions Remote frame is received on a transmit message with auto answering mode RMDEO 1 Remote frame is transmitted from receive message buffer Indicates a message buffer overwrite 0 No overwriting occurred 1 Message buffer contents have been overwritten at least once since the DN flag of the M_STATm register has been cleared 0 Remark If the OVM bit of the CxCTRL register is cleared 0 a message buffer linked to
374. er reset the read input value is determined by the port pins 1 Operation in control mode Pn Alternate Pin Name Pin Name o Remarks Block Block Type x D to Port AH PAHO A23 to A16 Address bus MES CR Preliminary User s Manual U15839EE1VOUMOO 575 Chapter 16 Port Functions 2 Setting in input output mode and control mode Port AH is set in input output mode using the port AH mode register PMAH In control mode it is set using the port AH mode control register PMCAH a Port AH mode register PMAH This register can be read or written in 8 bit or 1 bit units Figure 16 30 Port AH Mode Register PMAH 0 Address At Reset 7 6 5 4 3 2 1 PMAHn Specifies input output mode of PAHn pin 7100 n 7 to 0 0 Output mode Output buffer on 1 Input mode Output buffer off b Port AH mode control register PMCAH This register can be read or written in 8 bit or 1 bit units Figure 16 31 Port AH Mode Control Register 3 2 1 0 Address At Reset 7 6 5 4 PMCAH PMCAH7 PMCAH6 5 PMCAH4 PMCAH2 PMCAH1 PMCAHO FFFFF042H FFH Bit Position Function Specifies operation mode of PMCAHn pin PMCAHn n 7 to 0 0 Input output port mode 1 A23 to A16 address output 576 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 11 Port CS Port CS is a 3 bit input output port in which input or output can be specif
375. er than AVgg even within the range of the absolute maximum ratings is input to a channel the converted value of the channel becomes undefined Moreover the values of the other channels may also be affected Noise counter measures To maintain 10 bit resolution attention must be paid to noise input to pin AVpp and pins ANIO to ANI11 Because the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 15 13 Analog Input Pin Handling on page 541 to reduce noise Figure 15 13 Analog Input Pin Handling If there is a possibility that noise equal to or higher than AV or equal to or lower than AVgg may enter clamp with a diode with a small V value 0 3 V or lower Reference voltage O T ANIO to ANI7 1 1 ANIO to ANI11 The analog input pins ANIO to ANI11 also function as input port pins P80 to P83 P70 to P77 When A D conversion is performed with any of pins ANIO to ANI11 selected do not execute a port input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion Preliminary User s Manual U
376. er there is a fetch access to a cacheable area set using the cache configuration register BHC 2 Operation on Instruction Cache Hit 1 Ona fetch access from memory the CPU outputs the instruction fetch request and the concerned address to the instruction cache 2 If a hit occurs due to the address existing in the instruction cache the instruction data is read from the instruction cache and passed through to the CPU Figure 6 6 Operation on Instruction Cache Hit Instruction Cache Instruction Cache Interface 160 Preliminary User s Manual U15839EE1VOUMOO Chapter6 Instruction Cache 3 Operation on Instruction Cache Miss 1 2 3 4 Caution On a fetch access from memory the CPU outputs the instruction fetch request and the concerned address to the instruction cache If an instruction cache miss occurs due to the address not existing in the instruction cache the fetch request and the address will be output from the instruction cache to the BCU The BCU then outputs the address to external memory via the VSB and refills the instruction cache with one line 4 words at the address to be read The instruction cache then transfers the data to be read among the 4 words of refill data to the CPU The miss penalty time when a miss occurs varies depending on such things as mem ory controller specifications for external memory and VSB bus cycle wait insertion time Figure 6 7 Operation on Instructi
377. er to prevent this invalid conversion result from adversely affecting the system The following are examples of software processing Use the average value of the results of multiple A D conversions as the A D conversion result Perform A D conversion multiple consecutive times and use conversion results with the exception of any abnormal conversion results that are obtained If an A D conversion result from which it is judged that an abnormality occurred in the system is obtained do not perform abnormality processing at once but perform it upon reconfirming the occurrence of an abnormality Be sure that voltages outside the range AVss to AVggr are not applied to pins being used as A D converter and input pins Preliminary User s Manual U15839EE1VOUMOO Chapter 15 A D Converter 15 3 Control Registers The following 2 types of registers are used to control A D converter A D converter mode register ADM Analog input channel setting register ADS 15 3 1 Register format of A D Converter Control Register Table 15 2 Register format of A D Converter Control Register SFR name Manipulable Bit Unit 1 bit 8 bits 16 bits A D converter mode register After Reset Analog input channel setting register A D conversion result register A D conversion result register A D conversion result register Preliminary User s Manual U15839EE1VOUMOO 527 Chapter 15 A D Converter
378. erence The calculated watch time can be corrected according to the actual sub clock deviation Remark 0 1 Figure 10 1 Block Diagram of Timer C on page 273 shows the block diagram of Timer C 272 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer Figure 10 1 Block Diagram of Timer C Clear amp start COUNT gt INTTMCO Sub Clock 1 16 bit I Calibration 1 I I 1 1 I 1 1 PSM CMODE 1 1 jJ 1 I 1 Edge Ticoo Detection Edge S Q um TOCO R af pe INTCCCO INTCCC1 Remark fporLk internal peripheral clock Preliminary User s Manual U15839EE1VOUMOO 273 Chapter 10 Timer 10 1 3 Basic configuration Table 10 1 Timer C Configuration List Generated Capture Timer Output Count lock Register Interrupt Signal Trigger S R INTTMCO fpcik 2 fpcik 4 84 16 INTCCCOO INTCCCOO Timer C fpcik 32 fpc 64 128 fpc 256 INTCCCO 1 INTCCCO 1 Remarks 1 fpc Internal peripheral clock 2 S R Set Reset 3 nz0 1 1 16 bit counter TMCO TMCO functions as a 16 bit free running timer or as an event counter for an external signal Besides being mainly used for cycle measurement Timer C can be used as pulse output TMCO is a 16 bit units read only register Figure 10 2 Timer C counter TMCO 15
379. ergo FE aen OCTLGOH OCTLGIH Bit Position Bit Name Function Fixes the TOGnm pin output level according to the setting of ALVGm bit 15 11 7 3 0 disable TOGnm to inactive level 1 enable TOGnm Specifies the active level of the TGOm pin output 0 Active level is 0 1 Active level is 1 Caution Don t write this bit before ENFGO or ENFG1 of TMGSTn is 0 so first clear TMGOE or TMG1E bit of the TMGMn register and check ENFGO ENFG1 bit before writing 14 10 6 2 Specifies Capture Compare mode selection 0 Capture mode if external edge is detected the INTCCGnm interrupt occurs the corresponding counter value is written to GCCnm 1 Compare mode if GCCnm matches with corresponding timebase the INTCCGnm interrupt occurs if SWFGm is set the PWM output mode is set 13 9 5 1 Caution Don t write this bit before POWER bit of TMGMHhn is 0 Remark 1 4 318 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 8 Timer Gn output control register Low OCTLGnL This register is the low byte of the OCTLGnH register This register can be read written in 8 bit or 1 bit units Figure 10 37 Timer Gn Output Control Register Low OCTLGnL 7 6 5 4 3 2 1 0 Address 1118 value The explanation of the bit 7 to 0 is the same as the bit 7 to 0 of the OCTLGn register 9 Timer Gn output control register High OCTLGnH This register is the low byte of the OCTLGnH register T
380. errupt pending register 2 C2INTP 00H xxxxn1026H CAN local interrupt pending register 3 C3INTP 00H xxxxn1028H CAN local interrupt pending register 4 C4INTP 00H xxxxn1040H CAN 1 address mask register LO C1MASKLO Undefined xxxxn1042H CAN 1 address mask register HO C1MASKHO Undefined xxxxn1044H address mask register L1 C1MASKL1 Undefined xxxxn1046H CAN1 address mask register H1 C1MASKH1 Undefined xxxxn1048H CAN1 address mask register L2 C1MASKL2 Undefined xxxxn104AH address mask register H2 C1MASKH2 Undefined xxxxn104CH CAN1 address mask register L3 C1MASKL3 Undefined xxxxn104EH CAN 1 address mask register H3 C1MASKH3 mK OK mK ox XX XX XxX XxX Xx Undefined xxxxn1050H control register Note 1 C1CTRL 0101H xxxxn1052H CAN definition register Note 1 C1DEF 2 2 xjxj x x x x x x x x 0000H xxxxn1054H 100 CAN1 information register C1LAST Preliminary User s Manual U15839EE1VOUMOO 00FFH Address xxxxn1056H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 17 18 Function Register Name CANI error counter register C1ERC Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value 0000H xxxxn1058H CANI interrupt
381. ers 0 to IMRO to 1 219 8 3 6 In service priority register 5 220 8 3 7 Maskable interrupt status flag 220 8 4 Noise Elimination 221 8 4 4 AnalogFilter lleeeeeeeeeel e eh 222 8 4 2 Interrupt Trigger Mode Selection 222 8 4 3 Interrupt Edge Detection Control Registers 223 8 5 Software 227 8 51 Operatiori zung aa a pede e Rond Rs e tab a Dee ds e tu x de das die 227 8 5 25 RESTO L me UBI E TUERI UE NP TR RE 228 8 5 3 Exception status flag EP 229 8 6 Exception Trap ie x rt EG 230 8 6 1 Illegal opcode definition 230 8 6 2 wee awed eS 232 8 7 Multiple Interrupt Processing 234 8 8 Interrupt Response 236 8 9 Periods in Which Interrupts Are Not Acknowledged 237 Chapter9 Clock 239 9 1 Featur
382. es lol ll lb Mee ee ee ee Dds 239 92 Configuration ecce ade ee aoe eee Re el eee ura etm ace ien 240 9 3 Control Registers lr ee ieee 241 9 3 1 Clock Control Register CKC 0 0 00 cee eee 241 9 3 2 Clock Generator Status Register 243 9 3 8 Watchdog Timer Clock Control Register 244 9 3 4 Processor Clock Control Register 245 9 3 5 Reset Source Monitor Register 5 247 9 3 6 SSCG Frequency Modulation Control Register SCFMC 248 9 3 7 SSCG Frequency Control Register 0 6 249 9 3 8 SSCG Frequency Control Register 1 6 1 250 9 4 Power Saving Functions 251 941 General s oux oid ec bU es BELA te ea Seat at he he ae ee 251 9 4 2 Power Save Modes Outline 253 9 4 8 Power Saving Mode lt 254 9 4 4 HALT mode aer b er asa yaaa 256 9 45 DCE Modes ose LL S SEIL 258 9 46 WATCH mode a a a ee tees 259 9 4 7 SUB WATCH mode 261 9 4 8 Software STOP 265 Preliminary U
383. est INTSRn is generated by the transfer of data to the RXBn Transmission shift register This is a shift register that converts the parallel data that was transferred from the transmission buffer register TXBn to serial data When one byte of data is transferred from the TXBn the shift register data is output from the TXDn pin This register cannot be directly manipulated Preliminary User s Manual U15839EE1VOUMOO 365 Chapter 13 Serial Interface Function 8 Transmission buffer registers TXBO TXB1 TXBn is an 8 bit buffer for transmit data A transmit operation is started by writing transmit data to TXBn The transmission completion interrupt request INTSTn is generated synchronized with the completion of transmission of one frame 9 Addition of transmission control parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXBn register according to the contents that were set in the ASIMn register Figure 13 1 Asynchronous Serial Interfaces Block Diagram N Internal bus Transmission buffer register n TXBn Reception buffer register n RXBn Asynchronous serial interface mode register n ASIMn Transmission shift register Reception RXD5no shift register TXD5n 0 4 lt Reception control parity check parity INST A A gt INTSR5n gt Parity gt Framing I
384. ests and exceptions are acknowledged regardless of this flag when a maskable interrupt is acknowledged the ID flag is automatically set to 1 by hardware The interrupt request generated during the acknowledgement disabled period ID 1 is acknowledged when the PIFn bit of PICn register is set to 1 and the ID flag is reset to 0 220 Preliminary User s Manual U15839EE1VOUMO00 Chapter 8 Interrupt Exception Processing Function 8 4 Noise Elimination Circuit V850E CA2 is provided with input filter for noise suppression for ports to P5 and on all interrupt and timer G timer C control inputs For peripheral interrupts programmable edge detection is available Inputs for Timer G are equipped with edge detection and need only noise suppression Figure 8 14 Port Interrupt Input Circuit P52 P53 P61 P62 P63 P64 Input Noise Filter Edge Detect INT CPU ESn1 ESnO Figure 8 15 Timer G Input Circuit P30 P35 P40 P45 P54 P55 gt Tinm TMC TMG Edge Detect INT CPU Noise Filter ESn1 ESnO Figure 8 16 NMI Input Circuit Noise Filter Edge Detect INT CPU Note Edge select circuit is different for NMI and INTPn NMI can only configured as rising or falling edge sensitive whereas INTPn can be triggered by rising falling or both edges Preliminary User s Manual U15839EE1VOUMOO 221 Chapter 8 Interrupt Exception Processing Function 8 4 1 Analog Filter The analog filte
385. et clear function on page 452 Figure 14 35 CAN 1 to 4 Definition Registers C1DEF to C4DEF 1 4 Address Initial 15 14 13 12 11 10 9 8 7 6 5 4 3 2 P vale CIDEF 0 0 0 0 0 0 0 0 DGM MOM ISSHT PBB BERRVALID WAKE OVR 1052H 0000H C2DEF 0 0 0 0 0 0 0 0 DG SSHT PBB BERR VALID WAKE OVR 1092H 0000H C3DEF 0 0 0 0 0 0 0 0 DG SSHT PBB BERR VALID WAKE OVR 10D2H 0000H C4DEF 0 0 0 0 0 0 0 0 DG SSHT PBB BERR VALID WAKE OVR 1112H 0000H Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST ST CL GADER BERR VALID BERR Mon CODEF ST ST ST ST ST ST ST_ ST_ CL_ CL_ CL_ CL_ CL_ OL CL_ CL_ 1092H DGM MOM SSHT PBB BERR VALID WAKE OVR DGM MOM SSHT BERR VALID WAKE OVR C3DEF ST ST ST ST ST ST ST_ ST_ CL_ CL_ CL_ CL_ CL_ CL CL_ COL 10D2H DGM MOM SSHT PBB OVR DGM MOM SSHT PBB BERR VALID WAKE OVR ST ST C4DEF BERR VALID 1112H Note The register address is calculated according to the following formula 492 effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 35 CAN 1 to 4 Definition Registers C1DEF to C4DEF 2 4 Read 1 2 Bit Position Bit Name Specifies the storage of receive message in diagnostic mode
386. et cancel register 11 SC STAT11 0000H xxxxn180H CAN message event pointer 120 M EVT120 Undefined xxxxn181H CAN message event pointer 121 M EVT121 Undefined xxxxn182H CAN message event pointer 122 M EVT122 Undefined xxxxn183H CAN message event pointer 123 M EVT123 Undefined xxxxn184H CAN message data length register 12 M DLC12 Undefined xxxxn185H CAN message control register 12 M CTRL12 Undefined xxxxn186H CAN message time stamp register 12 M TIME12 Undefined xxxxn188H CAN message data register 120 M DATA120 Undefined xxxxn189H CAN message data register 121 M DATA121 Undefined xxxxn18AH 90 CAN message data register 122 M DATA122 Preliminary User s Manual U15839EE1VOUMOO Undefined xxxxn18BH Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 7 18 Function Register Name CAN message data register 123 M DATA123 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn18CH CAN message data register 124 M DATA124 Undefined xxxxn18DH CAN message data register 125 M DATA125 Undefined xxxxn18EH CAN message data register 126 M DATA126 Undefined xxxxn18FH CAN message data register 127 M DATA127 Undefined xxxxn190H CAN message ID register L12 M I
387. eu Dee DP a ceases began ates Rege kd 106 PHOMBDB U EI tereti ie nextel wa e Ud 105 PES ta dte T e noa resa tee a D bat Pere eof 106 Sages Ai acted toate torta paced arated Gnd Guards acd eq o qaa 33 40 Pin l O CIICUITS is ted eek e Ra EORR ER ET RR EUER REN ut Saal ah 54 PIM Identification res eR vx HERI Sea dee MOT QE Ree Mh e Re RC Rs CRT on RR s eC ta 28 pipelihe Hf ad det dures recie SLT Ic Y numb b ed eet d ees 55 PLL synthesizer 5 PU UA EE E PLORA I OPES NE END PR A 239 PII T Sour rh ebbe ra olt on 557 560 563 565 567 570 574 576 578 580 582 hte ME tere as 558 561 563 565 568 571 576 578 580 582 Tu LE 340 Port d suu eto MEA 40 556 559 562 564 566 569 572 573 574 575 577 579 POIU2 cns eiecti dieit Sa uat deti ior Esa statist Sie ham Rd 41 ee we trn Nie d ste E S rete a 42 43 DE sce CH rM 44 PONE Os cS reb mtcr OUR m REC EU Ac Mu EI n tob 45 46 Port AH 47 del ES 48 Port Conflguratlon cia eed eG peu we eee a REPE Ee Red beer eve e eges 546 eU LR Itc 47 Port OT
388. executing the code in an uncacheable area tags are not cleared if the above processing is performed by code in a cacheable area When clearing way 0 and way 1 at the same time a Set the TCLRO and TCLR1 bits b Read the TCLRO and TCLR1 bits to confirm that these bits are cleared c Perform a and b above again When clearing way 0 and way 1 individually ete a Set the TCLRO bit b Read the TCLRO bit to confirm that this bit is cleared c Perform a and b above again d Set the TCLR1 bit e Read the TCLR1 bit to confirm that this bit is cleared f Perform d and e above again Note The setting can also be made in order of d e f a b c Way 0 shares the counter to clear tags with way 1 Therefore a clear tag operation must not be started set the TCLRO bit or TCLR1 bit of the ICC register even if the other way is currently being cleared When clearing the tags of way 0 and way 1 individually if tag clearing for either way is executed during tag clear execution for the other way TCLRO or TCLR1 1 the counter stops in the middle of tag clearing Consequently normal tag clearing cannot be performed because the counter switches to perform the other tag clear operation still indicating the value it had when stopped halfway Be sure to con firm that tag clearing for one way is completed TCLRO or TCLR1 0 before performing tag clearing for the other way When setting both bits at t
389. f a write operation is carried out to the ADM or the ADS register during conversion operation the conversion operation is aborted and restarts from the beginning 2 If the ADCS bit of the ADM register is cleared 0 during A D conversion operation the conversion operation is aborted and conversion operation is stopped Preliminary User s Manual U15839EE1VOUMOO 537 15 5 2 Operation modes Chapter 15 A D Converter The operation mode of the A D converter is the soft trigger mode One analog channel is selected from among ANIO to ANI11 with the analog input channel setting register ADS a Soft trigger mode In the soft trigger mode the A D converter converts one analog input specified in the ADS register The conversion result is stored in the ADCR ADCRL ADCRH register Figure 15 10 No write operation is made to ADM or ADS register during A D conversion operation ANIO Input A D conversion ADCR ADCRL ADCRH registers INTAD interrupt Data 1 Data 1 ANIO Conversion start ADCS bit of ADM register is set 1 Data 2 Data 2 ANIO Data 1 ANIO ADS3 to ADSO bits of ADS register are cleared 0 538 Data 3 Data 3 ANIO Preliminary User s Manual U15839EE1VOUMOO Data 4 Data 4 ANIO Data 2 ANIO Data 3 ANIO Data 4 ANIO Chapter 15 A D Converter Figure 15 11 ADCS bit is cleared 0 during A D conversion operation ANIO In
390. faces Serial clock control circuit fook 4 fecix 8 SCKOn fecu 16 Clock start stop control POUR Selector amp frork 32 clock phase control Interrupt 64 control INTCSIOn I CUI BRGO SCKOn O Transmission control Transmission data control y Control signal Initial transmit i data buffer register SO0n SOTBFn SOTBFLn Transmit data buffer register SOTBn SOTBLn 5 10 Receive data buffer register SIRBn SIRBLn Remark nz0to2 394 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 3 3 Control registers 1 Clocked serial interface mode registers CSIMO to CSIM2 The CSIMn register controls the CSlOn operation n 0 to 2 These registers can be read written in 8 bit or 1 bit units however bit O is read only Figure 13 22 Clocked Serial Interface Mode Registers CSIMO to CSIM2 7 6 3 2 1 0 Address value 5 4 CSIMO FFFF FDOOH CSIM CSIE TRMD CCL DIR CSIT AUTO 0 CSOT FFFFFD40H 00H CSIM2 CSIE TRMD CCL DIR AUTO 0 CSOT FFFFFD80H Enables disables CSIOn operation 0 Disable CSIOn operation 7 CSIE 1 Enable CSIOn operation The internal CSIOn circuit can be reset asynchronously by setting the CSIE bit to 0 For the SCKOn and SOOn pin output status when the CSIE bit 0 refer to 13 3 5 Output pins on page 422 Specifies transmission recepti
391. ffer off 570 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions b Port 6 mode control register PMC6 This register can be read or written in 8 bit or 1 bit units Figure 16 24 Port 6 Mode Control Register PMC6 3 2 1 0 Address At Reset 7 6 5 4 Specifies operation mode of P65 pin 0 Input output port mode 1 SCK2 input output mode Specifies operation mode of P65 pin 0 Input output port mode 1 SO2 output mode Specifies operation mode of P65 pin 0 Input output port mode 1 SI2 input mode Specifies operation mode of P64 pin 0 Input output port mode 1 External interrupt request INTP3 input mode Specifies operation mode of P63 pin 0 Input output port mode 1 External interrupt request INTP2 input mode Specifies operation mode of P62 pin 0 Input output port mode 1 External interrupt request INTP1 input mode Specifies operation mode of P61 pin 0 Input output port mode 1 External interrupt request INTPO input mode Specifies operation mode of P60 pin 0 Input output port mode 1 NMI interrupt input mode Remark To avoid unintended disable of the NMI the bit PMC60 can only be set 1 Once the bit PMC60 is set 1 clearing that bit PMC60 0 is not possible The bit PMC60 is cleared by the generation of a RESET Preliminary User s Manual U15839EE1VOUMOO 571 Chapter 16 Port Functions 16 3 7 Port 7 Port 7 is an 8 bit input port which is
392. form access only in the idle state CSOT bit of CSIMn register 0 If the SOTBLn register is accessed during data transfer the data cannot be guaranteed Preliminary User s Manual U15839EE1VOUMOO 403 Chapter 13 Serial Interface Function 9 Clocked serial interface initial transmission buffer registers SOTBFO to SOTBF2 The SOTBFn register is a 16 bit buffer register that stores initial transmission data in the repeat transfer mode n 0 to 2 The transmission operation is not started even if data is written to the SOTBFn register These registers can be read written in 16 bit units Figure 13 30 Clocked Serial Interface Initial Transmission Buffer Registers to SOTBF2 Initial value SOTBFO FFFF FD08H 0000H 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Address SOTBFO SOTBF15 SOTBF14 SOTBF13 SOTBFI2 SOTBETI SOTBF10 SOTBF9 SOTBFB SOTBF7 ISOTEFS SOTBFS SOTBFI SOTBF3 SOTBF2 SOTBFI SOTBF1 SOTBFI4 SOTBF3 SOTBF12 SOTEFI FFFF FD48H 0000H SOTBF2 SOTBFIS SOTBFI4 SOTBF13SOTBF12 SOTBF11 FFFF FD88H 0000H SOTBF15 to n ANE 15100 SOTBFO Stores initial transmission data in repeat transfer mode Caution Access the SOTBFn register only when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOT bit of CSIMn register O If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 404 Preliminary User s Manual U15839EE
393. fter the STOP mode has been released the SSCG and PLL can be switched on any software again once However the start up of the SSCG and PLL cause always a certain delay of some Milliseconds During this time the clock operates but the CPU operation is suspended due to clock security reasons If it is required to have a fast response when waking up from STOP mode the SSCG and PLL should not be re enabled after waking up as this causes again the delay In this case time relevant reactions of the CPU should be done first before re enabling the PLL Preliminary User s Manual U15839EE1VOUMOO 267 Chapter 9 Clock Generator 9 5 Register Description 9 5 1 Power Save Control Register PSC This is an 8 bit register that controls the power save mode Data can be written only in a sequence of specific instructions so that its contents are not easily rewritten in case of program hang up This register can be read or written in 8 bit or 1 bit units Figure 9 15 Power Save Control Register PSC 7 6 5 0 Address Initial value 4 3 2 1 Bit name Function Intsignal release mask 0 Permits NMI1 requests 1 Prohibits NMIO requests Intsignal release mask 0 Permits NMIO requests 1 Prohibits NMIO requests Intsignal release mask 0 Release by maskable interrupt 1 Don t release by maskable interrupt Power save mode specification 0 IDLE WATCH STOP mode are released 1 IDLE WATCH STOP mode are entered N
394. g peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register PCM is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Port CM PCMO WAIT Wait insertion signal input E Caution In case that the port pin PCMO operates as a control signal for the external memory interface WAIT it is recommended to plug in an external pull up resistor to that pin Preliminary User s Manual U15839EE1VOUMOO 581 Chapter 16 Port Functions 2 Setting in input output mode and control mode Port CM is set in input output mode using the port CM mode register PMCM In control mode it is set using the port CM mode control register PMCM a Port CM mode register PMCM This register can be read or written in 8 bit or 1 bit units Figure 16 39 Port CM Mode Register PMCM Address At Reset Specifies input output mode of PCMO pin PMCMO 0 Output mode Output buffer on 1 Input mode Output buffer off b Port mode control register PMCCM This register can be read or written in 8 bit or 1 bit units Figure 16 40 Port CM Mode Control Register PMCCM Address At Reset Bit Position BitName Name Function LI operation mode of PMCCMO pin PMCCMO 0 I
395. g the Power bit to 1 when starting transfer Set the Power bit to 0 after setting the bit to 0 when stopping transfer 6 TXE To initialize the transfer unit clear 0 the bit and after letting 2 Clock cycles base clock elapse set 1 the TXE bit again If the TXE bit is not set again initialization may not be successful For details about the base clock refer to 13 2 6 Dedicated baud rate generators BRG of UART5n n 0 1 on page 384 Preliminary User s Manual U15839EE1VOUMOO 367 Chapter 13 Serial Interface Function Figure 13 2 Asynchronous Serial Interface Mode Registers ASIMO ASIM1 2 3 Enables disables reception 0 Disable reception Perform synchronous reset of reception circuit 1 Enable reception Cautions 1 Set the RXE bit to 1 after setting the Power bit to 1 when starting transfer Set the Power bit to 0 after setting the RXE bit to 0 when stopping transfer To initialize the reception unit status clear 0 the RXE bit and after letting 2 Clock cycles base clock elapse set 1 the RXE bit again If the RXE bit is not set again initialization may not be successful For details about the base clock refer to 13 2 6 Dedicated baud rate generators BRG of UART5n n 0 1 on page 384 Controls parity bit PSO Transmit Operation Receive Operation Don t output parity bit Receive with no parity Output 0 parity Receive as 0 parity Output odd parity Judge as odd pa
396. generated When 7 bits is specified for the data length bits 6 to 0 of the RXBn register are transferred for the receive data and the MSB bit 7 is always 0 However if an overrun error OVE occurs the receive data at that time is not transferred to the RXBn register Except when a reset is input the RXBn register becomes even when Power bit 0 in the ASIMn register This register is read only in 8 bit or 1 bit units n 0 1 Figure 13 5 Reception Buffer Registers RXBO RXB1 Initial 7 6 5 4 3 2 1 0 Address value 7100 RXB7 to Stores receive data RXBO 0 can be read for RXB7 when 7 bit or character data is received 372 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 5 Transmission buffer registers TXBO TXB1 The TXBn register is an 8 bit buffer register for setting transmit data When transmission is enabled bit 1 in the ASIMn register the transmit operation is started by writing data to TXBn register When transmission is disabled bit 0 in the ASIMn register even if data is written to TXBn register the value is ignored The TXBn register data is transferred to the transmission shift register and a transmission completion interrupt request INTSTn is generated synchronized with the completion of the transmission of one frame from the transmission shift register For information about the timing for generating this interrupt request refer to 13 2 5
397. generated within one clock after the end of a sin gle transfer DMA channels 0 and 3 are used for the single transfer example When two DMA transfer request signals are activated at the same time the two DMA transfers are performed alternately Figure 7 18 Single Transfer Example 3 DMA Transfer Request Transfer Request CH3 J DMA channel 3 DMA channel 0 terminal count terminal count Figure 7 19 Single Transfer Example 4 on page 188 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within one clock after the end of a sin gle transfer DMA channels 0 2 and 3 are used for this single transfer example When three or more DMA transfer request signals are activated at the same time always the two highest priority DMA trans fers are performed alternately Figure 7 19 Single Transfer Example 4 DMA Transfer Request CHO Transfer Request 2 J wo DMA Transfer Request CH3 Note Note Note Note Note Note Note Note Note DMA channel 0 DMA channel 3 terminal count terminal count DMA channel 2 terminal count Note The bus is always released 188 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 5 2 Single step transfer mode In single step transfer mode the DMAC releases the bus at each byte halfword word transfer Once a DMA transfer request signal is received transfer is perf
398. gister 056 M DATA056 Undefined XxxxnOAFH CAN message data register 057 M_DATA057 X XXIX XxX XxX XxX x Undefined xxxxnOBOH CAN message ID register L05 M IDLO5 Undefined xxxxnOB2H CAN message ID register H05 M IDHO5 Undefined xxxxnOB4H CAN message configuration register 05 M CONFO05 Undefined xxxxnOB5H CAN message status register 05 M STATO5 Undefined xxxxnOB6H CAN status set cancel register 05 SC STATOS 0000H XxxxnOCOH CAN message event pointer 060 M EVTO60 Undefined xxxxnOC1H CAN message event pointer 061 M EVTO61 Undefined xxxxnOC2H CAN message event pointer 062 M_EVT062 Undefined XxxxnOC3H CAN message event pointer 063 Preliminary User s Manual U15839EE1VOUMOO M EVTO063 Undefined 87 Address xxxxnOCAH Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 4 18 Function Register Name CAN message data length register 06 M DLCO06 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn0OC5H CAN message control register 06 M DTRLO6 Undefined xxxxnOC6H CAN message time stamp register 06 M TIMEO6 Undefined Xxxxn0C8H CAN message data register 060 M DATAO60 Undefined xxxxnOC9H CAN message data register 061 M DATAO61 Undefined XxxxnOCAH
399. global time system is integrated in the FCAN system That functional block is supplied by the global time system clock fers which is derived from The time system prescaler scales fats and is controlled by the register The time base of the global time system is realised by the 16 bit free running counter the CAN global time system counter CGTSC Time stamp information is captured from the CGTSC counter 438 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 2 4 Interrupt handling The very high number of interrupt events generated by the FCAN system does not allow to assign an independent interrupt vector of the V850E CA2 to each event Therefore the interrupt request signals are bundled into groups and the grouped interrupt request signal is then assigned to an independent interrupt vector The concept of interrupt request signal bundling leads to the fact that all interrupt request signals of the FCAN system are designed as interrupt pending signals Interrupt pending signals are not automati cally treated by an interrupt service routine like interrupt request signals with an unambiguous interrupt vector Rather on occurrence of the interrupt event the interrupt signal is generated and latched In the interrupt service routine the software must analyse which particular interrupt event caused the interrupt request by scanning the interrupt pending flags of a bundled interrupt signal group After
400. grammable 131 Preliminary Users Manual U15839EE1VOUMOO 7 4 8 2 External wait function 133 4 8 3 Relationship between programmable wait and external wait 133 4 9 Idle State Insertion 134 4 10 Bus Priority Order eee Wwe 135 4 11 Boundary Operation lt 136 4 11 1 Program 136 411 2 Data Spaces eyes a a E Se eee eS 136 Chapter5 Memory Access Control Function 137 5 1 SRAM External ROM External I O Interface 137 SPE Fees n 137 5 1 2 lt 138 5 1 3 SRAM external ROM external I O 5 139 5 2 ROM Controller 145 5 231 FEAS o eet eoe Et ee I PI y da teh donb E E S E CIR RRE 145 5 2 2 ROM lt 146 5 2 3 On page off page 147 5 2 4 Page ROM configuration register 149 5 2 5
401. he CMS1 and CMSO bits of the TMCCO 1 register are set to 0 the register operates as a capture register A capture operation that captures and holds the TMCO count value asynchronously relative to the count clock fcouwr is performed synchronized with an external trigger An interrupt request INTCCCOO or INTCCCO 1 n 0 1 is generated by TICnO or TICn1 signal input and is used as an external trigger capture trigger The valid edge of the capture trigger is set by valid edge selection register SESCO The TMCO count value during counting is captured and held in the capture register synchronized with that capture trigger signal The capture register value is held until the next capture trigger is generated a Example capture for pulse cycle measurement If one of the edges is set as the capture trigger the input pulse cycle can be measured Figure 10 10 Timing of capture for pulse cycle measurement rising edge TMCO CE CCCO0 Capture register TICO1 Capture trigger Capture trigger Remarks 1 When the CE bit is 0 no capture operation is performed even if INTCCCO 1 is input 2 Valid edge of TICO1 Rising edge Preliminary User s Manual U15839EE1VOUMOO 285 Chapter 10 Timer b Example capture for pulse cycle measurement If both the rising and falling edges are set as capture triggers the input pulse width from an external source can be measured Figure 10 11 Timing of capture for puls
402. he GCC5 register is not FFFFH Remark The setting of the CCSGm bit in combination with the SWFGm bit sets the mode for the tim ing of the actualization of new compare values In compare mode the new compare value will be immediately active n PWM mode the new compare value will be active first after the next overflow or match amp clear of the assigned counter TMGO TMG1 Preliminary User s Manual U15839EE1VOUMOO 323 Chapter 10 Timer 10 3 7 Operation in Free run mode This operation mode is the standard mode for Timer Gn operations In this mode the 2 counter TMGnO and TMGn1 are counting up from 0000H to FFFFH generates an overflow and start again In the match and clear mode which is described in Chapter 10 3 8 on page 335 the fixed assigned register GCCnO GCCn5 is used to reduce the bit size of the counter TMGn 1 1 Capture operation free run Basic settings m 1 to 4 CCSGn0 CCSGn5 SWFGm disable TOGnm free run mode assign counter for GCCnm 0 TMGnO 1 TMGn1 TBGm 324 Preliminary User s Manual U15839EE1VOUMO00 Chapter 10 Timer a Example Pulse width or period measurement of the TIGny input signal free run Capture setting method 1 When using one of the TOGn1 to TOGn4 pins select the corresponding counter with the TBGm bit When TIGnO is used the corresponding counter is TMGnO When TIGn5 is used the corresponding counter is TMGn1 2 Select a count
403. he SOTBn register when the transfer reservation period is over the following occurs In case of contention between transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and normal data transfer cannot be performed Figure 13 40 Transfer Request Clear and Register Access Contention Transfer reservation period SCKOn input output INTCSIn interrupt rq_clr Reg_R W Remarks 1 0 2 420 2 rq Internal signal Transfer request clear signal Reg Whc Internal signal This signal indicates that the transmit data buffer register SOTBn SOTBL n has been written Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function In case of contention between interrupt request and register access Since continuous transfer has stopped once executed as a new repeat transfer In the slave mode a bit phase error transfer error results refer to Figure 13 41 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 13 41 Interrupt Request and Register Access Contention Transfer reservation period SCKOn input output 0 1 2 3 4 INTCSIn interrupt ra cir Reg R W Remarks 1 n 0to2 2 Internal signal Transfer request clear signal Reg Whc Internal signal Thi
404. he message is detected as valid i e if no error was detected until the last but one bit of the end of frame EOF was received The selection of the two trigger options is controlled by the TMR bit in the CxCTRL register x 1 to 2 for the derivative uPD703128 A x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 The capture value itself is stored in the M TIMEm register m 00 to 31 of the message buffer for which the received message has been accepted Remark The value of M TIMEm register is undefined when an error occurs while receiving the mes sage Figure 14 5 Time Stamp Capturing at Message Reception Time stamp reception at SOF SOF Message ACK EOF message valid Message Buffer CAN Global Time System Counter capture temporary buffer copy TE Time stamp reception at message EOF SOF Message ACK EOF message valid MAC Message Buffer CAN Global Time System Counter capture and copy M_TIME Preliminary User s Manual U15839EE1VOUMOO 441 Chapter 14 FCAN Interface Function For the time stamp capturing at message transmission the SOF signal of the transmit message is used as the event trigger see Figure 14 6 The captured value from the CGTSC counter is written into particular data bytes of the transmit mes sage s data field Table 14 9 shows the s
405. he next start bit is extended two clocks of basic clock Clock longer than normal However on the reception side the transfer result is not affected since the timing is initialized by the detection of the start bit Figure 13 20 Transfer Rate During Continuous Transmission Start bit of 1 data frame ar second byte Start bit Parity bit Stop bit Start bit a lt FL FL FL Flsp FL FL Representing the 1 bit data length by FL the stop bit length by FLstp and the basic clock frequency by fork fields the following equation FLstp FL 2 foy Therefore the transfer rate during continuous transmission is as follows Transfer rate 11 x FL 2 fork 13 2 7 Precautions When the supply of clocks to UART5n n 0 1 is stopped for example IDLE or STOP mode operation stops with each register retaining the value it had immediately before the supply of clocks was stopped The TXD5n pin output also holds and outputs the value it had immediately before the supply of clocks was stopped However operation is not guaranteed after the supply of clocks is restarted Therefore after the supply of clocks is restarted the circuits should be initialized by setting Power bit 0 RXE bit 0 and bit 0 in the ASIMn register Preliminary User s Manual U15839EE1VOUMOO 391 Chapter 13 Serial Interface Function 13 3 Clocked Serial Interfaces CSIOO to CSIO2 13 3 1 Features e High speed transfer Maximu
406. he same time as shown below normal tag clearing will be performed properly Be sure not to perform other processing simultaneously with tag clearing before reading the TCLRO and TCLR1 bits of the ICC register and confirming that these bits are cleared 0 Preliminary Users Manual U15839EE1VOUMOO 163 Chapter 6 Instruction Cache Sample Coding 1 mov 0x3 r2 c2 LOPO 3 Id h ICC rO r1 lt 4 gt cmp rO r1 lt 5 gt bnz LOPO lt 6 gt st h r2 ICC rO lt 7 gt LOP1 First TAG clear lt 8 gt Id h ICC rO r1 9 cmp rO r1 10 bnz LOP1 lt 11 gt st h r2 ICC rO 12 LOP2 Second TAG clear 13 Id h ICC rO r1 lt 14 gt cmp rO r1 lt 15 gt bnz LOP2 Remark The clock count required for a tag clear operation is 256 clocks To actually clear tags the required clock count is doubled because a tag clear operation is performed twice sequen tially Note During reset active the value of the bits TCLRO and TCLR1 becomes set 1 and tag initializa tion begins automatically Upon completion of tag initialization the value of these bits changes to 0 164 Preliminary User s Manual U15839EE1VOUMOO Chapter6 Instruction Cache 5 Autofill Function Way 0 only The autofill function automatically fills instructions for one way Once autofilled a way is automati cally locked and write is disabled and it operates the same as a ROM that is accessible in one cycle When th
407. his register can be read written in 8 bit or 1 bit units Figure 10 38 Timer Gn Output Control Register High OCTLGnH 7 6 5 4 3 2 1 0 Address ital value The explanation of the bit 7 to 0 is the same as the bit 15 to 8 of the OCTLGn register Preliminary User s Manual U15839EE1VOUMOO 319 Chapter 10 Timer 10 Time base status register TMGSTn The TMGSTn register indicates the status of TMGnO and TMGn1 For the CCFGy bit see Chapter 10 3 7 Operation in Free run mode on page 324 This register can be read in 8 bit or 1 bit units Figure 10 39 Timer Gn Status Register TMGSTn 7 6 5 4 3 2 1 0 Address ital value Bit Position Bit Name Function Indicates TMGnO or TMGn1 overflow status 0 No overflow 1 Overflow Caution The CCFGy bit is set if a TMGnO TMGn1 overflow occurs This flag is only updated if the corresponding GCCy register was read so first read the GCCy register and then read this flag if necessary Indicates TMGn1 TMGn0 operation 0 indicates operation stopped 1 indicates operation Remarks 1 0 5 2 0 1 320 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 3 5 Output delay operation When the OLDE bit is set different delays of count clock period are added to the TOGnm pins Output pin delay 1 fcouNT The figure below shows the timing for the case where the count clock is set to 2 However OFFFH is set in GCCn0
408. his shows the degree to which the conversion characteristics deviate from the ideal linear rela tionship It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero scale error and full scale error are O Figure 15 18 Nonlinearity Error Ideal line Digital output Analog input 544 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 1 Features Input Output ports 5 V 51 Input ports 5 V 12 Input Output ports 3 3 V 15 Ports alternate as input output pins of other peripheral functions Input or output can be specified in bit units Preliminary User s Manual U15839EE1VOUMOO 545 Chapter 16 Port Functions 16 2 Port Configuration The V850E CA2 incorporates a total of 78 input output ports 12 ports are input only 15 input output ports have 3 3 V power The ports are named ports P1 through P9 and PAH PCM PCT and PCS The configuration is shown below Figure 16 1 Port Configuration Port 1 Port 7 Port 2 Port 8 Port 3 Port 9 Port 4 Port PAH Port 5 Port PCS Port 6 Port PCT Port POM 546 Preliminary User s Manual U15839EE1VOUMOO 1 Functions of each port Chapter 16 Port Functions The V850E CA2 has the ports shown below Any port can operate in 8 or 1 bit units and can provide a variety of controls Moreover besides its function as a port some have functions as
409. hows instruction mnemonics This column shows instruction operands refer to Table B 1 This column shows instruction codes opcode in binary format 32 bit instructions are displayed in 2 lines refer to Table B 2 This column shows instruction operations refer to Table B 3 This column shows flag statuses refer to Table B 4 Instruction Mnemonic Operand Operation Group Preliminary User s Manual U15839EE1VOUMOO 589 Appendix A List of Instruction Sets Table A 1 Symbols in Operand Description Description reg1 General register rO to r31 Used as source register reg2 General register rO to r31 Mainly used as destination register ep Element pointer r30 bit 3 3 bit data for bit number specification immx x bit immediate data dispx x bit displacement System register number vector 5 bit data that specifies trap vector number 00H to 1FH cccc 4 bit data that indicates condition code Table A 2 Symbols Used for Op Code Symbol Description 1 bit data of code that specifies reg1 or regID 1 bit data of code that specifies reg2 1 bit data of displacement 1 bit data of immediate data 4 bit data that indicates condition code 3 bit data that specifies bit number 590 Preliminary User s Manual U15839EE1VOUMOO Appendix A List of Instruction Sets Table A 3 Symbols Used for Operation Description Description
410. i ad reed elven ee 137 External signal cycle measurement 271 External wait function lisse hn ah 133 F FCAN Baud rate setting llli 509 Data new 446 447 451 464 475 477 481 482 489 512 Priority storage i e ee e eec e Rege Eee menda dex EU x iov eer dee oid oerte qe EUER d wh 446 Timestamp io zer vo Rs NER Ee ORI Bede oie Blah TRE UI E RA PIER S ane ale A 441 442 PERG TEM EET 58 dh a Ease SRL pv NO Mt OM 58 fixed time intervals asiu hh mne 353 Framing OMOT tino rete ater ERR 364 TOS TUM enu Duca de aont Vete pole Dea edo Deb aote D NOR QU e was 329 331 testun MOUS is IE bRPEHR EH RIA RE Rig E pike pee rs Se eg pees ui 322 free running timer 0 0000 cette nnn 274 275 PUIFGUDIOX Pr 364 375 full duplex communication sseeeeeee eae 363 Fullscale Erfor 2 EAS LEE dee ee ae ee Boa Bidar eet Base 544 Functions Of each POM ERRARE a een eed ned ne 547 Functions of each port pin on reset and registers that set port or control mode 548 G GOCGnO0 311 GG OD oie drove tec ate ord EN Een tdt teat 311 312 General registers 332 d vare Roe fe e
411. icates a receive completion interrupt of CAN module x CxINT1 bit of CGINTP reg CCINTPH ister 7 4 1 0 No Interrupt pending CCINTPL 1 Interrupt pending 0 Indicates a transmit completion interrupt of CAN module x CxINTO bit of CGINTP reg CCINTPH ister 6 3 0 CANXTRX 0 No Interrupt pending CCINTPL 1 Interrupt pending 15 14 131211109 8 7 6 5 4 3 2 1 15 Indicates an interrupt of the CAN bridge GINT7 bit of CGINTP register Nete 4 CCINTPL INTACT 0 No Interrupt pending 1 Interrupt pending Indicates a MAC interrupt OR function of GINT3 to GINT1 bits of CGINTP register INTMAC 0 No Interrupt pending 1 Interrupt pending 14 CCINTPL Notes 1 The register address is calculated according to the following formula effective address PP_BASE address offset x 1 to 2 for the derivative uPD703128 x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 Due to the fact that there s no bridge functionality implemented in the V850E CA2 device this bit isn t relevant for the application Remark The CCINTP register is a read only register which summarizes the CAN interrupt pending signals Therefore it cannot be used to clear the interrupt pending signals after servicing The interrupt pending signals must be cleared in the dedicated interrupt pending registers CGINTP C1INTP C2INTP and C3INTP Preliminary User s Manual U15839EE1VOUMOO 467 Chapter 14 FCAN Interface F
412. ication software must handle the remote frame in the expected way 2 RMDEO RMDE1 bits as well as ATS bit of M CTRLm register are set to 0 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function b Reception in a transmit message buffer When the FCAN system searches for the corresponding message buffer after reception of a remote frame and finds a message buffer with a matching identifier which is defined for transmis sion the content of the remote frame is not stored but programmable reactions are launched Accepting a remote frame for a transmit message buffer does not change the content of the trans mit message buffer except the DN flag of the M STATm register depending on the setting of the RMDEO RMDR1 and RTR bits of the M CTRLm register refer to Table 14 15 The remote frame reception in a transmit message buffer causes a reaction according to the set ting of the RMDEO RMDR1 bits and the RTR bit of the M CTRLm register The following reac tions are programmable Generation of an auto answer i e TRQ bit of the transmit message buffer is automatically set without any CPU interaction Signalling the remote frame reception by updating the DN flag in the transmit message buffer No reaction at all Table 14 15 shows the detailed handling reaction upon the reception of a remote frame for a transmit message buffer depending on the settings of RMDEO RMDE1 and RTR flags Table 14 15 Remote
413. ied 2 Fora setting of the DBCn register in which the transfer count cannot be divided by 4 the sections that can be line transferred are line transferred first then the remaining indivisible sections are transferred as single transfer Remark nz0to3 174 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 2 4 DMA addressing control registers 0 to 3 DADCO to DADC3 These 16 bit registers are used to control the DMA transfer modes for DMA channel n They can be read written in 16 bit units Figure 7 6 DMA Addressing Control Registers 0 to 3 DADCO to DADC3 1 2 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value wooo v 7 remo m 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value Sos Tv 3 T spes om we oO eos um 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value 3 T9 s pes om we Tn eon um 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DADC3 FFFFFOD6H 0000H Bit Position Bit Name Function 15 14 DS1 DSO Sets the transfer data size for DMA transfer Transfer Data Size 8 bits 16 bits 32 bits Setting prohibited For the peripheral I O and programmable peripheral I O registers ensure the transfer size matches the access size 7 6 SAD1 Sets the count direction of the source address for DMA channel n n 0 to 3 SAD
414. ied in 1 bit units After reset port PCSO operates as a chip select output pin CSO The port pins PCS3 and PCS4 operate as port input after reset Each port bit can be independently configured to port input port output or peripheral functionNete 1 This register can be read in 1 bit and 8 bit units Figure 16 32 Port CS PCS Address At Reset 7 6 5 4 3 2 1 0 PCSn n 4 3 0 Input output port Remark Input Mode When the PCS register is read the pin levels at that time are read Writing to the PCS register writes the values to that register This does not affect the input pins In Output Mode When the PCS register is read the values of PCS are read Writing to the PCS register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as the chip select signal output when memory is accesses externally Notes 1 If using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register PCS is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Alternate Pin Name Remarks Block Type Chip select signal output Port AH Chip select signal output
415. igure 14 27 Message Set Clear Status Registers 00 to 31 SC to SC STAT31 Address Initial 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OttsetNote value ST IST IST ST CL CL CL CL_ ERQ DN TRQ RDY ERQ DN RDY 816H m x 20H SC STAT Status of ERQ bit ERQ bit is cleared 0 ERQ bit is set 1 Others No change in ERQ bit value Sets clears the DN bit of the M STATm register ST DN CL DN Status of DN bit 0 1 DN bit is cleared 0 1 0 DN bit is set 1 Others No change in DN bit value Sets clears the TRQ bit of the M STATm register ST TRQ CL TRQ Status of TRQ bit 0 1 TRQ bit is cleared 0 1 0 TRQ bit is set 1 Others No change in TRQ bit value Sets clears the RDY bit of the M STATm register Status of RDY bit RDY bit is cleared 0 RDY bit is set 1 Others No change in RDY bit value Note The register address is calculated according to the following formula effective address PP BASE address offset Remark 00 to 31 Preliminary User s Manual U15839EE1VOUMOO 477 Chapter 14 FCAN Interface Function 5 Message data registers m0 to m7 M DATAmO to M DATAm7 m 00 to 31 The M DATAmO to M_DATAm7 registers are used to hold the receive or transmit data of the corre sponding message m m 00 to 31 These registers can be read written in 8 bit units Figure 14 28 Message Data Registers m
416. il the set value is transferred to internal units When a count operation begins the count cycle from 0000H to 0001H differs from subsequent count cycles To initialize the TMDn register status and start counting again clear the CE bit to 0 and then set the CE bit to 1 after an interval of fpc 2 clocks has elapsed Up to fpc 2 clocks are required until the value that was set in the CMDn register is transferred to internal units When writing continuously to the CMDn register be sure to secure a time interval of at least fpc_ 2 clocks The CMDn register can be overwritten only once during a timer counter operation from 0000H until an INTTMDn interrupt is generated due to a match of the TMDn register and CMDn register If this cannot be secured make sure that the CMDn register is not overwritten during a timer counter operation The count clock must not be changed during a timer operation If the clock selection by CS2 to CSO bits is going to be changed it should be overwritten after the CE bit is cleared to 0 If the count clock is changed during a timer operation operation cannot be guaranteed An INTTMDn interrupt will be generated after an overflow if a value less than the counter value is written in the CMDn register during TMDn register operation Remark n 0 1 Preliminary User s Manual U15839EE1VOUMOO 305 Chapter 10 Timer 10 3 Timer G 2 x 16 bit multi purpose timer of Timer G are implemented Timer GO
417. ime the DMAC clears the ENn bit of the DCHOn register of all channels and the DMA transfer disabled state is entered An NMI request can then be acknowledged after the DMA transfer executed during NMI input is termi nated In the single step transfer mode block transfer mode or line transfer mode the DMA transfer request is held in the DMAC If the ENn bit is set the DMA transfer restarts from the point where it was interrupted In the single transfer mode if the ENn bit is set the next DMA transfer request is acknowledged and DMA transfer begins Figure 7 27 Example of Forcible Interruption of DMA Transfer NMI input Forcible Transfer Forcible D interruption restart Ie interruption DMA transfer DMA transfer stop transfer DMA transfer stop DDIS register DRST register 01H ENO bit of DCHCO register Caution forcibly interrupt transfer and stop the next transfer from occurring the NMI signal must be made active before the end of the DMA transfer currently under exe cution Moreover although it is possible to restart DMA transfer following an inter ruption this transfer cannot be executed under new settings new conditions Execute DMA transfer under new settings either after the end of the current transfer or after transfer has been forcibly terminated by setting the INITn bit of the DCHCn register Remark nz0to3 Preliminary User s Manual U15839EE1VOUMOO 195 Chapter 7 D
418. iming when both edges of TIGnO are valid free run JULIUS pU ee En Of GL el epo PS dar A A Count start Clear du pe INTCCGnO INTTMGnO CCFGnO gt gt 22 No overflow Overflow No overflow Remark The figure above shows an image In actual circuitry 3 to 4 periods of the count up signal are required from the input of a waveform to TIGnO until a capture interrupt is output See Chapter 10 1 3 Basic configuration 1 16 bit counter TMCO b Synchronous reset on page 275 326 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer b Timing of capture trigger edge detection The Tin inputs are fitted with an edge detection and noise elimination circuit Because of this circuit 3 periods to less than 4 periods of the count clock are required from edge input until an interrupt signal is output and capture operation is performed The timing chart is shown below Basic settings x 0 1 and y 0 to 5 Remark Count clock fpc 4 detection of both edges Figure 10 42 Timing of capture trigger edge detection free run _ iom c pp up TMGno TMGn1 C E Ko Udo Se Ge Ba TIGnO i ka SS INTCCGny GCCny t4 I 3 count clock periods Preliminary User s Manual U15839EE
419. ined xxxxn3B6H CAN status set cancel register 29 SC STAT29 0000H xxxxn3COH CAN message event pointer 300 M EVT300 Undefined xxxxn3C1H CAN message event pointer 301 M_EVT301 Undefined xxxxn3C2H CAN message event pointer 302 M EVT302 Undefined xxxxn3C3H CAN message event pointer 303 M EVT303 Undefined XXxxn3C4H CAN message data length register 30 M_DLC30 Undefined XXxxn3C5H CAN message control register 30 M_CTRL30 Undefined xxxxn3C6H CAN message time stamp register 30 M_TIME30 Undefined xxxxn3C8H CAN message data register 300 M DATA300 Undefined xxxxn3C9H CAN message data register 301 M DATA301 Undefined Xxxxn3CAH CAN message data register 302 M DATAS302 Undefined xxxxn3CBH CAN message data register 303 M DATA303 Undefined XXxxn3CCH CAN message data register 304 M_DATA304 Undefined xxxxn3CDH CAN message data register 305 M DATA305 Undefined xxxxn3CEH CAN message data register 306 M DATA306 Undefined xxxxn3CFH CAN message data register 307 M DATAS307 X XIXI XIX XxX Xx Xx Undefined xxxxn3DOH CAN message ID register L30 M IDL30 Undefined xxxxn3D2H CAN message ID register H30 M_IDH30 Undefined xxxxn3D4H CAN message configuration register 30 M_CONF30 Undefined xxxxn3D5H CAN message statu
420. intended by NEC Electronics they must contact NEC Electronics sales representative in advance to determine NEC Electronics s willingness to support a given application Notes 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 10 Preliminary Users Manual U15839EE1VOUMOO 3 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en Espa a
421. ion 1 bit 8 bit 16 bit Initial Value Undefined Xxxxn296H CAN status set cancel register 20 SC_STAT20 0000H xxxxn2A0H CAN message event pointer 210 M_EVT210 Undefined xxxxn2A1H CAN message event pointer 211 M EVT211 Undefined Xxxxn22AH CAN message event pointer 212 M_EVT212 Undefined Xxxxn2A3H CAN message event pointer 213 M_EVT213 Undefined xxxxn2A4H CAN message data length register 21 M_DLC21 Undefined xxxxn2A5H CAN message control register 21 M CTRL21 Undefined xxxxn2A6H CAN message time stamp register 21 M TIME21 Undefined Xxxxxn2A8H CAN message data register 210 M DATA210 Undefined Xxxxn2A9H CAN message data register 211 M DATA211 Undefined XXXXh2AAH CAN message data register 212 M DATA212 Undefined xxxxn2ABH CAN message data register 213 M DATA213 Undefined Xxxxn2ACH CAN message data register 214 M DATA214 Undefined xxxxn2ADH CAN message data register 215 M DATA215 Undefined Xxxxn2AEH CAN message data register 216 M DATA216 Undefined Xxxxn2AFH CAN message data register 217 M_DATA217 x K K XIX XxX XxX Xx Undefined xxxxn2BOH CAN message ID register L21 M_IDL21 Undefined Xxxxn2B2H CAN message ID register H21 M_IDH21 Undefined xxxxn2B4H CAN message configuration regis
422. ion result Preliminary User s Manual U15839EE1VOUMOO 535 Chapter 15 A D Converter Figure 15 9 Relation between Analog Input Voltage and A D Conversion Result lt gt c a a 2048 1024 2048 1024 2048 2048 1024 2048 1024 2048 1024 Input voltage AVpp 15 4 Interrupt Request The A D converter generates a dedicated interrupt A D conversion termination interrupt INTAD 1 A D conversion termination interrupt INTAD In A D conversion enabled status an A D conversion termination interrupt is generated when the specified input channel A D conversion has terminated Preliminary User s Manual U15839EE1VOUMOO 536 Chapter 15 A D Converter 15 5 A D Converter Operation 15 5 1 A D converter basic operation A D conversion is performed using the following procedure 1 Set the analog input selection using the ADSNete 1 register Setting 1 the ADCSN 2 pit of the ApMNete 1 register starts the A D conversion for the selected A D input channel 2 When the A D conversion starts the selected analog input is compared with the voltage generated by the D A converter 3 When the 10 bit comparison is completed the conversion result is stored in the ADCR ADCRL and ADCRH registers and a new conversion operation is started 4 Aninterrupt request signal INTAD is generated after completion of each conversion Notes 1 I
423. ions show that the prescaler must be an even number between 2 and 128 the data bit time must be a value in the range 8 to 25 As the synchronization jump width SJW is defined as 3 TQ the maximum setting for the sampling point SPT can be only 3 TQ less than the setting for the data bit time DBT and also less than 17 TQ SPT lt min 1 17 Based on the restrictions and assumptions above the four settings are basically possible Prescaler Data Bit Time Max Sampling Point Calculated Sampling BRP DBTR SPTR Point 5 8 62 5 9 12 75 13 16 81 25 17 24 71 510 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Regarding the maximum sampling point setting and the resulting sampling point two settings meet all the requirements above Therefore the correct settings are 1 2 TLM 0 BRP5 to BRPO DBTR4 to DBTRO SPTR4 to SPTRO or BRP5 to BRPO DBTR4 to DBTRO SPTR4 to SPTRO TLM 1 BRP7 to BRPO DBTR4 to DBTRO SPTR4 to SPTRO or BRP7 to BRPO DBTR4 to DBTRO SPTR4 t oSPTRO 000101B 01111B 01100B 000111B 01011B 01000B 00001011B 01111B 01100B 00001111B 01011B 01000B Preliminary User s Manual U15839EE1VOUMOO prescaler BRP 12 TQ data bit time DBT 16 TQ sampling point SPT 13 TQ prescaler BRP 16 TQ data bit time DBT 12 TQ sampling point SPT 9 TQ prescaler BRP 12 data bit
424. is 1 message buffer number 15 ID 2 023H 2 message buffer number 1 ID 120H 3 message buffer number 22 ID 123H 4 message buffer number 14 ID 223H 5b message buffer number 2 ID 229H Preliminary User s Manual U15839EE1VOUMOO 443 Chapter 14 FCAN Interface Function Table 14 10 Example for Automatic Transmission Priority Detection Message Buffer Message Buffer Message Buffer Message Buffer Waiting for Address OffsetNote1 Number Link TypeNote2 Transmission Identifier zx D wo a MDM N Co Notes 1 The address of a message buffer entry is calculated according to the following formula effective address PP_BASE address offset 2 TRX transmit message Caution In case more than 5 transmit messages are linked to a CAN module the user must allocate the 5 higher prior transmit messages to message buffers with a lower address There is no sorting needed among the 5 higher prior message buffer 444 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Table 14 11 Example for Transmit Buffer Allocation When More Than 5 Buffers Linked to a CAN Module Message Buffer Address Offset Notis Number Link Type Message Buffer Message Buffer Message Buffer pb Identifier 007H 001H Note 3 00
425. is reset if the result is positive 0 The operation result was positive or 0 1 The operation result was negative This flag is set if the result of operation is zero if the result is not zero it is reset 0 The operation result was not 0 1 The operation result was 0 Note The result of a saturation processed operation is determined by the contents of the OV and S flags in the saturation operation Simply setting the OV flag 1 will set the SAT flag 1 ina saturation operation 60 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function Table 3 3 Saturation Processed Operation Result Flag Status Saturation Processed Operation Result Status of Operation Result Maximum positive value exceeded 7FFFFFFFH Maximum negative value exceeded 80000000H Positive maximum not exceeded Retains the value before operation Operation result itself Negative maximum not exceeded Preliminary User s Manual U15839EE1VOUMOO 61 Chapter 3 CPU Function 3 3 Operation Modes 3 3 1 Operation modes The V850E CA2 Jupiter has the following operations modes Mode specification is carried out by the MODEO to MODE2 pins 1 2 62 Normal operation mode ROM less mode Access to the external ROM is enabled In ROM less mode after system reset is cleared each pin related to the bus interface enters the control mode program execution branches to the reset entry addres
426. ister is not written to causing a protection error Writing 0 to the PRERR flag after the value is checked clears the error Operation conditions of PRERR flag Set condition 1 If the most recent store instruction for peripheral I O register operation is not an operation to write the PHCMD register and if data is written to the specific register 2 If the first store instruction operation after data has been written to the PHCMD register is to memory or peripheral I Os other than those of a specified register Reset condition 1 When 0 is written to the PRERR flag of the PHS register 2 On system reset 106 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 6 4 Internal peripheral function wait control register VSWC This register inserts wait states to the internal access of peripheral SFRs This register can be read or written in 1 bit and 8 bit units Figure 3 20 Internal peripheral function wait control register VSWC Format Reset Value 0 1 1 1 0 1 1 1 7 6 5 4 3 2 1 0 Address R W Bit Name Description Setup wait for internal peripheral bus length Number of data wait states n 7 0 0 1 system clock 2 system clock 3 system clock 4 system clock 5 system clock 6 system clock 7 system clock default Number of data wait states n 7 0 0 1 system clock 2 system clock 3 system clock 4 system clo
427. ister is the A D conversion result register that holds the upper 8 bit result of the A D conversion The ADCRH register is the same as the higher byte of the ADCR register This register can be read in 1 bit or 8 bit units Figure 15 6 A D Conversion Result Register ADCRH 7 6 5 4 3 2 1 0 Address Initial value p The bits ADCR9 to ADCR2 hold the upper 8 bits result of the A D conversion 532 Preliminary User s Manual U15839EE1VOUMOO Chapter 15 A D Converter 6 Port function register 7 8 PORT7 PORTS The PORT7 PORTS register holds the digital input values of the A D input channels ANIO to ANI 1 P70 to P77 P80 to P83 This register can only be read in 16 bit units Figure 15 7 Port Function Register PORT7 PORTS8 5 44 43 12 dn 40 9 7 6 5 04 3 2 14 0 Address tal value Port7 P83 Pe2 Pat erri P76 P75 erai erar Prat P71 Por esee yndet Port8 ANIA 41ANI10 ANIS ANIB ANI7 ANI6 ANIS ANIA ANIS ANI2 ANI ANIO P83 to P80 The bits P83 to P80 holds the digital input values of the A D input channels ANI11 to P77 to P70 The bits P77 to P70 holds the digital input values of the A D input channels ANI7 to Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark x 0to 11 Preliminary User s Manual U15839EE1VOUMOO 533 Chapter 15 A D Converter 7 Port function register 7 PORT The PORT7 register hold
428. itted Transmission in progress no data is in TXBn Writing is permitted Waiting transmission data is in TXBn Writing is not permitted Transmission in progress data is in TXBn Writing is not permitted Caution When transmission is performed continuously data should be written to TXBn register after confirming the TXBF bit value If writing is not permitted transmit data cannot be guaranteed when data is written to TXBn register Preliminary User s Manual U15839EE1VOUMOO 371 4 Chapter 13 Serial Interface Function Reception buffer registers RXBO RXB1 The RXBn register is an 8 bit buffer register for storing parallel data that had been converted by the reception shift register When reception is enabled RXE bit 1 in the ASIMn register receive data is transferred from the reception shift register to the RXBn register synchronized with the completion of the shift in processing of one frame Also a reception completion interrupt request INTSRn is generated by the transfer to the RXBn register For information about the timing for generating this interrupt request refer to 13 2 5 4 Receive operation on page 380 If reception is disabled RXE bit 0 in the ASIMn register the contents of the RXBn register are retained and no processing is performed for transferring data to the RXBn register even when the shift in processing of one frame is completed Also no reception completion interrupt is
429. ives uPD703129 A uPD703129 A1 x 1 to 2 for the derivative uPD703128 A The register layout depends on the TLM bit bit 15 and distinguishes between 6 bit prescaler TLM bit 0 and 8 bit prescaler TLM bit 1 These registers can be read written in 8 bit and 16 bit units However write access is only permit ted in initialisation mode ISTAT bit of the CxCTRL register 1 Figure 14 40 CAN 1 to 4 Bit Rate Prescaler Registers C1BRP to C4BRP 1 2 Address Initial OffsetNote value fo o 0 0 JBTYPE BRPS BRPA BRP3 BRP2 BRP1 BRPO 105CH 0000H C2BRP TLM 0 0 0 0 0 0 0 0 TYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 109CH 0000H 10DCH 0000H 111CH 0000H Address Initial OffsetNete value C1BRP TL BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 105CH TLM 1 15 14 12 11 10 9 8 7 6 5 4 3 2 C2BRP TL BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 109CH C3BRP TL TYPE BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRPO 10DCH C4BRP TL BRP7 BRP6 BRP5 BRP4 BRP3 2 111CH c c c c c c c c c c c c c c c c c c c c c E E lt lt lt U U U m m m Bit Position Bit Name Function Specifies the transfer layer mode 0 Transfer layer uses 6 bit prescaler setting 1 Transfer layer uses 8 bit prescaler setting
430. ked receive buffer received remote frame fits in receive buffer linked to mask 0 received remote frame fits in receive buffer linked to mask 1 received remote frame fits in receive buffer linked to mask 2 received remote frame fits in receive buffer linked to mask 3 Caution A priority class with lower priority don t provide a backup for classes with higher pri 446 ority That means that a message i e data frame remote frame is explicitly stored in the priority class with higher priority and never stored in the lower prior class Example Two receive message buffers are linked to CAN module 1 e Buffer 1 non masked receive buffer with identifier ID e Buffer 2 receive buffer with IDk linked to mask 2 Under that configuration a message with ID is never stored in the receive buffer linked to mask 2 but always into the non masked receive buffer Furthermore there is a fixed inner storage rule in case several buffers of the same priority class are linked to a CAN module For the inner priority class storage rule the data new flag DN in the M STATm register is the first storage criteria m 00 to 31 Whenever the DN flag cannot provide an unambiguous criteria for storing the message i e there are several message buffers of the same priority class with DN flag set or not set the physical message buffer number is chosen as the second criteria Preliminary User s Manual U15839EE1VOUMOO Chapter 14
431. kes place In the V850E CA2 an illegal opcode exception ILGOP Illegal Opcode Trap is considered as an exception trap 8 6 1 Illegal opcode definition The illegal instruction has an opcode bits 10 to 5 of 111111B a sub opcode bits 23 to 26 of 0111B to 1111B and a sub opcode bit 16 of OB An exception trap is generated when an instruction applicable to this illegal instruction is executed 1 1110 5 5 4 0 Remark Arbitrary 3 27 26 2322 16 1 0 1 1 1 x X X X X to X X X X X X 1 11 1 1 Operation If an exception trap occurs the CPU performs the following processing and transfers control to the handler routine Saves the restored PC to DBPC 1 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the exception trap to the PC and trans fers control Figure 8 24 illustrates the processing of the exception trap Figure 8 24 Exception Trap Processing Exception trap ILGOP occurs restored PC PSW 1 CPU processing 54 1 00000060H Exception processing 230 Preliminary User s Manual U15839EE1VOUMOO 2 Chapter 8 Interrupt Exception Processing Function Restore Recovery from an exception trap is carried out by the DBRET instruction By executing the DBRET instruction the CPU carries out the following processing and controls the address of the restored PC
432. l value Remark This register is assigned fix to timebase TMGn1 Preliminary User s Manual U15839EE1VOUMOO 311 Chapter 10 Timer 3 Timer G capture compare registers with external PWW output function GCCn1 to GCCn4 The GCCn1 to GCCn4 registers 16 bit capture compare registers of Timer Gn They can be assigned to one of the 2 counters either TMGnO or TMGn1 In the capture register mode these registers capture the value of TMGnO when the TBGm bit m 1 to 4 of the TMGCMHn register 0 When the TBGm bit 1 these registers hold the value of TMGn1 In compare mode these registers represent the actual compare value and the TOGnm Output m 2 1 to 4 can generate a PWW if they are activated These registers can be read written in 16 bit units Figure 10 29 Timer Gn free assignable Capture Compare Registers GCCnm m z 1 to 4 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Address ital value 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Address ital value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Addess ial value 15 44 13 i2 11 10 9 8 7 8 5 4 3 2 1 Address 11 value Remarks 1 In capture mode only reading is possible 2 n compare mode read write is possible 312 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 3 4 Control registers 1 Timer Gn Mode Register TMGMn n 0 1 This register can be read written in 16 bit 8 bit or 1 bit units Figure 10 30 Timer Gn Mode Register TMGMn 1 2 5
433. l U15839EE1VOUMOO 357 Chapter 12 Watchdog Timer Function 12 2 Configuration The watchdog timer consists of the following hardware Table 12 1 Watchdog Timer Configuration Watchdog timer clock selection register WDCS Watchdog timer mode register WDTM Watch Dog Timer command register WCMD Watch Dog Timer command status register WPHS Control registers 358 Preliminary User s Manual U15839EE1VOUMOO Chapter 12 Watchdog Timer Function 12 3 Watchdog Timer Control Register The registers to control the watchdog timer is shown below Watchdog timer clock selection register WDCS Watchdog timer mode register WDTM 1 Watchdog timer clock selection register WDCS This register selects the overflow times of the watchdog timer WDCS is set by an 8 bit memory manipulation instruction Figure 12 2 Watchdog Timer Clock Selection Register WDCS 7 4 3 2 1 0 Address R W After reset 6 5 wpocs 0 0 0 0 WDCS2WDCS WDCSO FFFF F571H 00H Overflow TimeNote fwo fx fwo fxr 4 MHz main clock 32 KHz sub clock Note This are only 2 examples for fwp The clock depends on the clock tree settings and the external main oscillator resonators 4 or 5 MHz Preliminary User s Manual U15839EE1VOUMOO 359 Chapter 12 Watchdog Timer Function 2 Watchdog timer mode register WDTM This register sets the operating mode of the watchdog timer and enables and disables coun
434. latch timing margin is made 2 basic clocks Clock the minimum allowable transfer rate FLmin is as follows FLm n e MAISE e en cit 2k Di E Therefore the transfer destination s maximum baud rate BRmax that can be received is as follows _ 22k BRmax 11 DARED xBR Similarly the maximum allowable transfer rate FLmax can be obtained as follows 10 _ 2 _ 21k 2 qq FLmax 11xFL ak xFL OR x FL _ 21k 2 FLmax OK x FL x 11 Therefore the transfer destination s minimum baud rate BRmin that can be received is as follows x BR FLmex _ 20k BRmin 11 21 2 The allowable baud rate error of UART5n and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 13 5 Maximum and Minimum Allowable Baud Rate Error Maximum Allowable Minimum Allowable Baud Rate Error Baud Rate Error Division Ratio k Remarks 1 The reception precision depends on the number of bits in one frame the basic clock frequency and the division ratio k The higher the basic clock frequency and the larger the division ratio k the higher the precision 2 k BRGCm setting value Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 4 Transfer rate during continuous transmission During continuous transmission the transfer rate from a stop bit to t
435. lds DINFO the very last bit Number of bits detected on the CAN bus since the last occurrence of a SOF signal Remarks 1 The CAN bus diagnostic information shows all CAN bus bits including stuff bits delimit ers etc 2 The storage of the last 8 bits is automatically stopped either when detecting an error on the CAN bus or when detecting a valid message acknowledge delimiter It is automati cally reset whenever a SOF is detected on the CAN bus Caution In normal operating mode the CxDINF register is hidden and the corresponding CxBRP register appears instead of it at the same address 508 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 4 Operating Considerations 14 4 1 Rules to be observed for correct baud rate settings Observing the following rules for the baud rate setting assures correct operation of a CAN module and compliance to the CAN protocol specification 1 Rule for sampling point SPT setting The sample point position needs to be programmed between 3 TQ and 17 TQ which corresponds to the SPTR4 to SPTRO bits of the CxSYNC register x 1 to 4 for the derivatives uPD703129 A and 0703129 1 x 1 to 2 for the derivative uPD703128 A 3TQ lt SPT p 1 TQ lt 17 TQ 2 p lt 16 p decimal value of bits SPTR4 to SPTRO 2 Rule for data bit time DBT setting The number of TQ per CAN frame bit is restricted to a range from 8 TQ to 25 TQ which corre
436. level for one clock period immediately after each counter overflow except the first overflow The figure shows the state of TOGn1 when FFFFH is set in GCCn1 and TMGn0 is selected Figure 10 48 Timing when FFFFH is set in GCCnm free run ENFGO Match FFFFH FFFFH FFFFH TMGnO INTGCCn1 INTTMGnO TOGn1 ALVG1 1 TOGn1 ALVG1 0 GCCn1 and TMGn0 are selected Preliminary User s Manual U15839EE1VOUMOO 333 334 Chapter 10 Timer c When GCCnm is rewritten during operation m 1 to 4 When GCCn1 is rewritten from 5555H to AAAAH the operation shown below is performed The figure below shows a case where TMGn0 is selected for GCCn1 Figure 10 49 Timing when GCCnm is rewritten during operation free run ENFGO TMGnO GCCn1 Slave register GCCn1 Master register INTCCGn1 INTTMGnO TOGn1 ALVG1 1 5555H AAAAH TOGn1 ALVG1 0 GCCn1 and TMGn0 are selected If GCCn1 is rewritten to AAAAH after the second INTCCGn1 is generated as shown in the figure above AAAAH is reloaded to the GCCn1 register when the next overflow occurs The next match interrupt INTCCGn1 is generated when the value of the counter is AAAAH The pulse width also matches accordingly Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 3 8 Match and clear mode The match and clear mode is mainly used reduce the number of valid bits of the counters TMGnO TMGn1 Therefore the fixed assigned register
437. lisation State Normal Operation Set INIT flag register CXCTRL Read ISTAT flag register CXCTRL Note No Yes INIT Mode Note Incase of permanent bus activity the program loops for a long time Therefore a time out mech anism should be provided in order to limit the runtime of the routine Remark 1 to 4 for the derivatives uPD703129 A uPD703129 A1 x 1 to 2 for the deriva tive UPD703128 A Preliminary User s Manual U15839EE1VOUMOO 519 Chapter 14 FCAN Interface Function Example for C routine int CAN ModuleStop unsigned char module no can module type can mod ptr define CAN module ptr can mod ptr amp can module module no load CAN module ptr if Can mod ptr CxCTRL amp 0x0001 0 if INIT flag not yet set can_mod_ptr gt CxCTRL 0x0100 set INIT flag while can_mod_ptr gt CxCTRL amp 0x0100 0 wait until initialisation state is confirmed ISTAT bit 2 1 return 0 520 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 4 Shutdown of the FCAN system If the clock to the CAN interface should be switched off for power saving the following sequence has to be executed for correct termination of any CAN bus activity 1 2 3 4 5 Caution For each CAN module x x 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 x 1 to 2 for the derivative uPD703128 A
438. llowing areas the data processing method is fixed to Little Endian method Any setting of Big Endian method for these areas according to the BEC register is invalid On chip peripheral I O area Internal RAM area Fetch area of external memory Figure 4 5 Big Endian Addresses within Word 31 24 23 16 17 87 0 0008H 0009H 000AH 000BH 0004H 0005H 0006H 0007H 0000H 0001H 0002H 0003H Figure 4 6 Little Endian Addresses within Word 31 24 23 16 17 8 7 _ 000BH 0009H ooosH 0007H OQ06H 05 0004H 0003H 0002H STE 0000H Preliminary User s Manual U15839EE1VOUMOO 117 Chapter 4 Bus Control Function 4 7 Cache Configuration The cache configuration register BHC is used to set the cache memory configuration for each CS area selected by the chip select signals CSO to CS7 1 Cache configuration register BHC This register can be read or written in 16 bit units 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address s sr Temps qee v ws v em v sm cmm L l L L L l L L L CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bmw ae 14 12 10 8 Sets whether or not the instruction cache located in the block n area can be 6 4 2 0 used Instruction Cache Setting 0 Cache not available 1 Cache available Cautions 1 Be sure to disable the cache for big endian format CS area and CS areas set a
439. lock frequency fork Basic clock frequency k Setting values of MDL7 to MDLO bits in BRGCm register ERR Baud rate error 388 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 3 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination s baud rate is allowed during reception is shown below Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range Figure 13 19 Allowable Baud Rate Range During Reception Latch timing V V V V V V Start bit Bito Bit 1 Bit7 Parity bit Stop bit transfer rate FL 1 data frame 11 FL Minimum allowable Start bit Bit 0 Bit 1 Bit7 Parity bit Stop bit transfer rate FLmin Maximum allowable Start bit Party it J stop bi transfer rate FL FLmax As shown in Figure 13 19 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the BRGCm register If all data up to the final data stop bit is in time for this latch timing the data can be received normally Applying this to 11 bit reception is theoretically as follows BR BR UART5n baud rate k BRGOm register setting value FL 1 bit data length Preliminary User s Manual U15839EE1VOUMOO 389 Chapter 13 Serial Interface Function When the
440. lock is called the basic clock Clock and its frequency is referred to as fok When Power bit 0 Clock is fixed at low level 384 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 2 Serial clock generation A serial clock can be generated according to the settings of the CKSRm and BRGCm registers The basic clock to the 8 bit counter is selected according to the TPS3 to TPSO bits of the CKSRm register The 8 bit counter divisor value can be set according to the MDL7 to MDLO bits of the BRGCm register m 0 1 a Clock select registers CHKSRO CHKSR1 The CKSRm register is an 8 bit register for selecting the basic block according to the TPS3 to TPSO bits The clock selected by the TPS3 to TPSO bits becomes the basic clock Clock of the transmission reception module Its frequency is referred to as This register can be read or written in 8 bit or 1 bit units Figure 13 17 Clock Select Registers CHKSRO0 CHKSR1 Initial value 7 6 5 4 3 2 1 0 Address Specifies the basic clock Basic Clock fc 2 fpcik 4 8 fpcik 16 TPS3 to fpcu 32 TPSO 64 0 0 0 0 0 0 0 0 256 512 1024 1 2048 Arbitrary Arbitrary Setting prohibited Remark fpc internal peripheral clock Preliminary User s Manual U15839EE1VOU
441. lt 5 5 V Power supply voltage range Vpp3 3 0 V lt lt 3 6 V Temperature range Ta 40 to 85 C 32 MHz 400 110 o 20MHz 24 Preliminary User s Manual U15839EE1VOUMOO Chapter 1 Bus control unit Address data separated bus Supply voltage power for Bus Interface Chip Select Signals DMA control unit lines 5 V Input lines 5 V lines 3 3 V A D Converter Select Mode AVngr switchable On Off by Software Introduction 24 bit address 16 bit data bus 3 3 V 3 4 channels 51 12 15 10 bit resolution 12 channels Analog input channels shared with port functionality Serial Interfaces 3 wire mode UART mode Full CAN Interface 2 0b active Timers 16 bit multi purpose timer event counter 16 bit multi purpose timer counter 16 bit OS timer Watch timer Watchdog timer Interrupts and exceptions Non maskable interrupts Maskable interrupts Software exceptions Exception trap Clock Correction of Sub Oscillator Package e CMOS technology Remark 3 channels 2 channels 2 4 channels 2 channel 1 channel 2 channel 1 channel 1 channel 2 source 57 sources 63 sources 32 sources 1 source uPD703128 uPD703129 144 QFP 0 5 mm pin pitch The CAN macro of this device fulfils the requirements according ISO 11898 Additionally the CAN macro was tested according to
442. lumn right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark Supplementary explanation to the text Numeric notation Binary XXxx or Decimal XXxx Hexadecimal XXXxH or Ox Xxxx Prefixes representing powers of 2 address space memory capacity kilo 219 1024 M mega 220 10242 1 048 576 giga 299 1024 1 073 741 824 Preliminary User s Manual U15839EE1VOUMOO Table of Contents Preface sak ee sage EAE E Ee dh 5 Chapter 1 Introduction lt i 223620 ee ro RR ERR RERR eee eek wed 23 11 mcr 23 1 2 Device Features 5 oou dt eed de et IE 24 1 3 Application Fields ce ace toa en Sa ee ee CA ee Se ad 26 1 4 Ordering Information 000 ee 26 1 5 Pin Configuration Top 27 1 6 Function Block 29 Onchip lnits bate ater Pa E E REG dread are Sa dia MERE Ra 30 Chapter2 Pin Functions uk dee v reete ER UL ERE 33 2 1 ListofPin Functions 2 bI Il eM Il Se bx x ee ele pex 33 2 2 Description of Pin Functions lsseeeeeeee e III III 40 2 3
443. m 5 Mbps Master mode or slave mode can be selected e Transmission data length 8 bits or 16 bits Transfer data direction can be switched between MSB first and LSB first e Eight clock signals can be selected 7 master clocks and 1 slave clock e 9 wire type SO0n Serial transmit data output SIOn Serial transmit data input SCKOn Serial clock input output Interrupt sources 1 type Transmission reception completion interrupt INTCSIOn Transmission reception mode and reception only mode can be specified Two transmission buffers SOTBFn SOTBFLn SOTBn SOTBLn and two reception buffers SIRBn SIRBLn SIRBEn SIRBELn are provided on chip Single transfer mode and repeat transfer mode can be specified Remark n 0to2 392 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 3 2 Configuration CSIOn is controlled via the clocked serial interface mode register CSIMn n 0 to 2 Transmission reception of data is performed with reading SlOn register n 0 to 2 1 2 3 4 5 6 7 8 9 10 11 Clocked serial interface mode registers CSIMO to CSIM2 The CSIMn register is 8 bit register that specifies the operation of CSlOn Clocked serial interface clock selection registers CSICO to CSIC2 The CSICn register is an 8 bit register that controls the CSIOn serial transfer operation Serial I O shift registers SIOO to
444. me Function D RQNote DOFL Note pies Sets the interrupt source that serves as the DMA start factor Interrupt Source Peripheral Source INTIN1 CSIO INTIN2 CSI INTIN3 CSI2 INTIN5 UARTO Transmission INTIN7 UART1 Transmission INTIN8 ADC INTIN15 TMGO 4 INTIN16 TMC1 Note DRQ and DOFL are set by hardware and reset by software Setting these bits by software is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFR3 register set tings 2 An interrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor 182 Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 7 3 Next Address Setting Function The DMA source address registers DSAHn DSALn DMA destination address registers DDAHn DDALn and DMA transfer count register DBCn are buffer registers with a 2 stage FIFO configuration When the terminal count is issued these registers are automatically rewritten with the value that was set immediately before Therefore during DMA transfer transfer is automatically started when a new DMA transfer setting is made for these registers and the MLEn bit of the DCHCn register is set however the DMA transfer end interrupt may be issued even if DMA transfer is automatically started Figure 7 14
445. mmable data waits can be inserted during the on page cycle through setting of the PRC register Up to 7 states of programmable data wait can be inserted during the off page cycle through setting of the DWCO and DWC1 registers Waits can be controlled with pin input Preliminary User s Manual U15839EE1VOUMOO 145 Chapter 5 Memory Access Control Function 5 2 2 Page ROM connections Examples of page ROM connections are shown below Figure 5 3 Example of Page ROM Connections a In case of 16 bit data bus width V850E CA2 16 Mbit page ROM 1 Mword x 16 bits b In case of 8 bit data bus width A1 to A21 DO to D7 K 16 Mbit page ROM 2 Mwords x 8 bits D8 to D15 K V850E CA2 16 Mbit page ROM 2 Mwords x 8 bits Remark CS0 CS3 and CS4 146 Preliminary User s Manual U15839EE1VOUMOO Chapter 5 Memory Access Control Function 5 2 3 On page off page judgment Whether a page ROM cycle is on page or off page is judged by latching the address of the previous cycle and comparing it with the address of the current cycle Through the page ROM configuration register PRC according to the configuration of the connected page ROM and the number of continuously readable bits one of the addresses A3 to A6 is set as the masking address no comparison is made Figure 5 4 On Page Off Page Judgment during Page ROM Connection 1 2 a In case of
446. module It determines the number of FCAN system clocks fmen per time quantum TQ A time quantum TQ is the basic unit of a bit in a CAN frame 504 TOR fete Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 9 CAN 1 to 4 synchronization control registers 15 to CASYNC A bit in a CAN frame is built by a programmable number of time quanta TQ as shown in the Figure 14 41 below Figure 14 41 Bus Bit Timing DBT rs al SPT mm SYNC SEG PROP SEG PHASE SEG PHASE SEG2 1 1 8 1 8 A 1 8 time quanta time quanta time quanta time quanta Sampling Point For the CAN modules in the FCAN system the bit length of segments SYNC SEG PROP SEG PHASE SEG1 and PHASE SEG2 must be defined explicitly All necessary CAN bit timings are programmed by defining the total number of time quanta TQ per CAN bit DBT the location of the sample point i e SPT as a number of TQ The CAN protocol segmentation is done by the CAN module automatically Due to re synchronisation mechanisms the CAN module may lengthen PHASE SEG or shorten PHASE SEG2 by one or more TQ The total number of TQ for which the CAN module is permitted to lengthen or shorten the phase segments is called synchronisation jump width SJW The SJW value must be less or equal the difference of and SPT which corresponds to PHASE SEG2 and can be specified in the range of 1 TQ to 4 TQ
447. module register while GOM bit of the CGST register is cleared 0 2 Interrupt signals an illegal FCAN system shut down i e GOM bit is going to be cleared while at least one of the CAN modules is not in ini tialisation state Note The register address is calculated according to the following formula effective address PP_BASE address offset 468 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 22 CAN Global Interrupt Pending Register CGINTP 2 2 Write Clears the interrupt pending bit GINT7 CL GINT7 0 No change of GINT7 bit 1 GINT7 bit is cleared 0 Clears the interrupt pending bit GINT3 CL GINT3 0 No change of GINT3 bit 1 GINT3 bit is cleared 0 Clears the interrupt pending bit GINT2 CL GINT2 0 No change of GINT2 bit 1 GINT2 bit is cleared 0 Clears the interrupt pending bit GINT1 CL GINT1 0 No change of GINT1 bit 1 GINT1 bit is cleared 0 Remarks 1 The interrupts GINT1 GINT2 and GINT7 are only generated when the corresponding interrupt enable bit in the CGIE register is set 2 In the CGIE register is no interrupt enable bit implemented for GINT3 Thus this inter rupt cannot be disabled 3 The interrupt pending bits must be cleared by software in the interrupt service routine Caution In case the interrupt pending bit is not cleared by software in the interrupt service routine no subsequent interrupt is generated
448. more than once between the 1st and 2nd INTCCCOO interrupts Remarks 1 DO to 03 TMCO register s count values 2 t Count clock cycle 3 In this example the valid edge of TICOO input has been set to both edges rising and falling 288 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 4 Compare operation The TMCO register has two capture compare registers These are the CCCOO register and the CCC01 register A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMSO bits of the TMCCO 1 register If 1 is set in the CMS1 and CMSO bits of the TMCC01 register the register operates as a compare register A compare operation that compares the value that was set in the compare register and the TMCO count value is performed If the TMCO count value matches the value of the compare register which had been set in advance a match signal is sent to the output control circuit The match signal causes the timer output to change and an interrupt request signal INTCCCOO INTCCC01 to be generated at the same time Figure 10 13 Timing of compare operation Count up Compare register CCC01 Match detection INTCCCO 1 S n Remark The match is detected immediately after the count up and the match detection signal is generated Preliminary User s Manual U15839EE1VOUMOO 289
449. must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not
450. n O loiojoo o o jo jo ojoj ojo j ooco oj o o o oj o o ooolo o o oijioio o o oiloiojo o o oo o c FCAERPR2 Preliminary User s Manual U15839EE1VOUMOO FCAERPR1 FC4ERPRO 217 Chapter 8 Interrupt Exception Processing Function Table 8 2 Addresses and Bits of Interrupt Control Registers 2 2 ey Address Register FFFFF166H CSIOIC CSIOIF CSIOMK FFFFF168H CSMIC CSMIF CSHMK FFFFF16AH CSI2IC CSI2IF CSI2MK FFFFF16CH SEROIC SEROIF SEROMK FFFFF16EH SROIC SROIF SROMK FFFFF170H STOIC STOIF STOMK FFFFF172H SER1IC SER1IF 1 FFFFF174H SR1IC SRIIF SR1MK FFFFF176H ST1IC ST1IF ST1MK FFFFF178H DMAOIC DMAOIF DMAOMK FFFFF17AH DMA1IC DMA1IF DMA1MK FFFFF17CH DMA2IC DMA2IF DMA2MK FFFFF17EH DMA3IC DMASIF DMA3MK FFFFF180H DOVFIC DOVFIF DOVFMK FFFFF182H POOIC POOIF POOMK FFFFF184H 5 POSIF PO5MK FFFFF186H P10IC FFFFF188H P15IC FFFFF18AH P20lC FFFFF18CH P21IC FFFFF18EH Reserved CSIOPR2 CSIOPR1 CSIOPRO CSHPR2 CSHPR1 CSHPRO CSl2PR2 CSI2PRH1 CSI2PRO SEROPR2 SEROPR1 SEROPRO SROPR2 SROPR1 SROPRO STOPR2 STOPR1 STOPRO SER1PR2 SER1PR1 SER1PRO SR1PR2 SR1PR1 SR1PRO ST1PR2 ST1PR1 ST1PRO DMAOPR2 DMAOPR1 DMAOPRO DMA1PR2 DMA1PR1 DMA1PRO DMA2PR2 DMA2PR1 DMA2PRO DMA3PR2 DMA3PR1 DMASPRO DOVFPR2 DOVFPR1 DOVFPRO POOPR2 POOPR1 POOPRO POSPR2 POSPR1 POSPRO P10PR2 P10PR1 P10PRO P15PR2
451. n 15 to 0 TSO Remark The trigger for the time stamp capture event is selected by the TMR flag of the CxCTRL register For details refer to chapter 11 2 5 Time stamp Note The address of a message time stamp register is calculated according to the following formula effective address PP_BASE address offset Remarks 1 00 to 31 2 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 3 1 to 2 for the derivative LPD7031928 A Preliminary User s Manual U15839EE1VOUMOO 483 Chapter 14 FCAN Interface Function 9 Message event registers m0 m1 M EVTmO M EVTm1 M EVTm3 m 00 to 31 The message event registers M EVTmO MEVTm1 and M EVTm3 imply the event pointers for event processing with a CAN bridge m 0 to 31 These register can be read written in 8 bit units Figure 14 32 Message Event Registers m0 m1 and m3 M_EVTm0 M_EVTm1 M_EVTm2 M_EVTm3 00 to 31 Address 7 6 5 4 3 2 1 0 Initial value _EVTm0 PTRO7 PTRO06 PTRO5 PTRO4 PTRO3 PTRO2 PTRO1 PTROO 800H undef m x 20H M EVTm1 PTR17 PTR16 PTR15 PTR14 PTR13 PTR12 PTR11 PTR10 801H undef m x 20H _EVTm2 PTR27 PTR26 PTR25 PTR24 PTR23 PTR22 PTR21 PTR20 802H undef m x 20H M EVTm3 PTR37 PTR36 PTR35 PTR34 PTR33 PTR32 PTR31 PTR30 803H undef m x 20H PTRO7 to PTROO PTR17 to PTR10 PTR27 to PTR20 PTR37 to PTR30 8 bit event pointer 0 fo
452. n 178 DMA Trigger Factor Registers 0 DTFRO sessee m 179 Preliminary Users Manual U15839EE1VOUMOO 13 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 7 26 Figure 7 27 Figure 7 28 Figure 7 29 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 11 Figure 8 12 Figure 8 13 Figure 8 14 Figure 8 15 Figure 8 16 Figure 8 17 Figure 8 18 Figure 8 19 Figure 8 20 Figure 8 21 Figure 8 22 Figure 8 23 Figure 8 24 Figure 8 25 Figure 8 26 Figure 8 27 Figure 8 28 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 14 DMA Trigger Factor Registers 1 DTFR1 esee 180 DMA Trigger Factor Registers 2 DTFR2 esee 181 DMA Trigger Factor Registers DTFR3 esee 182 Buffer Register Configuration sss enne enne 183 DMAC Bus Cycle State Transition 186 Single Transfer Example 1 ia nennen snnt 187 Single Transfer Example 2 2 nnn 187 Single Transfer Example 3
453. n circuit control of internal return resistance 0 Resistance connected 1 Resistance disconnected Remark The FRC bit must always remain cleared 0 while sub system clock operation is enabled Main system clock oscillation circuit control of internal return resistance 0 Resistance connected 1 Resistance disconnected Remark The initial setting of the MFRC bit must not be changed at anytime To secure proper operation of the main system clock the internal feed back resistance must remain connected always MFRC Preliminary User s Manual U15839EE1VOUMOO 245 Chapter 9 Clock Generator Figure 9 5 Processor Clock Control Register PCC 2 2 Bit name Function CLS CKS1 CKSO Specifies the CPU clock source Main oscillator SSCG PLL Main oscillator frequency x 4 PLL Main oscillator frequency x 8 Sub Oscillator Note X don t care Caution Data is set to the registers by the following sequence Remarks 1 246 Write the set data to the command register PHCMD see Chapter 3 6 2 Peripheral Command Register PHCMD on page 105 Write the set data to the destination register PCC If it is required to switch to another CPU clock source it is recommended to monitor the status of the clock source to be selected before Switching to an unstable clock source is not protected by hardware It is only possible to change the contents of the PCC register for one time after the
454. n in 8 bit or 1 bit units Figure 16 14 Port 3 Mode Register PM3 0 Address At Reset 7 6 5 4 3 2 1 o o PM35 PM34 Pass PM32 PM31 PM3O FFFFF424H PM2n Specifies input output mode of P2n pin 7t00 n 7 to 0 0 Output mode Output buffer on E 1 Input mode Output buffer off b Port 3 mode control register PMC3 This register can be read or written in 8 bit or 1 bit units Figure 16 15 Port 3 Mode Control Register PMC3 7 4 3 2 1 0 Address At Reset 6 5 Bit Position Bit Name Function Specifies operation mode of P35 pin 0 Input output port mode 1 TIGO5 input mode or external interrupt request INTPO5 input mode Specifies operation mode of P34 pin 0 Input output port mode 1 TIGO4 TOG04 input output mode Specifies operation mode of P33 pin 0 Input output port mode 1 TIGO3 TOGO3 input output mode Specifies operation mode of P32 pin 0 Input output port mode 1 TIGO2 TOGO02 input output mode Specifies operation mode of P31 pin 0 Input output port mode 1 TIGO1 TOGO0 1 input output mode Specifies operation mode of P30 pin 0 Input output port mode 1 TIGOO input mode or external interrupt request INTPOO input mode Preliminary User s Manual U15839EE1VOUMOO 563 Chapter 16 Port Functions 16 3 4 Port 4 Port 4 is a 6 bit input output port in which input or output can be specified in 1 bit units Each port bit can be independently configured
455. n of the CSI00 to CSIO2 baud rate signals respectively This register can be read written in 8 bit or 1 bit units n 0 to 2 Figure 13 43 Prescaler Mode Registers 0 1 PRSM0 PRSM1 7 6 5 4 3 2 1 0 Address 7 6 5 4 3 2 1 0 Address Initial value 00H Initial value 00H Enables baud rate counter operation 0 Stop baud rate counter operation and fix baud rate output signal to 0 1 Enable baud rate counter operation and start baud rate output operation Selects count clock for baud rate counter Count Clock Selection 2 fpciK 4 fpcik 8 fpcLK 16 Remarks 1 fpc k internal peripheral clock Cautions 1 Do not change the value of the BGCS1 BGCSO bits during transmission reception operation 2 Set the PRSMn register prior to setting the CE bit to 1 424 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function c Prescaler compare registers 0 1 PRSCMO PRSCM1 PRSCMn is an 8 bit compare register that sets the value of the 8 bit timer counter This register can be read written in 8 bit or 1 bit units n 0 to 2 Figure 13 44 Prescaler Compare Registers 0 1 PRSCMO PRSCM1 7 6 5 4 3 2 1 0 Address value PRSCMO PRSCM7 PRSCM6 5 5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCMO FFFFFDCiH 00H 7 6 5 4 3 2 1 0 Address Mal value PRSCM7 to I PRSCMO Compare value of the 8 bit timer counter Cautions 1 The in
456. n the specified A D conversion terminates there also is an A D conversion termination inter rupt INTAD 524 Preliminary User s Manual U15839EE1VOUMOO 6 7 8 9 10 11 Chapter 15 A D Converter A D conversion result register ADCR ADCRL ADCRH The ADCR register is an 16 bit register that holds all 10 bits of an A D conversion result ADCRL is an 8 bit register that holds the lower 2 bits of an A D conversion result ADCRH is an 8 bit register that holds the higher 8 bits of an A D conversion result Whenever an A D conversion terminates the conversion result from the successive approximation register SAR is loaded RESET input sets these to 0000H Controller The controller selects an analog input generates sample and hold circuit operation timing controls the conversion trigger specifies the conversion operation time ANIm pins m 0 to 11 The ANIm pins are the 12 channel analog input pins to analog converter AVrer The AVggr pin is used to input reference voltage to the A D converter A signal input to the ANIm pin is converted to a digital signal based on the voltage applied between AVpgr and Note m 0 to 11 If not using the AVp_er pin connect it to AVpp or AVss AVss pin The AVgg pin is the ground voltage pin of the A D converter Even if not using A D converter always ensure that this pin has the same DC potential as the Vsss pin AVpp pin The AVpp pin is the analog p
457. n trigger unintended interrupt requests Therefore be sure to mask the respective interrupt requests Preliminary User s Manual U15839EE1VOUMOO 223 Chapter 8 Interrupt Exception Processing Function 2 Interrupt mode register 1 INTM1 Figure 8 18 Interrupt Mode Register 1 IMTM1 7 6 5 4 3 2 1 0 Address Initial value INTM1 ESO71 ESO70 ES061 ESO60 ES051 5050 ESO41 ES040 FFFFF882H 00H Edge selection for INTPO5 to interrupt controller Selects active edge for interrupt generation Edge selection Falling edge Rising edge Reserved Both edges Edge selection for INTPOO to interrupt controller Edge selection 0 0 Falling edge 1 0 Reserved Edge selection for INTP5 to interrupt controller Edge selection Falling edge Rising edge Reserved Both edges Edge selection Falling edge Rising edge Reserved Both edges Note Programming edge detection or port mode register can trigger unintended interrupt requests Therefore be sure to mask the respective interrupt requests 224 Preliminary User s Manual U15839EE1VOUMOO Chapter8 Interrupt Exception Processing Function 3 Interrupt mode register 2 INTM2 Figure 8 19 Interrupt Mode Register 2 IMTM2 7 6 5 4 3 2 1 0 Address Initial value 2 ES111 ES110 ES101 ES100 ES091 ESO90 ES081 5080 FFFFF884H 00H Edge selection for INTP21 to interrupt controller
458. nal Operation TXBF bit TXSF bit 1 Set transmission mode 2 Write data 1 to TXBn register 3 Generate start bit Start data 1 transmissionNete 4 Read ASIFn register confirm that TXBF bit 0 Write data 2 lt lt Transmission in progress gt gt lt 5 gt Generate transmission completion interrupt INTSTn lt 6 gt Read ASIFn register confirm that TXBF bit 0 Write data 3 7 Generate start bit Start data 2 transmission lt lt Transmission in progress gt gt lt 8 gt Generate transmission completion interrupt INTSTn lt 9 gt Read ASIFn register confirm that TXBF bit 0 Write data 4 Note For a certain time it may happen that the bit combinations of TXBF and TXSF bits or 11B can be read 378 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function b Ending procedure Figure 13 10 Continuous Transmission End Procedure TXD5n Data V output n 2 APV INTST5n output TXB5n register Data n 1 N Data n Transmission shift register S1 Data n 1 V Data n FFH ASIF5n register Ed V meme n m Bd c bits CAE bit or TXE bit 1 2 3 4 5 6 7 8 lt 9 gt ASIFn Register Transmission End Procedure Internal Operation TXBF TXSF Bit Bit 1 Transmission of data n 2 is in progress
459. nary User s Manual U15839EE1VOUMOO 417 Chapter 13 Serial Interface Function c Next transfer reservation period In the repeat transfer mode the next transfer must be prepared with the period shown in Figure 13 39 Figure 13 39 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits operation mode CKP bit 0 DAP bit 0 SCKOn input output INTCSIn interrupt is Reservation period 7 SCKOn cycles b When data length 16 bits operation mode CKP bit 0 DAP bit 0 SCKOn input output INTCSIn interrupt Reservation period 15 SCKOn cycles 418 Preliminary User s Manual U15839EE1VOUMO00 Chapter 13 Serial Interface Function Figure 13 39 Timing Chart of Next Transfer Reservation Period 2 2 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 SCKOn input output INTCSIn interrupt Reservation period 6 5 SCKOn cycles d When data length 16 bits operation mode CKP bit 0 DAP bit 1 SCKOn input output INTCSIn interrupt Reservation period 14 5 SCKOn cycles Remark nz0to2 Preliminary User s Manual U15839EE1VOUMOO 419 Chapter 13 Serial Interface Function d Cautions To continue repeat transfers it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period If access is performed to the SIRBn register or t
460. nary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions Table 2 1 Port Pins 3 3 Function Alternate Port AH 8 bit input output port Port CS 3 bit input output port Port CT 3 bit input output port Port CM 1 bit input output port Note CAN module and CAN module 4 are available in the derivatives PD703129 A and uPD703129 A1 only Preliminary User s Manual U15839EE1VOUMOO 35 Chapter 2 Pin Functions 2 Non port pins Table 2 2 Non Port Pins 1 3 Pin Name Function Alternate Vppso Vpps2 Power supply 5 V Vss50 Vsss2 GND potential for 5 V power supply N Power supply 3 3 V Vss30 Vss36 GND potential for 3 3 V power supply Connection for 3 3 V clock oscillator power supply GND potential for 3 3 V clock oscillator power supply System clock oscillator connection pins Sub clock oscillator connection pins Selects operating mode System reset input System reset output incl Watchdog timer reset Power supply for A D converter Ground potential for A D converter reference voltage input for A D converter non maskable interrupt input P60 ANIO ANI7 analog input to A D converter P77 to P70 ANI8 ANI 1 analog input to A D converter P80 to P83 P20 serial receive data input to CSIO0 CSIO2 P23 P65 P21 serial transmit data output from CSIO0 CSIO2 P24 P66 P22
461. nary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 1 Features e Multiplication function by PLL synthesizer Spread Spectrum PLL for CPU BCU clock supply e Clock sources Oscillation through oscillator connection Oscillation through sub oscillator connection during sub watch mode Power save modes WATCH mode Sub WATCH mode HALT mode IDLE mode STOP mode low power sub clock for watch timer and watchdog timer to reduce power consumption in watch mode Preliminary User s Manual U15839EE1VOUMOO 239 Chapter 9 Clock Generator 9 2 Configuration Figure 9 1 Block Diagram of the Clock Generator STOP WATCH S WATCH STOP WATCH S WATCH Main System f Clock OSC SSCG 5 64 fx 4 MHz 8 WATCH S WATCH 50 f 5 MHz E NU DLE e 5 CPU BCU gt E fopu 0 STOP WATCH S WATCH foe Y 1 2 Selector Subsystem XT20 Clock OSC 5 o Watchdog Timer o f o WDT 1 128 o Watch Timer 2 fokser2 o Watch Timer f CKSEL1 Peripherals foci This block diagram does not necessarily show the exact wiring in hardware but the functional structure 240 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 3 Control Registers 9 3 1 Clock Control Register CKC This is an 8 bit register that controls the
462. nary User s Manual U15839EE1VOUMOO 275 Chapter 10 Timer 2 Capture compare registers CCC00 and CCCO1 These capture compare registers are 16 bit registers They can be used as capture registers or compare registers according to the CMS1 bit and CMSO bit specifications of Timer C control register 1 TMCCO 1 These registers can be read written in 16 bit units However write operations can only be performed in compare mode Figure 10 3 Capture Compare Register 0 CCCO00 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 Address ial value Figure 10 4 Capture Compare Register 1 CCCO01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O0 Address dal value 276 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer a Setting CCCOn registers to capture registers set CMS1 CMSO bits of TMCCO 1 to 0 When these registers are set to capture registers the valid edges of the corresponding external interrupt signals TICnO n 0 1 are detected as capture triggers The counter register TMCO is synchronized with the capture trigger and the value of TMCO is latched in the CCC00 and CCCO01 registers capture operation The valid edge of the TICOO pin is specified rising falling or both edges according to the IES10 and IESOO bits of the SESCO register The valid edge of the TICO1 pin is specified according to the IES11 and IES10 bits of the SESCO register The capture operation is performed asynchronously relative to the count clock The la
463. nce Write any 8 bit data to the command register WCMD Write the set data to the destination register WDTM 2 If RUN is set to 1 and the watchdog timer is cleared the actual overflow time may be up to 212 x seconds less than the set time 360 Preliminary User s Manual U15839EE1VOUMOO Chapter 12 Watchdog Timer Function 3 Watchdog timer command register WCMD This command register WCMD is used to protect the WDTM register from unintended writing Writing to WDTM register is possible only immediately after writing to WCMD register Data written into WCMD register are ignored Data read from WCMD register are undefined too WDTM is set by an 8 bit memory manipulation instruction Caution WCMD register setting by DMA transfer is prohibited This registers should be writ ten with STORE instruction execution by CPU only Figure 12 4 Watchdog Timer Mode Register WCMD 0 Address R W After reset WCMD EE EE CP E FFFF F580H R W undefined 4 Watchdog timer command status register WPHS The WPHS register monitors the success of a write instruction to the WDTM register If the write to WDTM fails because of violating the special instruction sequence writing WCMD immediately before WDTM the WPRERR flag is set WPHS can be accessed by 8 bit or 1 bit memory instructions Caution The WPERR bit can only be reset by software Setting the WPERR by software is not possible Figure 12 5 Watchdog Timer Mode Register
464. ncreases the interrupt response speed by assigning handler addresses corresponding to interrupts exceptions The collection of these handler addresses is called an interrupt exception table which is located in the external ROM area When an interrupt exception request is accepted execution jumps to the handler address and the program written at that memory is executed Table 3 5 shows the sources of interrupts exceptions and the corresponding addresses Table 3 5 Interrupt Exception Table 1 3 Start Address of Interrupt Exception Table 0000 0000H RESET input 0000 0010H P60 NMI Input 0000 0020H Watchdog timer 0000 0040H TRAP instruction 0000 0050H TRAP instruction 0000 0060H Illegal opcode DBTRAP instruction 0000 0080H Real Time Clock Divider Tick 0000 0090H Compare Match 0000 00A0H Compare Match 0000 00BOH Interval time 0000 00COH P61 0000 00DOH P62 0000 00EOH P63 0000 00F0H P64 0000 0100H P52 0000 0110H P53 0000 0120H Time base 0 Overflow 0000 0130H Time base 1 Overflow Note Reserved for internal use only please leave at RESET value Preliminary User s Manual U15839EE1VOUMOO Interrupt Exception Source Chapter 3 CPU Function Table 3 5 Interrupt Exception Table 2 3 Start Address of Interrupt Exception Table 0000 0140H Interrupt Exception Source CC coincidence Channel 0 0000 0150H CC coincidence Channel 1 0000 0160H
465. nd remains set while the interrupt is serviced When the RETI instruction is executed the bit corresponding to the interrupt request having the highest priority is automatically reset to 0 by hardware However it is not reset to 0 when execution is returned from non maskable interrupt servicing or exception processing This register is read only in 8 bit or 1 bit units Figure 8 12 In Service Priority Register ISPR Initial 7 6 5 4 3 2 1 0 Address value ISPR7 to Indicates priority of interrupt currently acknowledged 7100 0 Interrupt request with priority n not acknowledged ISPRO Ste 1 Interrupt request with priority n acknowledged Remark 0 7 priority level 8 3 7 Maskable interrupt status flag ID The ID flag is bit 5 of the PSW and this controls the maskable interrupt s operating state and stores control information regarding enabling or disabling of interrupt requests Figure 8 13 Maskable Interrupt Status Flag ID 31 876543210 codd value P5SW 00 0000000000000000000 0 0 0 NPEP ID SATCYOV 5 2 00000020H Indicates whether maskable interrupt processing is enabled or disabled 0 Maskable interrupt request acknowledgement enabled 1 Maskable interrupt request acknowledgement disabled pending This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction Its value is also modified by the RETI instruction or LDSR instruction when referencing to PSW Non maskable interrupt requ
466. ne 104 Peripheral Command Register PHCMD 105 Peripheral Status Register PHS 106 Internal peripheral function wait control register VSWC 107 Memory Block FUn ction 110 Chip Area Select Control Registers 0 1 1 2 111 Programmable Peripheral I O Register Outline esses 113 Peripheral Area Selection Control Register 114 Big Endian Addresses within Word ssssseseeeenne nenne 117 Little Endian Addresses within Word sssne eene 117 Example of Wait 133 Example of Connection to SRAM 138 SRAM External ROM External I O Access Timing 1 6 139 Example of Page ROM Connections W sssesseeree nerne renere kreere nnns 146 On Page Off Page Judgment during Page ROM Connection 1 2 147 Page ROM Configuration Register PRO 149 Page ROM Access Timing 1 4 150 Instruction Cache Configuration
467. ned Xxxxn20CH CAN message data register 164 M_DATA164 Undefined xxxxn20DH CAN message data register 165 M_DATA165 Undefined xxxxn20EH 92 CAN message data register 166 M DATA166 Preliminary User s Manual U15839EE1VOUMOO Undefined xxxxn20FH Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 9 18 Function Register Name CAN message data register 167 M DATA167 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined xxxxn210H CAN message ID register L16 M IDL16 Undefined xxxxn212H CAN message ID register H16 M IDH16 Undefined xxxxn214H CAN message configuration register 16 M CONF16 Undefined xxxxn215H CAN message status register 16 M STAT16 Undefined xxxxn216H CAN status set cancel register 16 SC STAT16 0000H Xxxxn220H CAN message event pointer 170 M EVT170 Undefined xxxxn221H CAN message event pointer 171 M EVT171 Undefined Xxxxn222H CAN message event pointer 172 M EVT172 Undefined Xxxxn223H CAN message event pointer 173 M_EVT173 Undefined Xxxxn224H CAN message data length register 17 M_DLC17 Undefined Xxxxn225H CAN message control register 17 M_CTRL17 Undefined Xxxxn226H CAN message time stamp register 17 M_TIME17 Undefined Xxxxn228H C
468. nerated 3 TOGnm does not make a transition until the first overflow occurs Even if the counter is cleared by software TOGnm does not make a transition until the next overflow occurs After the first overflow occurs TOGnm is activated 4 When the value of the counter matches the value of GCCnm TOGnm is deactivated and a match interrupt INTCCGnm is output The counter is not cleared but continues count up operation b The counter overflows and INTTMGnO or INTTMGn 1 is output to activate TOGnm The counter resumes count up operation starting with 0000H Figure 10 46 Timing of PWM operation free run ENFGO TMGnO 1 INTCCGn1 INTTMGnO TOGn1 ALVG1 1 TOGn1 ALVG1 0 Data N is set in GCCn1 counter TMGn0 is selected 332 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer a When OOOOH is set in GCCnm m 1 to 4 When OOOOH is set in GCCnm TOGnm is tied to the inactive level The figure below shows the state of TOGn1 when OOOOH is set in GCCn1 and TMGnO is selected Figure 10 47 Timing when 0000H is set in GCCnm free run ENFGO TMGnO GCCn1 0000H INTCCGn1 INTTMGnO TOGn1 ALVG1 1 Low TOGn1 ALVG1 0 High GCCn1 and TMGn0 are selected b When FFFFH is set in GCCnm m 1 to 4 When FFFFH is set in GCCnm TOGnm outputs the inactive
469. ng a match with the TMCO register If the ENTO and ALV bits of the TMCCO1 register are changed at the same time a glitch spike shaped noise may be generated in the TOCO pin output Either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ENTO and ALV bits do not change at the same time Preliminary User s Manual U15839EE1VOUMOO 295 Chapter 10 Timer 10 2 Timer D 2 x 16 bit interval timer of Timer D are implemented Timer D1 Timer D2 10 2 1 Features Timer D Timer Dn TMD functions as a 16 bit interval timer 10 2 2 Function overview Timer Dn Compare register 1 Count clock selected from divisions of internal peripheral clock maximum frequency of count clock fpc 2 10 MHz 20 MHz Prescaler division ratio 8 division ratios can be selected related to the internal peripheral clock fpc The range is from fpei 2 to fpei 256 Interrupt request sources 1 Compare match interrupt INTTMDn generated with CMDn match signal Timer clear TMDn register can be cleared by CMDn register match Remark In this Timer D chapter following indexes is consequently used e n20 1 for each of the 2 Timer D fpei Internal peripheral clock Figure 10 18 shows the block diagram of the channel of Timer Dn Figure 10 18 Block Diagram of Timer Dn n 0 1 TMCDn clear and count control Clear amp start TMDn 16 bit
470. nput output port mode 1 WAIT wait insertion input 582 Preliminary User s Manual U15839EE1VOUMOO Chapter 17 RESET 17 1 Reset Overview Jupiter needs a system reset in order to initialize on power up or re initialize to escape from power save mode or system malfunction by Watchdog Timer Regarding to the Mode setting and source of reset different actions are performed on reset When low level is input to the RESET pin there is a system reset and each hardware item of the V850E CA2 is initialized to its initial status When the RESET pin changes from low level to high level reset status is released and the CPU starts program execution The user has to initialize the contents of various registers as needed within the pro gram 17 2 Features e Noise elimination of RESET pin using analog delay 17 3 Pin Functions During a system reset most pins all but the RESOUT Vssn CVpp CVss AVpp AVREF pins enter the high impedance state Therefore when memory is connected externally a pull up or pull down resistor must be connected to the memory control pins of alphabet ports PCS PCT If no resistors are connected the memory con tents may be lost when these pins enter the high impedance state For the same reason the output pins of the internal peripheral I O function and other output port should be handled in the same manner Preliminary User s Manual U15839EE1VOUMOO 583 Chapter 17 RESET Table 17 1 shows
471. ntil initial setting of the DWCO and DWC1 registers is finished However it is possible to access external memory areas whose initialization has been finished Preliminary User s Manual U15839EE1VOUMOO 131 Chapter 4 Bus Control Function 2 Address setup wait control register ASC The V850E CA2 Jupiter allows insertion of address setup wait states before the T1 cycle of the SRAM or page ROM cycle The number of address setup wait states can be set with the ASC register for each CS area This register can be read written in 16 bit units 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Address is ASG AC71TAC7OTACG1TACGO TACS1TACBOTACA1TACAOTACS1 ACSO JAC21 AC2O JACTTTACTOTACOTIACOO FFFFFA8AH FFFFH L L L L L L CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Address Cycle Specifies the number of address setup wait states inserted before the T1 cycle of SRAM page ROM cycle for each CS area Number of Wait States Not inserted Remark During address setup wait the external wait function is disabled by the WAIT pin 132 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 8 2 External wait function When an extremely slow device I O or asynchronous system is connected any number of wait states can be inserted in a bus cycle by the external wait pin WAIT to synchronize with the external device Just as with programmable waits access to internal ROM internal RAM and internal peripheral
472. nts of the ASISn register during the INTSERn or INTSRn interrupt servicing n 0 1 The contents of the ASISn register are reset 0 by reading it Table 13 3 Reception Error Causes Error Flag Reception Error The parity specification during transmission did not match Parity error the parity of the reception data Framing error No stop bit was detected The reception of the next data was completed before data was read from the reception buffer register RXBn Overrun error a Separation of reception error interrupt A reception error interrupt can be separated from the INTSRn interrupt and generated as an INTSERn interrupt by clearing the ISRM bit of the ASIMn register to 0 Figure 13 12 When Reception Error Interrupt Is Separated from INTSRn Interrupt ISRM Bit 0 a No error occurs during reception b An error occurs during reception INTSR5n output INTSR5n output Reception completion Reception completion interrupt interrupt A INTSR5n does not occur INTSERS5n output INTSER5n output Reception error Reception error interrupt interrupt Figure 13 13 When Reception Error Interrupt Is Included in INTSHn Interrupt ISRM Bit 1 a No error occurs during reception b An error occurs during reception INTSR5n output INTSR5n output Reception completion Reception completion interr
473. o 31 M STAT00 to M STAT31 Address E 7 6 5 4 3 2 1 OttseiNote 1 Initial value m x 20H Indicates a request for event processing by a CAN bridgeNote2 for this message 0 No pending event processing 1 Event processing is pending Indicates new data received for this message 0 No new message was received 1 At least one new message was received Remarks 1 If the DN flag is set for a transmit message buffer it indicates a remote frame reception In case auto answering RMDEO bit of the M CTRLm register is active the DN flag is cleared automatically after the answer ing data frame is sent If the OVM bit of CxCTRL register is cleared 0 a message buffer assigned to the CAN module might be overwritten by new messages although the DN flag is already set x 1 to 4Nete3 Checking the MOVR bit of the M CTRLm register additionally indicates whether the message buffer has been overwritten After copying a received message from the message buffer to the application memory the DN flag has to be cleared 0 by software Indicates a transmit request of this message 0 No pending transmit request 1 Transmit request is pending Remark f the flag is set for a receive message a remote frame is sent refer to Table 9 16 Enables and indicates application processing of this message 0 Message is processed by the application and not ready to be handled by the assigned CAN module 1 Message is rea
474. o CAN module 4Note 6 Reserved Reserved Reserved Notes 1 The register address is calculated according to the following formula effective address PP BASE address offset 2 Mask number of the linked CAN module specified by MA1 MAO bits CAN module does not handle a message buffer of this type 4 A message buffer of this type is only handled if the linked CAN module is set to diagnostic mode In this case all messages received on the CAN bus will be stored in this message buffer regardless whether they could have been stored in other message buffers as well Even the type of the identifier standard or extended and the type of the frame remote or data frame are not respected In normal operation mode the message buffer is not han dled 5 If the message buffer is not assigned to CAN module it can be used as temporary buffer of the application or by the CAN bridge ELISA 6 CAN module and CAN module 4 are available in the derivatives PD703129 A and uPD703129 A1 only Remark m 00to 31 474 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 3 Message status registers 00 to 31 M STATOO to M STAT31 The M STATm registers indicate transmit and receive status of the corresponding message m m 00 to 31 Bits can be set cleared only by means of the SC STATm register These registers can be read only in 8 bit units Figure 14 26 Message Status Registers 00 t
475. o description of GOM flag above Preliminary User s Manual U15839EE1VOUMOO 459 Chapter 14 FCAN Interface Function 4 CAN global interrupt enable register CGIE The CGIE register enables the global interrupts of the FCAN system This register can be read in 1 bit 8 bit and16 bit units It can be written in 16 bit units only For set ting and clearing certain bits a special set clear method applies Refer to 14 3 1 Bit set clear function on page 452 Figure 14 13 Global Interrupt Enable Register CGIE 1 2 Address Initial OffsetNete value TS T TESTS T3 T4 T ERE 00004 Write Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 13 12 11 15 10 9 8 7 6 5 4 3 2 1 0 ST ST IST GL CL Tel G 7 G IE2 a IE1 G IE7 G IE2 a IE1 Read BENE Enables interrupt by CAN bridge 0 Interrupt disabled 1 Interrupt enabled Remark Due to the reason that no CAN bridge is implemented in the V850E CA2 device this bit must not be set at any time CGIE 1012H Enables illegal address interrupt 0 Interrupt disabled 1 Interrupt enabled Remarks 1 Interrupt signals any access to CAN module register while GOM bit of the CGST register is reset 0 Interrupt signals a write access to the temporary buffer while GOM bit of the CGST register is set 1 Enables access to unavailable memory addresses interrupt 0 Interrupt disabled 1 Interrupt enabled Remarks 1 Interr
476. o switch to the normal operating mode in response to a release cause This mode is entered by configuration the PSM and PSC registers In the WATCH mode program execution is stopped but the contents of all registers and internal RAM prior to entering this mode are retained On chip other peripheral hardware operation is also stopped The state of the various hardware units in the WATCH mode is tabulated below Table 9 7 Operating States in WATCH Mode Items Operation Clock generator Operating SSCG PLL Stopped Internal system clock Stopped WT WDT clock Operating CPU Stopped I O line Unchanged Peripheral function Stops exclude Watch timer Watchdog timer TMC calibration input Main Clock available Retains all internal data before entering WATCH mode such as CPU registers status data and on chip RAM D 15 0 A 23 0 Hi Z RD WRT WRO CSI 0 CS 4 2 H CLKOUT L Internal data WAIT Input value is not sampled Watch mode release The WATCH mode can be released by a non maskable interrupt request an unmasked maska ble interrupt request or RESET signal input 1 Release by interrupt request The WATCH mode is released unconditionally by an unmasked maskable interrupt request regardless of its priority level After oscillator stabilization time has passed CPU starts operation However if the WATCH mode is entered during execution of an interrupt handler the operation
477. ogress This flag is set when NMI is accepted and disables multiple interrupts 0 NMI servicing not under execution 1 NMI servicing under execution Indicates that exception processing is in progress This flag is set when an exception is generated Moreover interrupt requests can be accepted when this bit is set 0 Exception processing not under execution 1 Exception processing under execution Displays whether a maskable interrupt request has been acknowledged or not 0 Interrupt enabled 1 Interrupt disabled Displays that the operation result of a saturated operation processing instruction is sat urated due to overflow Due to the cumulative flag if the operation result is saturated by the saturation operation instruction this bit is set 1 but is not cleared 0 even if the operation results of subsequent instructions are not saturated To clear 0 this bit load the data in PSW Note that in a general arithmetic operation this bit is neither set 1 nor cleared 0 0 Not saturated 1 Saturated S ATNote This flag is set if carry or borrow occurs as result of operation if carry or borrow does not occur it is reset 0 Carry or borrow does not occur 1 Carry or borrow occurs This flag is set if overflow occurs during operation if overflow does not occur it is reset 0 Overflow does not occur 1 Overflow occurs This flag is set if the result of operation is negative it
478. on Read Enables CAN timer event 3 0 Timer event disabled 1 Timer event enabled Enables CAN timer event 2 0 Timer event disabled 1 Timer event enabled 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 Enables CAN timer event 1 0 Timer event disabled 1 Timer event enabled Enables CAN timer event O 0 Timer event disabled 1 Timer event enabled Notes 1 The register address is calculated according to the following formula effective address PP BASE address offset 2 Since there s no CAN bridge implemented in the V850E CA2 device the CGTEN register must not be written at any time It s recommended to keep the reset value always The timer events are as follows timer event 0 fgets 210 timer event 1 fgets 27 timer event 2 fgets 2 4 timer event 3 forg 216 Figure 14 15 Global Time System Counter and event generation CAN Global Time System Counter fars 16 bit free running counter fars 2 E event 14 fers 2 event 2 fors 2 1 STS event 1 fais 2 GTS event 0 462 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 6 CAN global time system counter CGTSC The CGTSC register holds the value of the free running 16 bit CAN global time system counter For details refer to chapters 14 2 3 Clock structure on page 438 and 14 2 5 Time stamp on page 441 This register can be read and writ
479. on Cache Miss Instruction Cache Instruction Cache Interface External Memory Preliminary Users Manual U15839EE1VOUMOO 161 Chapter 6 Instruction Cache Figure 6 8 Refill Sequence to Instruction Cache 16 bit Data Bus Higher address Data part 4 words Lower address 1 word 1 1 1 1 1 i 8 Addr EH lt 7 gt Addr CH 6 Addr AH lt 5 gt Addr 8H lt 4 gt Addr 6H 3 Addr 4H 2 Addr 2H lt 1 gt Addr 0H 128 entries 1 1 1 1 Y Remarks 1 The numbers within pointed brackets indicate the refill sequence 2 Adrs n Data of address in n OH to FH 162 Preliminary User s Manual U15839EE1VOUMOO Chapter6 Instruction Cache 4 Tag Clear Function The tag clear function clears invalidates the tags of one way In addition it automatically clears invalidates the tags of all ways on a system reset Instruction cache tag clear performs the follow ing procedure 1 Read the instruction cache control register ICC and confirm that bits 0 and 1 TCLRO TCLR1 are all cleared 2 Read the ICC register and confirm that bit 12 LOCKO is cleared 3 Setbit TCLRO or bit TCLR1 of the ICC register as follows Cautions 1 To clear the instruction cache tags the tag clear operation by setting the bits TCLRO or TCLR1 of the ICC register must be executed twice Perform all of 1 to 3 above tag clear
480. on UART50 0000 0380H Transmission Completion UART50 Note Reserved for internal use only please leave at RESET value Preliminary User s Manual U15839EE1VOUMOO 71 Chapter 3 CPU Function Table 3 5 Interrupt Exception Table 3 3 Start Address of Interrupt Exception Table 0000 0390H Reception Error UART51 0000 03A0H Reception Completion UART51 0000 03BOH Transmission Completion UART51 0000 03COH DMA Channel 0 transfer completed 0000 03D0H DMA Channel 1 transfer completed 0000 DMA Channel 2 transfer completed 0000 03FOH DMA Channel 3 transfer completed 0000 0400H DMA Overflow 0000 0410H P30 0000 0420H P35 0000 0430H P40 0000 0440H P45 0000 0450H P54 0000 0460H P55 0000 0470H reservedNote Note Reserved for internal use only please leave at RESET value Interrupt Exception Source Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 2 Internal RAM area For the PD703128 12 KB of memory addresses 3FF 8000H to 3FF AFFFH are reserved for the internal RAM area In the PD703129 the 16 KB of addresses 3FF 8000H to 3FF BFFFH are provided as internal physical RAM Figure 3 11 Internal RAM Area of uPD703129 uPD703129 3FF BFFFH Internal RAM area 16 Kbytes 3FF 8000H Figure 3 12 Internal RAM Area of uPD703128 uPD703128 3FF AFFFH Internal RAM area 12 Kbytes 3FF 8000H Preliminary User
481. on maskable external interrupt request input pin Preliminary User s Manual U15839EE1VOUMOO 45 7 8 46 Chapter 2 Pin Functions P70 to P77 Port 7 P80 to P83 Port 8 Input Port 7 is an 8 bit input only port in which all pins are fixed as input pins Port 8 is a 4 bit input only port P70 to P77 and P80 to P83 can function as input ports and as analog input pins for the A D converter in control mode However they cannot be switched between these input port and analog input pin a Port mode P70 to P77 and P80 to P83 are input only pins b Control mode P70 to P77 also function as pins ANIO to ANI7 and P80 to P83 also function as ANI8 to ANI11 but these alternate functions are not switchable c ANIO to ANI11 Analog Input 0 to 11 These are the analog input pins for the A D converter Connect a capacitor between AVpp and AVss to prevent noise related operation faults Also do not apply voltage that is outside the range for AVpp and AVss to pins that are being used as inputs for the A D converter If it is possible for noise above the AVpp range or below the AVss to enter clamp these pins using a diode that has a small Ve value P90 to P97 Port 9 Input Output Port 9 is an 8 bit input output port in which input or output can be set in 1 bit units An operation mode control register is not available for port 9 since no port pin of port 9 is shared with peripheral input output ports a Port mode P90 to
482. on mode 0 Receive only mode 1 Transmission reception mode When the TRMD bit 0 receive only transfer is performed and the SOOn pin output is fixed to low level Data reception is started by reading the SIRBn register When the TRMD bit 1 transmission reception is started by writing data to the SOTBn register Specifies data length 0 8 bits 1 16 bits Specifies transfer direction mode MSB LSB 0 First bit of transfer data is MSB 1 First bit of transfer data is LSB Controls delay of interrupt request signal 0 No delay 1 Delay mode interrupt request signal is delayed 1 2 cycle Caution The delay mode CSIT bit 1 is effective only in the master mode CKS2 to CKSO bits of the CSICn register are not 111B In the slave mode CKS2 to CKSO bits 111B do not set the delay mode Specifies single transfer mode or repeat transfer mode 0 single transfer mode 1 Repeat transfer mode Flag indicating transfer status 0 Idle status 1 Transfer execution status Caution The CSOT bit is cleared 0 by writing 0 to the CSIE bit Remark 0 2 Caution Overwriting the TRMD CCL DIR CSIT and AUTO bits of the CSIMn register can be done only when the CSOT bit 0 If these bits are overwritten at any other time the operation cannot be guaranteed Preliminary User s Manual U15839EE1VOUMOO 395 Chapter 13 Serial Interface Function 2 Clocked serial interface clock selection registers
483. on queue in the CPU The BCU provides a page ROM controller ROMC and a DMA controller DMAC a Page ROM controller ROMC This controller supports accessing ROM that includes the page access function It performs address comparisons with the immediately preceding bus cycle and executes wait con trol for normal access off page page access on page It can handle page widths of 8 to 128 bytes b DMA controller DMAC Instead of the CPU this controller controls data transfer between memory and I O There is one address mode 2 cycle transfer and there are three bus modes single transfer single step transfer and block transfer ROM The PD703128 uPD703129 is a ROM less MCU containing a 16 bit wide non multiplexed bus interface to be able to fetch instructions data from external memories RAM RAM are mapped from address FFFF8000H During instruction fetch data can be accessed from the CPU in 1 clock cycles Interrupt controller INTC This controller handles hardware interrupt requests NMI INTPO to INTP5 from on chip periph eral I O and external hardware Eight levels of interrupt priorities can be specified for these inter rupt requests and multiple interrupt servicing control can be performed for interrupt sources Spread spectrum Clock generator SSCG The spread spectrum clock generator SSCG generates a spread spectrum system clock for the CPU BCU system based on the main oscillator input clock Four types
484. onous Serial Interface Mode Registers ASIMO ASIM1 1 3 367 Asynchronous Serial Interface Status Registers 5150 ASIS1 370 Asynchronous Serial Interface Transmit Status Registers ASIFO ASIF1 371 Reception Buffer Registers RXBO RXB1 372 Transmission Buffer Registers TXBO 1 373 Asynchronous Serial Interface Transmit Receive Data ForMat 375 Asynchronous Serial Interface Transmission Completion Interrupt Timing 376 Continuous Transmission Starting Procedure sse 378 Continuous Transmission End 379 Asynchronous Serial Interface Reception Completion Interrupt Timing 380 When Reception Error Interrupt Is Separated from INTSRn Interrupt sinu ssa 381 When Reception Error Interrupt Is Included INTSRn Interrupt ISAM Bitte p 381 Noise Filter ir ian edere Ron Pee eie eaten ae ete ee 383 Timing of RXD5n Signal Judged as Noise sss 383 Baud Rate Generator BRG Configuration of UART5n n 0 1 384 Clock Select Registers CHKSRO CHKSR1 sse 385 Baud Rate Generator Control Registers BRGCO BRGC1
485. ons are given as an address offset value Caution Before accessing any register or buffer of the FCAN system the base address PP BASE must be fixed by the BPC register Preliminary User s Manual U15839EE1VOUMOO 429 Chapter 14 FCAN Interface Function The sections within the FCAN memory layout contain areas which are defined as illegal addresses or CANx temporary buffer x 1 to 2 for the derivative uPD703128 A x 1 to 4 for the derivatives uPD703129 A and PD703129 A1 Remarks 1 Areas defined as illegal addresses contain neither FCAN registers nor FCAN buffers Those area must not be read nor written by user program 2 CANx temporary buffers can be accessed by CPU write and read accesses when the GOM bit of the CGST register is cleared 0 means FCAN system inactive Whenever the FCAN system is in global operating mode 1 the temporary buffer must not be written by the CPU The global interrupt GINT2 signals accidental write accesses by CPU while the FCAN system is active 1 CAN message buffer section The message buffer section consists of 32 message buffers Each message buffer allocates 32 bytes The message buffers are not statically distributed and linked to the CAN modules rather the user must determine the link of a message buffer to a CAN module by software As a consequence the message buffers can be allocated to a CAN module according to the need of the particular CAN network Table 14 1 Configur
486. ontinues until stop bit is received and after reception is completed either a reception completion interrupt INTSRn or a reception error interrupt INTSERn is generated according to the ISRM bit setting in the ASIMn register If the RXE bit is reset 0 during a receive operation the receive operation is immediately stopped The contents of the reception buffer register RXBn and of the asynchronous serial interface status register ASISn at this time do not change and no reception completion interrupt INTSRn or reception error interrupt INTSERn is generated No reception completion interrupt is generated when RXE bit 0 reception is disabled Figure 13 11 Asynchronous Serial Interface Reception Completion Interrupt Timing san oo Y o1 ve INTSR5n output RXB5n register O_ gt q_X_ um i j csr Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 5 Reception error The three types of error that can occur during a receive operation are a parity error framing error or overrun error The data reception result is that the various flags of the ASISn register are set 1 and a reception error interrupt INTSERn or a reception completion interrupt INTSRn is generated at the same time The ISRM bit of the ASIMn register specifies whether INTSERn or INTSRn is generated The type of error that occurred during reception can be detected by reading the conte
487. ontrols the operation of TMCO 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution If CE 0 the external pulse output becomes inactive level The active level of TOCO output is set with the ALV bit of the TMCC01 register Preliminary User s Manual U15839EE1VOUMOO Controls the internal count clock fcouwr 0 Asynchronously reset entire TMCO unit Stop base clock supply to TMCO unit 1 Supply peripheral clock fpc to TMCO unit Cautions 1 When CAE 0 is set the TMCO unit can be reset asynchronously When CAE 0 the TMCO unit is in a reset state To operate TMCO first set CAE 1 When the CAE bit is changed from 1 to 0 all the registers of the TMCO unit are initialized When again setting CAE 1 be sure to then again set all the registers of the TMCO unit 279 Chapter 10 Timer 2 Timer C control register 1 TMCCO1 The TMCC01 register controls the operation of TMCO This register can be read written in 8 bit or 1 bit units Cautions 1 Do not change the bits of the TMCCO1 register during timer operation If they are to be changed they must be changed after setting the CE bit of the TMCCOO register to 0 If the TMCCO1 register is overwritten during timer operation the operation is not guaranteed 2 If the ENTO bit and the ALV bit are changed simultaneously a glitch spike shaped noise may be generated in the TOCO pin outpu
488. operate operate CS4 CS3 CSO operate operate UWR LWR operate operate RD operate X operate WAIT operate operate RESOUT HIGH HIGH TIGO5 to TIGOO A operate operate TIG15 to TIG10 A operate operate TICO1 to TICOO A operate operate INTPOS to INTPOO operate operate operate operate operate operate INTP15 to INTP10 i operate operate operate operate operate operate INTP21 to INTP20 operate operate operate operate operate operate INTP5 to INTPO operate operate operate operate operate operate NMI operate operate operate operate operate operate TOGO04 to TOGO1 HOLD HOLD HOLD HOLD operate operate TOG14 to TOG11 HOLD HOLD HOLD HOLD operate operate TOCO p HOLD HOLD HOLD HOLD operate operate 5002 5001 5000 A HOLD HOLD HOLD HOLD operate operate 5102 5101 5100 A operate operate SCK2 SCK1 SCKO A HOLD HOLD HOLD 1 HOLD operate operate RXD51 to RXD50 A A operate operate TXD51 to TXD50 A HOLD HOLD HOLD HOLD operate operate FCRXD4Nete to FCRXD1 operate FCTXD4Note FCTXD1 HOLD HOLD HOLD HOLD operate operate ANH 1 to ANIO operate operate 1 2 4 5 6 9 HOLD HOLD HOLD HOLD operate operate PAH7 to PAHO HOLD HOLD HOLD HOLD operate operate PCS4 PCS3 PCSO HOLD HOLD HOLD HOLD operate
489. operations can be performed continuously without suspension even during an interrupt interval When transmission is performed continuously data should be written after referencing the ASIFn register to prevent writing to the TXBn register by mistake This register is read only in 8 bit or 1 bit units n 0 1 Figure 13 4 Asynchronous Serial Interface Transmit Status Registers ASIFO ASIF1 Initial value ASIFO 0 Lour 0 wr ae Oe TXBFO TXSFO FFFFFAO5H 00H 7 6 5 4 3 2 1 0 Address This is a transmission buffer data flag 0 When the ASIMn register s Power or TXE bits is 0 or when data has been transferred to the transmission shift register Data to be transferred 1 TXBF i next to TXBn register does not exist 1 Data exists in TXBn register when the TXBn register has been written to Data to be transferred next exists in TXBn register This is a transmission shift register data flag It indicates the transmission status of UART5n 0 When the ASIMn register s Power or TXE bits is set to 0 or when follow 0 TXSF ing transfer completion the next data transfer from the TXBn register is not performed waiting transmission 1 When data has been transferred from the TXBn register Transmission in progress The following table shows relationships between the transmission status and write operations to TXBn register TXBF TXSF Transmission Status 9 Initial status or transmission completed Writing is perm
490. or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function 2 Preliminary User s Manual U15839EE1VOUMOO The information in this document is current as of 18 08 2003 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or rep
491. or each CS space The bus cycle following the T2 state starts after the idle state is inserted An idle state is inserted after read write cycles for SRAM external I O or external ROM In the following cases an idle state is inserted in the timing e after read write cycles for SRAM external I O or external ROM The idle state insertion setting can be specified by program using the bus cycle control register BCC Immediately after the system reset idle state insertion is automatically programmed for all memory blocks 1 Bus cycle control register BCC This register can be read written in 16 bit units Initial value FFFFF488H FFFFH 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Address CTT BOTT EGET BORD BCH TES SCAT BCIT ECST SCAT EC ECZU ECT OTD EGIT BC L L L L L L L L CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 BCC Bit Position Function Data Cycle Specifies the insertion of an idle state when accessing corresponding CSn area Idle State in CSn Area Not inserted Cautions 1 The internal iCache area the internal RAM area and the internal peripheral area are not subject to insertion of an idle state 2 Write to the BCC register after reset and then do not change the set value Also do not access an external memory area other than that for this initialization rou tine until initial setting of the BCC register is finished However it is possible to access external memory
492. ormed again This operation continues until a terminal count occurs When the DMAC has released the bus if another higher priority DMA transfer request is issued the higher priority DMA request always takes precedence Figure 7 20 Single Step Transfer Example 1 on page 189 shows a DMA transfer example in single step transfer mode Figure 7 20 Single Step Transfer Example 1 DMA Transfer Request CH1 Note Note Note DMA channel 1 terminal count Figure 7 21 Single Step Transfer Example 2 on page 189 shows a DMA transfer example in single step transfer mode in which a higher priority DMA transfer request is generated while the lower DMA channel has released the bus Figure 7 21 Single Step Transfer Example 2 DMA Transfer Request CHO Transfer Request CH1 DMA channel 0 DMA channel 1 terminal count terminal count Note The bus is always released Preliminary User s Manual U15839EE1VOUMOO 189 Chapter 7 DMA Functions DMA Controller 7 5 3 Line Transfer Mode In line transfer mode the DMAC releases the bus after every four byte halfword or word transfer If there is a subsequent DMA transfer request four transfers are performed again This operation contin ues until a terminal count occurs In two cycle transfer the operation from read to write is repeated four times If a higher priority DMA transfer request is generated whil
493. ot check status of TRQ flag and RDY flag 1 TRQ flag and RDY flag must be set Search criteria for the mask link bits MT2 to MTO of the M CONFm registers 0 Do not check mask link bits 1 Check only message buffers not linked with a mask Search criteria for data new flag DN of the M STATm registers 0 Do not check status of the DN flag 1 DN flag must be set Specifies the CAN module number to search for SMNO CAN Module Number Search for message buffers not linked to any CAN module Search for message buffers linked to CAN module 1 Search for message buffers linked to CAN module 2 Search for message buffers linked to CAN module 3Nete 2 Search for message buffers linked to CAN module 4Nete 2 Remark The SMNO2 to SMNOO bits define which messages are checked by the message search Only messages assigned to the CAN module defined by SMNO2 to SMNOO are checked all other messages are ignored Specifies the number of message buffer the search starts for 0 to 31 Remarks 1 Any search will start from the message number defined by STRT5 to STRTO and end at the highest available message buffer If a search STRTS to results in multiple matches the lowest buffer number is returned STRTO To get the next match without modifying the search criteria the STRT5 to STRTO bits must be set to the succeeding number of the found one MFND5 to MFNDO of the CGMSR register Notes 1 Th
494. ote If this bit is set to 1 proper operation can not be guaranteed Data is set in the power save control register PSC according to the following sequence 1 Set the power save mode register PSM with the following instructions e Store instruction ST SST instruction Bit manipulation instruction SET1 CLR1 NOT1 instruction 2 Prepare data in any one of the general purpose registers to set to the specific register 3 Write arbitrary data to the command register PRCMD 4 Set the power save control register PSC with the following instructions Store instruction ST SST instruction Bit manipulation instruction SET1 CLR1 NOT1 instruction 5 Assert the NOP instructions 5 instructions lt 5 gt to 9 268 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator Sample coding lt 1 gt ST B r11 PSM r0 Set PSM register 2 MOV 0x04 r10 9 ST B r10 r0 Write PRCMD register 4 ST B r10 PSC r0 Set PSC register 5 NOP Dummy instruction 6 NOP Dummy instruction 7 NOP Dummy instruction 8 NOP Dummy instruction 9 NOP Dummy instruction next instruction Execution routine after software STOP mode and IDLE mode release No special sequence is required to read the specific register Cautions 1 Remarks 1 A store instruction for the command register does not accept interrupts This coding is made on
495. ow the lowest operating voltage the internal RAM content is retained as long as the data retention voltage Vpppn is maintained STOP mode release The STOP mode can be released by a non maskable interrupt request an unmasked maskable interrupt request or RESET signal input Preliminary User s Manual U15839EE1VOUMOO 265 Chapter 9 Clock Generator 1 When released by RESET input This operation is the same as normal reset operation Oscillator stabilization time must be ensured by reset input Figure 9 13 STOP mode released by RESET input STOP mode setting Main Oscillation circuit System clock Er STOP state ein n K RESET signal E Internal system reset signal a Ensuring elapse of oscillation Oscillation circuit stop Stabilization time by RESET P 266 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 2 When released by Watchdog Timer RESET input CPU operation starts after main oscillation stabilization time has been secured Figure 9 14 STOP mode release by Watchdog reset NMI INT STOP mode setting Main Oscillation circuit System clock STOP state T NMI or INT input Oscillation stabilization counter Oscillation circuit stop I count time 2 After oscillation stabilization time has passed CPU starts operation Before entering the STOP mode the SSCG and PLL are switched off by hardware A
496. ower supply pin of A D converter Even if not using A D converter always ensure that this pin has the same potential as the Vpps pin Note When connecting the AVpgr pin to AVgg the power consumption will be reduced Caution Use input voltages to ANIm that are within the range of the ratings In particular if a voltage higher than AVpp or lower than even one within the range of absolute maximum ratings is input the conversion value of that channel is undefined and the conversion values of other channels also may be affected Preliminary User s Manual U15839EE1VOUMOO 525 ANIO ANI1 ANI2 ANIA ANIS ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 Figure 15 1 Sample amp hold circuit Chapter 15 A D Converter Block Diagram of A D Converter Comparator 3 o 5 a 4 ADS3 ADS2 ADS1 ADSO Analog input channel setting register ADS Controller and D A Converter Successive approximation register SAR INTAD ADCR ADCRH ADCRL 0 ADCS FR2 FR1 0 A D converter mode register ADM AVpp AVrer AVss A D conversion result 16 registers ADCRL ADCRH Internal Bus Cautions 1 526 Noise at an analog input pin ANIm or reference voltage input pin AVpggp may give rise to an invalid conversion result Software processing is needed in ord
497. p16 reg1 Z flag lt Not Load memory bit adr bit 3 Bit manip Store memory bit adr bit 3 1 ulate 10bbb1111 120 lt GR reg1 sign extend disp16 n e c Z flag lt Not Load memory bit 9 adr bit 3 Store memory bit bit 3 0 Notes 1 ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Only the lower half word data is valid dddddddddddddadddddadd is the higher 21 bits of dip22 dddddddd is the higher 8 bits of disp9 The op code of this instruction uses the field of reg1 through the source register is shown as reg2 in the above table Therefore the meaning of register specification for mnemonic description and op code is different from that of the other instructions rrr regID specification RRRRR reg2 specification Preliminary Users Manual U15839EE1VOUMOO 597 Instruction Group Appendix A List of Instruction Sets Operand Opcode Table A 6 Instruction Set List 6 7 Operation Bit manip ulate bit 3 disp16 reg1 01bbb1111 1ORRRRR ddddddddd ddddddd adr lt GR reg1 sign extend disp16 Z flag lt Not Load memory bit adr bit 3 Store memory bit adr bit 3 Z flag bit 3 disp16 reg1 11bbb1111 10RRRRR ddddddddd adr lt GR regt sign extend disp16 Z flag lt Not Load memory bit
498. page 453 452 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 7 16 Bit Data Write Operation for Specific Registers 15 14 138 12 11 10 9 8 7 6 5 4 3 2 1 0 Ee TI ad COO 8 4 P3 E Bae Fu Sets the register bit n 0 No change of register bit n 1 Register bit n is set 1 Clears the register bit n 0 No change of register bit n 1 Register bit n is cleared 0 Sets clears the Register bit n Status of Register Bit n Register bit n is cleared 0 Register bit n is set 1 Others No change in register bit n value Remarks 1 lf only bits are to be cleared the 16 bit write access can be replaced by an 8 bit write access to the register address If only bits are to be set the 16 bit write access can be replaced by an 8 bit write access to the register address 1 Nevertheless for better vis ibility of the program code it is recommended to perform only 16 bit write accesses 2 nz0to7 Preliminary User s Manual U15839EE1VOUMOO 453 Chapter 14 FCAN Interface Function 14 3 2 Common registers 1 CAN stop register CSTOP The CSTOP register controls the clock supply of the FCAN system This register can be read written in 8 bit and16 bit units Figure 14 8 Stop Register CSTOP Address Initial 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OffsetNote value GEIOPESTPI 6 440 76 0 1 97 87 50 0 507 07 50 0
499. pcode Operation rrrrr110 imm16 1 OTIRRRRR GR reg2 saturated GR regt Saturated reg2 sign extend imm16 operation iiiiiiii rrrrr000 GR reg2 saturated GR reg1 100RRRRR GR reg2 result lt GR reg2 AND GR reg1 GR reg2 lt GR reg2 OR GR reg1 regi reg2 rrrrr00 rag 1y ego 011RRRR rrrrrO0O0 000 R 1 R 1 R regi reg2 imm16 regt GR reg2 GR reg1 OR zero reg2 extend imm16 19 2292 rrrrr001 GR 2 lt GR reg2 AND GR 010RRRRR regt regt reg2 rrrrrl110 imm16 reg1 110RRRRR GR reg2 lt GR reg1 AND reg2 zero extend imm16 Logic IlIIll1lITi operation eee rrrrr0010 GR reg2 GR reg2 XOR GR gt reg 01RRRRR reg1 rrrrri1101 imm16 regi OLRRRRR GR reg2 GR reg1 XOR reg2 zero extend imm16 JULI CL 5 rrrrr0000 regt 2 01RRRRR GR reg2 NOT GR reg1 rrrrrl111 11RRRRR GR reg2 GR reg2 logically 000000001 shift left by GR reg1 1000000 regi reg2 GR reg2 lt GR reg2 logically shift left by zero extend imm5 imm5 reg2 rrrrr0101 Notes 1 ddddddd is the higher 7 bits of disp8 dddddd is the higher 6 bits of disp8 ddddddddddddddd is the higher 15 bits of disp16 Only the lower half word data is valid ddddddddddddddddddddd is the higher 21 bits of dip22 dddddddd is
500. port in which input or output can be set in 1 bit units Besides functioning as an input output port in control mode P30 to P35 operate as the real time pulse unit RPU input output and external interrupt request input An operation mode of port or control mode can be selected for each bit and specified by the port 3 mode control register PMC3 a Port mode P30 to P35 can be set to input or output in 1 bit units using the port 3 mode register b Control mode P30 to P35 can be set to port or control mode in 1 bit units using to TOG04 Timer output Output These pins output a timer 0 pulse signal d TIGOO to TIGOS5 Timer input Input These pins are the timer 0 external capture trigger input pins e INPTOO INTPO5 Interrupt request from peripherals Input These are external interrupt request input pins Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions 4 P40 to P45 Port 4 Input output Port 4 is a 6 bit input output port in which input or output can be set in 1 bit units Besides functioning as an input output port in control mode P40 to P45 operate as the real time pulse unit RPU input output and external interrupt request input An operation mode of port or control mode can be selected for each bit and specified by the port 4 mode control register PMCA a Port mode P40 to P45 can be set to input or output in 1 bit units using the por
501. pression Description Overflow No overflow Carry Lower Less than CY 0 No carry No lower Greater than or equal Z 1 Zero Equal Z 0 Not zero Not equal CY OR 2 1 Not higher Less than or equal CY OR Z 0 Higher Greater than S21 Negative 20 Positive Always unconditional SAT 1 Saturated S XOR OV 1 Less than signed S XOR OV 0 Greater than or equal signed Less than or equal signed 592 S XOR OV OR Z 1 S XOR OV OR Z 0 Greater than signed Preliminary User s Manual U15839EE1VOUMOO Instruction Group Load store Appendix A List of Instruction Sets Operand disp7 ep reg2 Table A 6 Instruction Set List 1 7 rrrrr 0110 ddddddd Operation adr lt ep zero extend disp7 GR reg2 sign extend Load memory adr Byte disp8 reg2 rrrrr1000 ddddddd Note 1 adr lt ep zero extend disp8 GR reg2 sign extend Load memory adr Halfword disp8 ep reg2 rrrrr1010 Note 2 adr lt ep zero extend disp8 GR 2 Load memory Word disp16 reg1 reg2 rrrrr111000 RRRRR ddddddddd ddddddd adr lt GR reg1 sign extend disp16 GR reg2 lt sign extend Load memory adr Byte disp16 reg1 reg2 rrrrr1110 OIRRRRR Not
502. pter 3 CPU Function Table 3 6 List of Peripheral I O Registers 6 7 Bit Units Address Function Register Name for Manipulation aes 1 bit 8 bit 16 bit FFFF F68A Timer Count Register 1 TMG11 0000H FFFF F68C Capture Compare register 0 GCC10 0000H FFFF F68E Capture Compare register 1 GCC11 0000H FFFF F690 Capture Compare register 2 GCC12 0000H FFFF F692 Capture Compare register 3 GCC13 0000H FFFF F694 Capture Compare register 4 GCC14 0000H FFFF F696 Capture Compare register 5 GCC15 0000H FFFF F800 Peripheral command register PHCMD undefined FFFF F802 Peripheral status register PHS 00H FFFF F820 Power save mode register PSM 00H FFFF F822 Clock control register CKC FFFF F824 Clock generator status register CGSTAT FFFF F826 Watch dog clock control register WCC FFFF F828 clock control register PCC FFFF F82A Frequency modulation control register SCFMC FFFF F82C Frequency control 0 SCFCO FFFF F82E Frequency control 1 SCFC1 FFFF F830 Reset source monitor register RSM RIW x x 00H 01H FFFF F840 DMA trigger source select register 0 DTFRO R IW x x 00H FFFF F842 DMA trigger source select register 1 DTFR1 R IW x x 00H FFFF F844 DMA trigger source select register 2 DTFR2 R IW x x 00H FFFF F846 DMA trigger source select register 3 DTFR3 R IW x x 00H FFFF F880 Interrupt Mode Control
503. put A D conversion A D conversion stops ADCS bit of ADM register is cleared 0 ADCR ADCRL ADCRH registers INTAD interrupt Conversion start Conversion stop ADCS bit of ADM register is set 1 ADCS bit of ADM register is cleared 0 ADS3 to ADSO bits of ADS register are cleared 0 Preliminary User s Manual U15839EE1VOUMOO 539 Chapter 15 A D Converter Figure 15 12 write operation is made to the ADS register during A D conversion operation Write operation to ADS register ADSO bit is set 1 Data 2 ANIO Input Data 1 ANI Input Data 5 A D conversion ADCR ADCRL ADCRH registers INTAD interrupt Conversion start Conversion operation stopped ADCS bit of ADM register is set 1 conversion operation started with ADSS to ADSO bits of ADS register new setting of ADS register are cleared 0 540 Preliminary User s Manual U15839EE1VOUMOO Chapter 15 A D Converter 15 6 A D Converter Precautions 1 2 3 4 C 100 to 1000 pF A Current consumption in standby mode A D converter current consumption can be reduced by stopping the A D conversion operation A D conversion operation is stopped by resetting the ADCS bit of the A D converter mode register ADM to 0 Input range of ANIO to ANI11 Keep the input voltage of the ANIO through ANI11 pins to within the rated range If a input voltage greater than AVpp or low
504. r bit set clear function CAN bus activity register bit set clear function J S D D gt Z CAN bit rate prescaler register in initialisation state only ISTAT bit 1 CAN bus diagnostic in diagnostic mode information register only C2DINF CAN synchronization control C2SYNC register Note The address of a CAN module 2 register is calculated according to the following formula effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO 435 Chapter 14 FCAN Interface Function Table 14 7 Relative Addresses of CAN Module 3 Registers Access Type Address Note2 Offset 1 bit 8 bits Comment C3MASKLO CAN3 mask 0 register L lower half word C3MASKHO CAN3 mask 0 register upper half word C3MASKL1 CAN3 mask 1 register L lower half word C3MASKH1 mask 1 register upper half word C3MASKL2 CAN3 mask 2 register L lower half word C3MASKH2 CAN3 mask 2 register upper half word C3MASKL3 CAN3 mask 3 register L lower half word C3MASKH3 CAN3 mask 3 register H upper half word control register bit set clear function C3DEF CANS definition register bit set clear function C3LAST CANG information register C3ERC CANS error counter register read only read only C3IE CANS interrupt enable register bit set clear function
505. r on page 486 Bit Position Bit Name Function Sets the CAN module mask option for the identifier type of the receive message 0 Check identifier type of a received message 15 1 Do not check identifier type CXMASKHn Remark When CMIDE is cleared 0 the specified identifier type standard or extended of the message buffer linked to this CAN mask register must match the identifier type of the received message in order to accept it for that message buffer Sets the CAN module mask option for the corresponding identifier bit ID28 to IDO of the receive message 0 Check identifier bit of a received message 1 Do not check identifier bit Remarks 1 When CMIDn is cleared 0 the specified identifier bit of the message buffer linked to this CAN mask register must match the identifier bit of 12 to 0 the received message in order to accept it for that message buffer CxMASKHn CMID28 to When a receive message buffer is linked to a mask always 29 bits of 15100 CMIDO the specified identifier in the M IDHm M IDLm registers of the mes CXMASKLn sage buffer are compared with the identifier of the received message even if a standard format 11 identifier bits is set In case standard for mat identifier is selected IDE 0 the lower 18 bits in the M IDm reg ister contain a copy of data field bits so that an address extensions by means of data field bits is possible When a mask is exclusively intended for
506. r 14 FCAN Interface Function 14 2 6 Message handling In the FCAN system the assignment of message buffers to the CAN modules is not defined by hard ware Each message buffer in the message buffer section can be assigned to any CAN module by soft ware The message buffers have individual configuration registers to assign the CAN module and to specify the message buffer type Basically a message buffer can be selected as a transmit message buffer or as a receive message buffer For receive message buffers there are further differentiations according to the mask links 1 Message transmission According to the CAN protocol the highest prior message must always gain the CAN bus access against lower prior messages sent by other nodes at the same time due to arbitration mechanism of CAN protocol and against messages waiting to be transmitted in the same node i e inner pri ority inversion The FCAN system scans the message buffer section at the beginning of each message transmit to analyse that no other message with a higher priority is waiting to be transmitted on the same CAN bus The FCAN system avoids inner priority inversion automatically Example 5 transmit messages are waiting to be sent at the same time in the example shown in Table 14 10 Example for Automatic Transmission Priority Detection on page 444 Although the priority of the transmit messages are not sorted according any scheme the sequence of transmits on the CAN bus
507. r Manipulation Initial Value 1 bit 8 bit 16 bit xxxxn000H message event pointer 000 M EVTO00O Undefined xxxxn001H message event pointer 001 M EVTO001 Undefined xxxxn002H message event pointer 002 M EVTO002 Undefined xxxxn003H CAN message event pointer 003 M EVTO00S Undefined xxxxn004H message data length register 00 M DLCOO Undefined xxxxn005H message control register 00 M CTRLOO Undefined xxxxn006H message time stamp register 00 M TIMEOO Undefined Xxxxn008H message data register 000 M DATAO00 X Undefined xxxxn009H message data register 001 M DATAO01 X Undefined Xxxxn00AH message data register 002 M_DATA002 X Undefined xxxxn0OBH message data register 003 M DATAO03 X Undefined xxxxn0OCH message data register 004 M_DATA004 x Undefined xxxxn00DH message data register 005 M_DATA005 X Undefined XxxxxnOOEH message data register 006 M DATAO06 R W X Undefined XxxxnOOFH message data register 007 M DATAO07 R W X Undefined xxxxn010H CAN message ID register LOO M IDLOO R W x Undefined xxxxn012H message ID register M IDHOO RAN x Undefined xxxxn014H message configuration register 00 M CONFOO R W x Undefined xxxxn015H message status register 00 M STATOO R X Undefined xxxxn016H status set cancel register 00 SC STATOO W 0000 Xxxxn020H message event pointer 010 M EVTO10 R W X Undefined xxxxn021H mess
508. r Used by compiler when calling function PC Program counter Holds instruction address during program execution 2 Program counter This register holds the instruction address during program execution The lower 26 bits of this register are valid and bits 31 to 26 are fixed to If a carry occurs from bit 25 to 26 it is ignored Bit 0 is fixed to 0 and branching to an odd address cannot be performed Figure 3 2 Program Counter PC 31 2625 10 1 After reset PC Fixed to 0 Instruction address during execution 00000000H Preliminary User s Manual U15839EE1VOUMOO 57 Chapter 3 CPU Function 3 2 2 System register set System registers control the status of the CPU and hold interrupt information To read write these system registers use the system register load store instruction LDSR or STSR instruction with a specific system register number indicated below Table 3 2 System Register Numbers Operand Specification System Register Name LDSR Instruction STSR Instruction Status saving register during interrupt EIPC Nete 1 Status saving register during interrupt EIPSW Status saving register during NMI FEPC Status saving register during NMI FEPSW Interrupt source register ECR Program status word PSW Reserved number for future function expansion operations that access these register numbers cannot be guaranteed Status saving register during CALLT execution
509. r consists of a comparator stage which compares the input pin level against a delayed input pin level The filter output follows the filter input if this compare operation matches 8 4 2 Interrupt Trigger Mode Selection The valid edge of the INTP pins can be selected by the program The edge that can be selected as the valid edge is one of the following e Rising edge Falling edge Both the rising and the falling edges 222 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function 8 4 8 Interrupt Edge Detection Control Registers Valid interrupt edges can be selected by INTMO to INTM3 registers Masking of interrupts is done inside the concerning interrupt control registers xxIC 1 Interrupt mode register 0 INTMO Figure 8 17 Interrupt Mode Register 0 IMTMO 7 6 5 4 3 2 1 0 Address Initial value Edge selection for INTP3 to interrupt controller Selects active edge for interrupt generation Edge selection Falling edge Rising edge Reserved Both edges Edge selection for INTP2 to interrupt controller ES021 ES020 Edge selection 0 0 Falling edge 0 1 Rising edge Reserved Both edges 1 to interrupt controller Edge selection Falling edge Rising edge Reserved Both edges Edge selection Falling edge Rising edge Reserved Both edges Note Programming edge detection or port mode register ca
510. r factor register O 179 7 2 9 DMA trigger factor register 1 1 180 7 2 10 DMA trigger factor register 2 2 181 7 2 11 DMA trigger factor register 182 7 3 Next Address Setting 183 7 4 DMA Bug States a 22s eee ee eet Ae qu bet EIE 184 Thl Types of bus states vxo se of sab ie al ghee bbe eens ie Rie bE E Aer be E Xt 184 7 4 2 DMAC bus cycle state 5 186 7 5 TransterMode cess ets see inl eR GRE ELI A ren 187 7 5 1 Single transfer 187 7 5 2 Single step transfer 189 75 3 Line Transfer Mode eis hid p 190 755 4 Block transfer mode ect epe t aeos epe GE 192 1 6 Transfer Types sere 193 TON Two cycletranster lx eR are ee re be VERI FR Re E RR Rd Me 193 7 7 ansterODbject 2 e e ER TEIG EN IE RN RERUM a 193 7 1 Transfer type and transfer 193 7 8 DMA Channel Priorities 194 7 9 DMA Transfer Start 5 19
511. r processing with a CAN bridge 8 bit event pointer 1 for processing with a CAN bridge 8 bit event pointer 2 for processing with a CAN bridge 8 bit event pointer 3 for processing with a CAN bridge Remark m 00to 31 Note V850E CA2 Jupiter has no CAN bridge implemented Therefore the Message Event Bytes have no function To avoid unexpected settings of the ERQ flag it is recommended to initialize all Message Event Bytes with the value 0x00 at the first initialization and let that initialization unchanged always 484 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 3 5 CAN Module Registers 1 CAN 1 to 4N te mask 0 to 3 registers L CXMASKLO to CXMASKL3 CXMASKHO to CxMASKH3 1 to 4Nete The CxMASKLO to CXMASKL3 and CxMASKHO to CxMASKHS registers specify the four accept ance masks for each CAN module x 1 to 4Netej For more details refer to chapter 14 2 7 Mask handling on page 448 These registers can be read written in 8 bit and 16 bit units Figure 14 33 CAN 1 to 4 Mask 0 to 3 Registers L H CxMASKLO0 to CXMASKL3 to CXMASKHS x 1 to 4 Address Initial Offset value cuneos pun v T s poepoe oe poes paa baee MGR CADO o n unde Table 14 17 on page 486 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 54 13 12 cd 10 9 8 7 6 5 4 3 2 1 US DBM SMOSH oMDS OMT TOS Ni DW te 14 17 unde
512. ransmit data is even 1 During reception The number of bits with the value 1 within the receive data including the parity bit is counted and a parity error is generated if this number is even parity During transmission the parity bit is set to 0 regardless of the transmit data During reception no parity bit check is performed Therefore no parity error is generated regardless of whether the parity bit is 0 or 1 d No parity No parity bit is added to the transmit data During reception the receive operation is performed as if there were no parity bit Since there is no parity bit no parity error is generated Preliminary User s Manual U15839EE1VOUMOO 7 Internal signal A Internal signal B Chapter 13 Serial Interface Function Receive data noise filter The RXD5n signal is sampled at the rising edge of the prescaler output basic clock Clock If the same sampling value is obtained twice the match detector output changes and this output is sampled as input data Therefore data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit see Figure 12 15 Refer to 12 2 6 1 a Basic clock Clock regarding the basic clock Also since the circuit is configured as shown in Figure 12 14 internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status Figure 13 14 Noise Filter Circuit
513. rated when the count value of TMGn0 TMGn1 toggles from FFFFH to 0000H In match and clear mode the INTTMGnO INTTMGn1 interrupt is generated when the count value of TMGnO TMGn1 matches the GCC1 value PWM output function Control of the outputs of TOGn1 through TOGn4 pin in the compare mode PWM output can be performed using the compare match timing of the GCCn1 to GCCn4 register and the corresponding timebase TMGn0 TMGn 1 Output delay operation A clock synchronized output delay can be added to the output signal of pins TOGn1 to TOGn4 This is effective as an EMI counter measure Edge detection and noise elimination filter External signals shorter than 1 count clock fecoun not fpc are eliminated as noise Note The TOGn1 to TOGn4 and TOGn1 to TOGn4 are each alternate function pins Figure 10 24 Block Diagram of Timer Gn on page 308 shows the block diagram of Timer Gn Preliminary User s Manual U15839EE1VOUMOO 307 Chapter 10 Timer Figure 10 24 Block Diagram of Timer Gn 1 16 bit Architecture fecu 2 fecu 4 i INTTMGnO fecu 8 COUNTO s feci 16 TMGnO 1 6 bit fecu 32 fecu 64 fea 128 INTCCGnO Noise Elimination GCCn0 16 bit TGO Edge Detection capture compare INTCCGn1 gt Een Control INTCCGn2 Ly Noise Elimination GCCn1 16 bit TIGn1 Edge Detection capture compare
514. ration Description 591 Symbols Used for Flag Operation seen 591 Condition CodeS EC 592 Instr ction Set EIst eii cct ien epe D hc Pede a TERR Re ved a eee Pine ede dee 593 Preliminary User s Manual U15839EE1VOUMOO Chapter 1 Introduction The V850E CA2 Jupiter is a product in NEC s V850 family of ROM less microcontrollers designed for Automotive applications 1 1 General The V850E CA2 Jupiter Rom less microcontroller is a member of NEC s V850 32 bit RISC family which match the performance gains attainable with RISC based controllers to the needs of embedded control applications The V850 CPU offers easy pipeline handling and programming resulting in com pact code size comparable to 16 bit CISC CPUs The V850E CA2 Jupiter offers an excellent combination of general purpose peripheral functions like serial communication interfaces UART clocked SI and measurement inputs A D converter with dedicated CAN network support The device offers power saving modes to manage the power consumption effectively under varying conditions Thus equipped the V850E CA2 Jupiter is ideally suited for automotive applications like dashboard or body It is also an excellent choice for other applications where a combination of sophisticated periph eral functions and CAN network support is required 1 V850E CPU The V850E CPU supports the RISC instruction set and through the
515. re 10 14 Figure 10 15 Figure 10 16 Figure 10 17 Figure 10 18 Figure 10 19 Figure 10 20 Figure 10 21 Figure 10 22 Figure 10 23 Figure 10 24 Figure 10 25 Figure 10 26 Figure 10 27 Figure 10 28 Figure 10 29 Figure 10 30 Figure 10 31 Figure 10 32 Figure 10 33 Figure 10 34 Figure 10 35 Figure 10 36 Figure 10 37 Figure 10 38 Figure 10 39 Figure 10 40 Figure 10 41 Figure 10 42 Figure 10 43 Figure 10 44 Figure 10 45 Figure 10 46 Figure 10 47 Figure 10 48 Figure 10 49 Figure 10 50 Figure 10 51 Figure 10 52 Sub Watch mode released by RESET input sse 263 Sub Watch mode release by Watchdog reset NMI 264 STOP mode released by RESET input sss eese 266 STOP mode release by Watchdog reset NMI 267 Power Save Control Register PSC 268 Power Save Mode Register PSM sse 270 Block Diagram of Timer 273 Timer C counter TMCO enne ennt enn 274 Capture Compare Register 0 276 Capture Compare Register 1 CCCO1 ssssssssssssseseeeeeeennnnnn nnns 276 Timer C control Register 0 1 2 sss 278 Timer C
516. re 13 27 Clocked Serial Interface Read Only Reception Buffer Registers Low SIRBELO to SIRBEL 1 Initial value SIRBELO SIRBE7 SIRBE6 SIRBE5 SIRBE4 SIRBES SIRBE2 SIRBE1 SIRBEO FFFF FDO06H OOH SIRBEL1 SIRBE7 SIRBE6 SIRBE5 SIRBE4 SIRBE3 SIRBE2 SIRBE1 SIRBEO FFFF FD46H SIRBEL2 SIRBE7 SIRBE6 SIRBES5 SIRBE4 SIRBES SIRBE2 SIRBE1 SIRBEO FFFF FD86H 00H 7 6 5 4 3 2 1 0 Address SIRBE7 to SIRBEO Store receive data Cautions 1 The receive operation is not started even if data is read from the SIRBELn register 2 The SIRBEL n register can be read only if the 8 bit data length has been set CCL bit of CSIMn register 0 Preliminary User s Manual U15839EE1VOUMOO 401 Chapter 13 Serial Interface Function 7 Clocked serial interface transmission buffer registers SOTBO to SOTB2 The SOTBn register is a 16 bit buffer register that stores transmit data n 0 to 2 When the transmission reception mode is set TRMD bit of CSIMn register 1 the transmission operation is started by writing data to the SOTBn register This register can be read written in 16 bit units Figure 13 28 Clocked Serial Interface Transmission Buffer Registers to SOTB2 14 13 12 8 7 5 4 3 2 dress value 5 M 403 12 8 7 5 4 3 2 1 Address 1 value SOTBI FFFFFD44H 0000H 15004 49 10 9 8 7 8 8 4 3 2 1 0 Address MEA value
517. red by set ting registers with software WATCH mode In this mode the clock generator PLL and SSCG stops operation Therefore the entire system excluding Watch timer Watchdog timer unit stops This mode provides low power consumption where the power consumed is only from OSC Main oscillator Sub Oscillator and Watch timer Watchdog timer circuit This mode is entered by setting registers with software SUB WATCH mode In this mode the clock generator PLL and SSCG stops operation Therefore the entire system excluding Watch timer Watchdog timer unit stops This mode provides ultra low power consump tion where the power consumed is only from the Sub Oscillator and Watch timer Watchdog timer circuit This mode is entered by setting registers with software Software STOP mode In this mode the main clock generator is stopped and the entire system stops This mode provides ultra low power consumption where the power consumed is only leakage current and Sub Oscilla tor operation if a crystal is connected This mode is entered by setting registers with software Preliminary User s Manual U15839EE1VOUMOO 253 Chapter 9 Clock Generator 9 4 3 Power Saving Mode Functions The Clock Controller supports 3 type of standby modes IDLE WATCH STOP The behaviour of all out put clocks is described in the following tables Table 9 2 Power Saving Mode Functions Condition release release release release settings of norm
518. register see 8 3 6 In service priority register ISPR on page 220 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction dur ing maskable interrupt processing in order to restore the PC and PSW correctly dur ing recovery by the RETI instruction it is necessary to set PSW EP back to 0 and PSW NP back to 0 using the LDSR instruction immediately before the RETI instruc tion Remark The solid lines show the CPU processing flow Preliminary User s Manual U15839EE1VOUMOO 211 Chapter 8 Interrupt Exception Processing Function 8 3 3 Priorities of maskable interrupts The V850E CA2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced Multiple interrupts can be controlled by priority levels There are two types of priority level control control based on the default priority levels and control based on the programmable priority levels that are specified by the interrupt priority level specification bit xxPRn of the interrupt control register xxICn When two or more interrupts having the same prior ity level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level before hand For more information refer to Table 8 1 Interrupt Exception Source List on page 200 The programmable priority control customizes inte
519. reliminary User s Manual U15839EE1VOUMOO 439 Chapter 14 FCAN Interface Function The interrupt pending registers of the FCAN system are CGINTP Global interrupt pending register C1INTP CAN module 1 interrupt pending register C2INTP CAN module 2 interrupt pending register CAN module interrupt pending register CAINTP CAN module 4 interrupt pending register Additionally the entire interrupt pending flags are summarized in one register the CAN interrupt pend ing register CCINTP However the CCINTP register is a read only register and cannot be used for clearing the interrupt pending flags For details on the interrupt pending registers refer to the chapter 14 3 3 CAN interrupt pending regis ters on page 467 440 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 14 2 5 Time stamp The FCAN system offers a time stamp capture capability at message reception and transmission The time stamp capture function is used to realize a synchronized global clock in a CAN network also called global time system However the development and functionality of such a global clock system has to be implemented by the user For time stamp capturing at message reception two trigger events are selectable see Figure 9 5 The counter value of the CAN global time system counter CGTSC is either captured upon the start of frame signal SOF of the receive message or it is captured at the time t
520. required for the CPU BCU clock supply the setting of the bits SCPSO SCPS1 0x00 is not supported at any time Therefore the setting of these bits must be modified before the SSCG is enabled SCFMCA Specifies the dithering frequency to SCFMCO The initial setting 0x0A of these bits must not be changed at any time Cautions 1 This register can only be written if the SSCG enable bit SCEN is cleared 2 After the first initialization of the SCFMC register no further write access is allowed until the occurrence of a Reset or the release of a power save mode hap pened Afterwards a power save mode has been released one bit is allowed to be changed 248 Preliminary User s Manual U15839EE1VOUMO00 Chapter 9 Clock Generator 9 3 7 SSCG Frequency Control Register 0 SCFCO This is an 8 bit register that controls the first frequency divider of the SSCG It determines the lower SSCG output frequency in dithering mode This register can be read or written in 8 or 1 bit units Figure 9 8 SSCG Frequency Control Register 0 SCFCO Initial value 7 6 5 4 3 2 1 0 Address Specifies the first frequency divider of the SSCG fx 4 MHz SCFCO7 to SCFCO0 Lower SSCG frequency fx 003EH 126 MHz SCFCO7 to fy 5 MHz scrcoo x 5 MHz SCFC07 to SCFC00 Lower SSCG frequency fx 0031H 125 MHz The initialization of the SCFCO register depends to the output frequency supplied by the main oscillation circuit Th
521. rescaler register C2BRP 0000H xxxxn109DH CAN bus diagnostic information register C2DINF 0000H xxxxn109EH CAN synchronization control register C2SYNC 0218H xxxxn10COH CAN3 address mask register LO Note 2 C3MASKLO Undefined xxxxn10C2H CANS address mask register Note 2 C3MASKHO Undefined xxxxn10C4H CANG address mask register L1 Note 2 C3MASKL1 Undefined xxxxn10C6H CANG address mask register H1 Note 2 C3MASKH1 Undefined xxxxn10C8H CANG address mask register L2 Note 2 C3MASKL2 Undefined xxxxn10CAH CANS address mask register H2 Note 2 C3MASKH2 Undefined xxxxn10CCH CAN3 address mask register L3 Note 2 C3MASKL3 Undefined xxxxn10CEH CANG address mask register Note 2 Undefined xxxxn10DOH CANG control register Nete 1 2 C3CTRL 0101H xxxxn10D2H CANG definition register Note 1 2 C3DEF 0000H xxxxn10D4H CANG information register Note 2 C3LAST 00FFH xxxxn10D6H CANG error counter register Nete 2 C3ERC 0000H xxxxn10D8H CANG interrupt enable register Note 1 2 0000H xxxxn10DAH Note 2 CANS bus active register C3BA 00FFH xxxxn10DCH CANG bit rate prescaler register Nete 2 C3BRP 0000H xxxxn10DDH CANS bus diagnostic information register Note 2 Preliminary User s Manual U15839EE1VOUMOO
522. ring the TMCO register value in the CCCO1 register When this value is captured an INTCCCO 1 interrupt is generated Preliminary User s Manual U15839EE1VOUMOO 287 Chapter 10 Timer Calculation The cycle of signals input to the INTCCCOO pin is calculated by obtaining the difference between the TMCO register s count value Dx that was captured in the CCCOO register according to the x th valid edge input of the TICOO pin and the TMCO register s count value 1 that was captured in the CCCOO register according to the x 1 th valid edge input of the TICOO pin and multiplying the value of this difference by the cycle of the clock control signal Similarly the cycle of signals input to the INTCCC01 pin is calculated by obtaining the difference between the TMCO register s count value Dx that was captured in the CCCO1 register according to the x th valid edge input of the TICO1 pin and the TMCO register s count value D x 1 that was captured in the CCCO1 register according to the x 1 th valid edge input of the TICO1 pin and multiplying the value of this difference by the cycle of the clock control signal Figure 10 12 Timing of cycle measurement operation FFFFHIO000HI0001H God TMCO j0000H start TICOO input CCCO0 register INTCCCOO interrupt INTTMCO interrupt 10000H D1 D2 x t DO xt No overflow Overflow occurs No overflow Caution An overflow must not be generated
523. riting of the CSEn2 to CSEn0 bits n 0 1 of TMGMHn register is prohibited These bits set the prescaler for the Timer Gn counter The rewriting of the CCSGy bits y 0 to 5 is prohibited This bits OCTLGnL and OCTLGnH registers set the capture mode or the compare mode to the GCCy register For the GCCn0 register and the GCCn5 register these bits TMGMLn register set the free run or match and clear mode of the TMGnO and TMGn1 counter The rewriting of the TMGCMnL and the TMGCMHn register is prohibited These registers configure the counter or TMGn1 for the GCCnm register m 1 to 4 and define the edge detection for the TIGM input pins falling rising both Even when POWER bit is set TOGnm output is switched by switching the ALVGm bit of OCTLGnL and OCTLGnH registers These bits configure the active level of the TOGnm pins m 1 to 4 When POWER bit and bit are set x 0 1 The rewriting of ALVGm is prohibited m 1 to 4 These bits configure the active level of the TOGnm pins m 1 to 4 When in compare mode the rewriting of the or GCCn5 register is prohibited In compare mode these registers set the value for the match and clear mode of the and TMGn 1 counter Functionality When the POWER bit is set to 0 regardless of the SWFGm bit OCTLGnL and OCTLGnH registers the TOGnm pins are tied to the inactive level The SWFGm bit enables or disables the outpu
524. rity Output even parity Judge as even parity Cautions 1 To overwrite the PS1 and PSO bits first clear 0 the and RXE bits 2 If 0 parity is selected for reception no parity judgment is performed Therefore no error interrupt is generated because the PE bit of the ASISn register is not set Even parity If the transmit data contains an odd number of bits with the value 1 the parity bit is set 1 If it contains an even number of bits with the value 1 the parity bit is cleared 0 This controls the number of bits with the value 1 contained in the transmit data and the parity bit so that it is an even number During reception the number of bits with the value 1 contained in the receive data and the parity bit is counted and if the number is odd a parity error is generated Odd parity In contrast to even parity odd parity controls the number of bits with the value 1 contained in the transmit data and the parity bit so that it is an odd number During reception the number of bits with the value 1 contained in the receive data and the parity bit is counted and if the number is even a parity error is generated Remark When reception is disabled the reception shift register does not detect a start bit No shift in processing or transfer processing to the reception buffer register RXBn is performed and the contents of the RXBn register are retained When reception is enabled
525. rity DMA transfer request is generated within one clock after the end of a single transfer even if the previous higher priority DMA transfer request signal stays active this request is not prioritized and the next DMA transfer after the bus is released for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figure 7 16 Single Transfer Example 1 on page 187 shows a DMAC transfer in single transfer mode In this example the DMA channel 3 is used for a single transfer Figure 7 16 Single Transfer Example 1 DMA Transfer Request CH3 Note Note te PU DMA channel 3 terminal count Figure 7 17 Single Transfer Example 2 on page 187 shows DMAC transfers in single transfer mode in which a higher priority DMA transfer request is generated DMA channels 0 to 2 are used for a block transfer and channel 3 is used for a single transfer Figure 7 17 Single Transfer Example 2 DMA Transfer Request CHO DMA Transfer Request CH1 DMA Transfer Request CH2 DMA Transfer Request CH3 DMA channel 1 DMA channel 3 terminal count terminal count DMA channel 0 DMA channel 2 terminal count terminal count Note The bus is always released Preliminary User s Manual U15839EE1VOUMOO 187 Chapter 7 DMA Functions DMA Controller Figure 7 18 Single Transfer Example 3 on page 188 shows a DMA transfer example in single transfer mode in which a lower priority DMA transfer request is
526. roduced in any form or by any means without prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC Electronics no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers
527. rogrammable peripheral I O area overlaps the following areas the pro grammable peripheral I O area becomes ineffective Peripheral I O area ROM area RAM area 4 Programmable peripheral I O area address setting is enabled only once Do not change address in the middle of a program M xx00B N xx11B Preliminary User s Manual U15839EE1VOUMOO 113 Chapter 4 Bus Control Function 1 Peripheral area selection control register BPC This register can be read written in 16 bit units Figure 4 4 Peripheral Area Selection Control Register BPC 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 Address Initial value REC EATE ZU EA PATA PATI DATO PAS ASI PT RAS PAS BAI Bit Position Bit Name Function Enables disables usage of programmable peripheral I O area 0 Disables usage of programmable peripheral I O area 1 Enables usage of programmable peripheral I O area PA13 to PAO Specifies the bit 27 to bit 14 of the starting address of the programmable periph eral I O area The other bits are fixed at zero Remark The recommended setting for the peripheral area selection control register BPC is x8600H With this configuration the effective start address of the programmable peripheral area is mapped to x1800000H 114 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 5 Bus Cycle Type Control Function In the V850E CA2 Jupiter the following external devices can be connecte
528. rr 85985858725 zz czccccecz0 lt lt lt lt lt ass E rece see amp PR IS IS IS OM IM IS IS OO cO o Qo oo ow N DO er 010 s s amp gt gt gt C o r x wo P43 TIG13 TOG13 1 AVop 2 O P42 TIG12 TOG12 AVss 3 PA1 TIG11 TOG11 MODE 4 P56 TOCOO PAHO A16 5 P65 SI02 A15 4 6 P66 SO02 A14 7 P67 8CK02 A13 8 VDD51 12 Vss51 11 P11 FCTXD1 A10 P10 FCRXD1 A9 P13 FCTXD2 PAH4 A20 P12 FCRXD2 P15 FCTXD3 Note Vssso P14 FCRXD3 Note PCTO LWR P51 FCTXD4 Note RESOUT P50 FCRXD4 Note PCMO WAIT e V850E CA2 Jupiter pus P34 TIGO4 TOGO4 P33 TIGOS TOGO3 23 5101 P24 SO01 P25 SCK01 P20 SI00 P21 SO00 P22 SCK00 VDD50 Vss50 P32 TIG02 TOG02 P31 TIG01 TOG01 P35 TIG05 INTP05 Vss31 19 2 18 A8 _ A7 A6 A5 A4 lt A2 A1 PCS0 CS0 PCT4 RD Vona m P52 INTP4 Ves e P64 INTP3 P63 INTP2 D8 e o N No TORRES LOTS G a a SOR gaaqgaqrartrar raragggana
529. rrupt processing in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 0 and PSW NP back to 1 using the LDSR instruction immediately before the RETI instruc tion Remark The solid line indicates the CPU processing flow 2 NMIWDT Restoring by RETI instruction is not possible Perform a system reset after interrupt servicing Preliminary User s Manual U15839EE1VOUMOO 207 Chapter 8 Interrupt Exception Processing Function 8 2 3 Non maskable interrupt status flag NP The NP flag is a status flag that indicates that non maskable interrupt NMI processing is under execu tion This flag is set when an NMI interrupt has been acknowledged and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged Figure 8 4 Non maskable Interrupt Status Flag NP Initial value a aa n 876543210 Indicates whether NMI interrupt processing is progress 7 0 No NMI interrupt processing 1 NMI interrupt currently being processed 8 2 4 Edge Detection Function The behaviour of the non maskable interrupt NMIO can be specified by the interrupt mode register 3 The valid edge of the external NMI pin input can be specified by the ESNO bit The register can be read written in 8 bit or 1 bit units Figure 8 5 Interrupt Mode Register 3 INTM3 Initial value 7 6 5 4 3 2 1 0 Address Specifies the NMI pin s valid
530. rrupt requests into eight levels by setting the priority level specification flag Note that when an interrupt request is acknowledged the ID flag of PSW is automatically set to 1 Therefore when multiple interrupts are to be used clear the ID flag to 0 beforehand for example by placing the El instruction in the interrupt service program to set the interrupt enable mode 212 Preliminary User s Manual U15839EE1VOUMOO Chapter8 Interrupt Exception Processing Function Figure 8 8 Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Processed 1 2 Main routine EI E Processing of a Processing of b Interrupt request a Interrupt level 3 request b Interrupt request b is acknowledged because the level 2 priority of b is higher than that of a and interrupts are enabled Processing of c Interrupt request c interrupt request d Wo n level 3 level 2 Although the priority of interrupt request d is higher n cM than that of c d is held pending because interrupts are disabled Processing of d Processing of e ZI Interrupt request e P Interrupt request f Interrupt request f is held pending even if interrupts are level 2 eel o enabled because its priority is lower than that of e Processing of f Processing of g El Interrupt request g Interrupt request h level 1 level 1 Interrupt request h is held pending ev
531. s Figure 16 6 Type E Block Diagram WR Q PMCCMn WR e PMCMn WR Pcun PCMn Selector RD pemn Address WAIT C 4 Preliminary User s Manual U15839EE1VOUMOO 555 Chapter 16 Port Functions 16 3 Pin Functions of Each Port 16 3 1 Port 1 Port 1 is a 8 bit input output port in which input or output can be specified in 1 bit units Each port bit can be independently configured to port input port output or peripheral functionNete 1 This register can be read or written in 1 bit and 8 bit units Figure 16 7 Port 1 P1 Address At Reset 7 6 5 4 3 2 1 0 i FFFFFAO0H ooHNet2 Pin n 7 to 0 Input output port Remark In Input Mode When the P1 register is read the pin levels at that time are read Writing to the P1 register writes the values to that register This does not affect the input pins In Output Mode When the P1 register is read the values of P1 are read Writing to the P1 register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as the serial interface UART1 FCAN1 FCAN2 3 input output 1 Operation in control mode Alternate Pin Name Remarks Block Type CRXD1 CTXD1 CRXD2 CTXD2 Serial interface UART1 FCAN1 FCAN2 CRXD3Note 2 FCAN3Nete 2 input output
532. s CSIOO to CSI02 channels FCAN controller 4 channels Remark For details about the FCAN controller refer to Chapter 13 FCAN Interface Function UART50 and UART51 transmit receive 1 byte serial data following a start bit and support full duplex communication CSI00 to CSIO2 perform data transfer according to three types of signals namely serial clocks to 2 serial inputs 5100 to S102 and serial outputs 5000 to 5002 3 wire serial I O FCAN conforms to CAN specification Version 2 0 Part B and provides 64 message buffers Preliminary User s Manual U15839EE1VOUMOO 363 Chapter 13 Serial Interface Function 13 2 Asynchronous Serial Interfaces UART5n UART50 UART51 13 2 1 Features Transfer rate 300 bps to 625 Kbps using a dedicated baud rate generator and an internal peripheral clock of 20 MHz Full duplex communications On chip reception buffer register RXBn On chip transmission buffer register TXBn e Two pin configuration TXD5n Transmit data output pin RXD5n Receive data input pin e Reception error detection functions Parity error Framing error Overrun error Interrupt sources types Reception error interrupt INTSERn Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSRn Interrupt is generated when receive data is transferred from the shift register to the reception b
533. s the following areas ROM area area Peripheral I O area Programmable peripheral I O area 2 The bits marked as 0 are reserved They have to leave to 0 Note 0107 118 Preliminary User s Manual U15839EE1VOUMOO Chapter 4 Bus Control Function 4 7 1 Bus width The V850E CA2 Jupiter accesses peripheral I O and external memory in 8 bit 16 bit or 32 bit units The following shows the operation for each type of access Access all data in order starting from the lower order side 1 Byte access 8 bits a When the data bus width is 16 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 Address Address 15773 15 TE 2n 1 8 8 7 7 7 zal 2n 0 0 0 Byte data External Byte data External data bus data bus b When the data bus width is 8 bits Little Endian 1 Access to even address 2n 2 Access to odd address 2n 1 Address Address 7 7 7 7 2n 2n 1 0 0 0 0 Byte data External Byte data External data bus data bus Preliminary User s Manual U15839EE1VOUMOO 119 120 Chapter 4 Bus Control Function c When the data bus width is 16 bits Big Endian 1 Access to even address 2n 2 Access to odd address 2n 1 Address Address 15 1577 2 8 Po 7 Ya 7 7 a 2n 1 0 Or 0 0 Byte data External Byte data External data bus data bus d When the data bus width is 8 bits Big Endian lt 1 gt Access to even
534. s Manual U15839EE1VOUMOO 73 Chapter 3 CPU Function 3 Internal peripheral I O area 4 KB of memory addresses SFFF000H to 3FFFFFFH is provided as an internal peripheral I O area Figure 3 13 Internal Peripheral I O Area 3FF FFFFH Internal Peripheral I O area 4 Kbytes 3FF 0000H Peripheral I O registers associated with the operation mode specification and the state monitoring for the internal peripherals I O all memory mapped to the internal peripheral I O area Program fetches cannot be executed from this area Cautions 1 3 In the V850E CA2 no registers exist which are capable of word access But if a register is word accessed half word access is performed twice in the order of lower address then higher address of the word area ignoring the lower 2 bits of the address For registers in which byte access is possible if half word access is executed the higher 8 bits become undefined during the read operation and the lower 8 bits of data are written to the register during the write operation Addresses that are not defined as registers are reserved for future expansion If these addresses are accessed the operation is undefined and not guaranteed Addresses 3FF F000H to 3FF FFFFH cannot be specified as the source destina tion address of DMA transfer Be sure to use addresses FFF F000H to FFF FFFFH for source destination address of DMA transfer Additionally to the peripheral I O area a 16 KB
535. s case no reception completion interrupt request INTSRn is generated Generate a reception completion interrupt request INTSRn as an interrupt when an error occurs In this case no reception error interrupt request INTSERn is generated Caution To overwrite the ISRM bit first clear 0 the RXE bit Preliminary User s Manual U15839EE1VOUMOO 369 Chapter 13 Serial Interface Function 2 Asynchronous serial interface status registers ASISO to ASIS2 The ASISn register which consists of 3 bit error flags PE FE and OVE indicates the error status when UART5n reception is completed The status flag which indicates a reception error always indicates the status of the error that occurred most recently That is if the same error occurred several times before the receive data was read this flag would hold only the status of the error that occurred last The ASISn register is cleared to 00H by a read operation When a reception error occurs the reception buffer register RXBn should be read and the error flag should be cleared after the ASISn register is read This register is read only in 8 bit or 1 bit units n 0 1 Caution When the Power bit or RXE bit of the ASIMn register is set to 0 or when the ASISO register is read the PE FE and OVE bits of the ASISn register are cleared 0 Figure 13 3 Asynchronous Serial Interface Status Registers ASISO ASIS1 7 6 5 4 3 2 1 0 Address ie This is a sta
536. s is calculated according to the following formula effective address PP BASE address offset Preliminary User s Manual U15839EE1VOUMOO 497 Chapter 14 FCAN Interface Function 6 CAN 1 to 4 interrupt enable registers C1IE to CAIE The CxIE registers enable the transmit receive and error interrupts of the corresponding CAN module x x 1 to 4 for the derivatives uPD703129 A 0703129 1 x 1 to 2 for the derivative uPD703128 A These registers can be read in 8 bit and 16 bit units It can be written in 16 bit units only For set ting and clearing certain bits a special set clear method applies refer to chapter 14 3 1 Bit set clear function on page 452 Figure 14 38 CAN 1 4 Interrupt Enable Registers to C4IE 1 3 Address Initia Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Of set Note value CIIE 0 0 0 0 0 0 0 0 0 INTSE INT4E INT3E INT2E INTI E INTO 1058H 0000H C2IE 0 0 0 0 0 0 0 0 0 INTSE INT4E INT3E INT2E INTI E INTO 1098 0000H C3IE 10D8H 0000H C4IE 1118H 0000H Write 1058H ST ST_ IST ST_ IST ST ST CL_ CL_ CL_ CL_ CL_ OL CL_ CHE 0 p inTelE wNTSE INTAE INTSIE INT2E INTHE INTO INT6JE INTSIE INTAIE INTE INT2E INTHE into 1098 ST ST_ IST ST_ ST_ ST_ ST_ CL CL_ CL CL CL_ CL_ 0 E
537. s of the external ROM and instruction processing starts Flash memory programming mode If this mode is specified it becomes possible to modify erase program the contents of external flash memories which are connected to the V850E CA2 Jupiter device via its external memory inter face The V850E CA2 Jupiter device provides a built in Boot Loader offering the possibility to download programming algorithms and the new ROM code itself To be able to use this feature there s no need to have already a dedicated boot software being programmed in the external flash memory It is possible to program external flash memory devices even in the case that the flash memory is completely erased Support of Virgin programming The complete Boot Loader functionality is provided from the V850E CA2 Jupiter device itself This Boot Loader is enabled when the so called Flash Programming Mode is enabled by a dedicated configuration of the V850E CA2 Jupi ter devices MODEO to MODE2 pins As an programming interface the UARTO or the CSIO serial interface can be selected The selec tion of the interface intended to be used can be done by applying a fixed voltage level UARTO or a dedicated amount of pulses CSIO to the V850E CA2 Jupiter device s MODE 1 pin For further information please refer to the document Preliminary Application Note EASE AN 4050 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 3 2 Operation mode specification
538. s offset Preliminary User s Manual U15839EE1VOUMOO 455 Chapter 14 FCAN Interface Function Figure 14 9 Main Clock Select Register CGSC 2 2 Specifies the prescaler for the memory access clock ref to Fig 9 10 Prescaler Memory Clock m 1 fem 1 m 1 fem 1 MCP3 to 2 MCPO fmem 16 Figure 14 10 Configuration of FCAN System Main Clock MCS MCPO to MCP3 Clock for Controller Prescaler Selector Figure 14 11 Configuration of FCAN Global Time System Clock 8 bit counter 8 bit compare fars 456 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 3 CAN global status register CGST The CGST register indicates and controls the operation modes of the FCAN system This register can be read in 1 bit 8 bit and 16 bit units It can be written in 16 bit units only For setting and clearing certain bits a special set clear method applies Refer to chapter 14 3 1 Bit set clear function on page 452 Figure 14 12 CAN Global Status Register CGST 1 3 Address Initial Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OffsetNote value esr TS T TETTE peal TD 00004 Write 14 13 12 11 15 10 9 8 7 6 5 4 2 1 0 ST ST ST_ ST CL CL CL CL CL EFSD TSM
539. s read the pin levels at that time are read Writing to the P3 register writes the values to that register This does not affect the input pins In Output Mode When the P3 register is read the values of P3 are read Writing to the P3 register writes the values to that register and those values are immediately output Besides functioning as a port in control mode it also can operate as the real time pulse unit RPU input output and external interrupt request input Notes 1 lf using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 The reset value of register P3 is 00H Due to the input mode of the port after reset the read input value is determined by the port pins 1 Operation in control mode Alternate Pin Name Remarks Block Type TIGOO INTPOO TOGO01 TIGO 1 TOGO2 TIG02 Real time pulse unit RPU input or external TOGO03 TIGO3 interrupt request input TOGO04 TIG04 TIGOS INTPO5 562 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 2 Setting in input output mode and control mode Port 3 is set in input output mode using the port 3 mode register PM3 In control mode it is set using the port mode control register a Port 3 mode register PM3 This register can be read or writte
540. s register 30 M STAT30 Undefined xxxxn3D6H CAN status set cancel register 30 SC STATS30 0000H xxxxn3EOH CAN message event pointer 310 M_EVT310 Undefined xxxxn3E1H CAN message event pointer 311 M_EVT311 Undefined Xxxxn3E2H CAN message event pointer 312 M_EVT312 Undefined Xxxxn3E3H CAN message event pointer 313 M_EVT313 Undefined xxxxn3E4H CAN message data length register 31 M DLC31 Undefined xxxxn3E5H CAN message control register 31 M CTRL31 Undefined xxxxn3E6H CAN message time stamp register 31 M TIMES1 Undefined xxxxn3E8H CAN message data register 310 Preliminary User s Manual U15839EE1VOUMOO M DATA310 Undefined 99 Address xxxxn3E9H Chapter 3 CPU Function Table 3 7 List of programmable peripheral I O registers 16 18 Function Register Name CAN message data register 311 M DATA311 Bit Units for Manipulation 1 bit 8 bit 16 bit Initial Value Undefined XxxxnSEAH CAN message data register 312 M_DATA312 Undefined xxxxn3EBH CAN message data register 313 M DATA313 Undefined xxxxn3ECH CAN message data register 314 M DATA314 Undefined xxxxn3EDH CAN message data register 315 M DATA315 Undefined xxxxn3EEH CAN message data register 316 M DATA316 Undefined xxxxn3EFH CAN message data register 3
541. s signal indicates that the transmit data buffer register SOTBn SOTBLn has been written Preliminary User s Manual U15839EE1VOUMOO 421 Chapter 13 Serial Interface Function 13 3 5 Output pins 1 SCKOn When the CSIOn operation is disabled CSIE bit of CSIMn register 0 the SCKOn pin output status is as follows n 0 to 2 CKSO SCKOn Pin Output Don t care Don t care Don t care Fixed to high level 1 1 1 Other than above Fixed to high level Fixed to low level Remarks 1 n 0to2 2 When any of bits CKP and CKS2 to CKSO of the CSICn register is overwritten the SCKOn pin output changes 2 SOON pin When the CS10n operation is disabled CSIE bit of CSIMn register 0 the SOOn pin output status is as follows n 0 to 2 SOOn Pin Output Don t care Don t care Don t care Don t care Fixed at low level 0 Don t care Don tcare Dont SO latch value low level SOTB7 value SOTBO value SOTB15 value SOTBO value SOTBF7 value SOTBFO value SOTBF15 value SOTBFO value Remarks 1 When any of bits TRMD CCL DIR AUTO and CSICn of the CSIMn register or DAP bit of the CSICn register is overwritten the SOOn pin output changes SOTBm Bit m of SOTBn register m 0 7 15 SOTBFm Bit m of SOTBFn register m 0 7 15 n 0to2 422 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 3 6 Dedicated
542. s the T1W state T2RI state State in which the bus is ready for DMA transfer to on chip peripheral I O or internal RAM state which the bus mastership is acquired for DMA transfer to on chip peripheral I O or internal RAM After entering the last T2RI state the bus invariably enters the T1W state T1W state The bus enters the T1W state at the beginning of a write operation in the two cycle transfer mode Address driving starts After entering the T1W state the bus invariably enters the T2W state T1WI state This is a state in which the DMAC is awaiting an acknowledge signal for an external memory write request After the last T1WI state the DMAC always transitions to the T2W state T2W state The T2W state corresponds to the last state of a write operation in the two cycle transfer mode or to a wait state In the last T2W state the write strobe signal is made inactive T1FH state This is the basic state of a flybyN t transfer and is the execution cycle of that transfer After the T1FH state the DMAC transitions to the T2FH state Preliminary User s Manual U15839EE1VOUMOO Chapter 7 DMA Functions DMA Controller 11 T1FHI state This is the last state of a flyby transfer and the DMAC is awaiting the end of the transfer After the T1FHI start the bus is released and the DMAC transitions to the TE state 12 T2FH state This is the state in which the DMAC judges whether or not to continue flybyNote transfers
543. s the digital input values of the A D input channels ANIO to ANI7 P70 to P77 This register can be read in 1 bit and 8 bit units Figure 15 8 Port Function Register 7 PORT7 7 6 5 4 3 2 1 0 Address Initial value Port7 P77 P76 P75 P74 P73 P72 P71 P70 FFFFFA40CH undef H ANI7 ANI6 ANI5 ANI4 ANIS3 ANI2 ANI1 ANIO P77 to P70 The bits P77 to P70 holds the digital input values of the A D input channels ANI7 to ANIO Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark 01 11 534 Preliminary User s Manual U15839EE1VOUMOO Chapter 15 A D Converter 15 3 2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins ANIO to ANI11 and the A D conversion result stored in the A D conversion result registers ADCR is shown by the following expression AV x 1024 ADCR INT 0 5 x 64 AVREF or the following expression ADCR 64 0 5 x AVrer _ ADCRI64 0 5 x AVREF lt 1024 3 1024 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVpp AVpp pin voltage and A D converter power supply ADCRL A D conversion result register ADCRL value Figure 15 9 Relation between Analog Input Voltage and A D Conversion Result on page 536 shows the relation between the analog input voltage and the A D convers
544. s the priority by message buffer numbers 0 Transmission priority is given by message identifier 1 Transmission priority is given by the number of the message buffer Remark Normally the message identifier defines the transmission priority If the PBB flag is set the location of a message defines the priority the lower the message buffer number the higher the transmission priority Indicates a CAN bus error 0 No CAN bus error occurred since the bit was cleared last 1 At least one CAN bus error occurred since the flag has been cleared last Remark For single shot mode SSHT bit 1 this flag indicates a loss of the arbitra tion Indicates valid protocol activity 0 No valid message was detected by the CAN protocol layer 1 At least one valid message was received on the CAN bus since the flag has been cleared last Indicates the wake up condition from CAN sleep mode 0 No wake up or sleep mode has been terminated by CPU normal operation 1 CAN sleep mode has been terminated by detection of CAN bus activity Indicates an overrun error 0 No overrun normal operation 1 An overrun occurred during access to the CAN memory Remark The OVR flag is set if the CAN message handler is not able to scan all the message areas defined for the CAN module due to timing problems The error interrupt CxINT6 is generated at the same time Possible cause for an overrun situation The CAN memory access clock fgg selection i
545. s too slow for the selected CAN baud rate 494 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 35 CAN 1 to 4 Definition Registers C1DEF to CADEF 4 4 Write Sets clears the DGM bit ST DGM CL Status of DGM bit 0 1 DGM bit is cleared 0 1 0 DGM bit is set 1 Others No change in DGM bit value Sets clears the MOM bit Status of MOM bit MOM bit is cleared 0 MOM bit is set 1 No change in MOM bit value Status of SSHT bit ST_SSHT SSHT bit is cleared 0 CL_SSHT SSHT bit is set 1 No change in SSHT bit value Status of PPB bit PPB bit is cleared 0 PPB bit is set 1 Others No change in PPB bit value Clears the BERR bit CL BERR 0 change of BERR bit 1 BERR bit is cleared 0 Clears the VALID bit CL VALID 0 No change of VALID bit 1 VALID bit is cleared 0 Clears the WAKE bit CL WAKE 0 No change of WAKE bit 1 WAKE bit is cleared 0 Clears the OVR bit CL OVR 0 No change of OVR bit 1 OVR bit is cleared 0 Preliminary User s Manual U15839EE1VOUMOO 495 Chapter 14 FCAN Interface Function 4 CAN 1 to 4 information registers CTLAST to CALAST The CxLAST registers return the number of the last received message and last CAN protocol error of the corresponding CAN module x x 1 to 4 for the derivatives 703129 and uPD7031
546. se so that the input level does not change during operation RESET Reset Input RESET input is asynchronous input When a signal having a certain low level width is input in asynchronous with the operation clock a system reset that takes precedence over all operations occurs Besides a normal initialize or start this signal is also used to release a standby mode HALT IDLE Watch Sub Watch software STOP RESOUT Reset Output RESOUT output is a 3 3 V reset output signal It is the internal system reset output RESOUT is active low in case of an external reset by RESET input pin or internal reset by watch dog timer If the RESOUT output pin is connected to a RESET IN of an external flash memory it can be used to terminate an embedded erase programming operation at the occurrence of a valid RESET signal NMI NON Maskable Interrupt Request input This is the non maskable interrupt request input pin X1 X2 Crystal These pins connect a resonator for system main clock generation XT1 XT2 Crystal These pins connect a resonator for the sub clock generation CVpp Power supply for clock generator This is the positive power supply pin for the clock generator CVss Ground for clock generator This is the ground pin for the clock generator Vppso to Vpps2 Power supply These are the positive 5 V power supply pins Preliminary User s Manual U15839EE1VOUMOO 49 Chapter 2 Pin Functions 23 Vssso to Vsss
547. sers Manual U15839EE1VOUMOO 9 9 5 Register lt 268 9 5 1 Power Save Control Register 5 268 9 5 2 Power Save Mode Register 5 270 Chapter 10 Times RR REG nee bea 271 TOT Timer C louer eae sacs lene es cera A 271 10 1 1 Features 271 10 1 2 Function overview Timer 272 10 1 3 Basicconfiguration eee 274 10 1 4 5 278 10 1 5 Operation cerca s geb ra Rein 283 10 1 6 Sub Oscillator Calibration 293 10 1 7 Precautions 295 10 2 Timer Diui ace Relates RA 296 10 2 1 Features Timer D eee 296 10 2 2 Function overview Timer 296 10 2 3 Basic configuration eerie tisui spaa ep R R rn 297 10 2 4 5 301 10 2 5 Operation seres prece sek be Meet Dd leq SEO
548. shared with the ADC input channels ANIO to ANI7 Port 7 holds the digital input values of the A D input channels ANIO to ANI7 P70 to P77 Port mode and port mode con trol are not available for port 7 This register can be read in 1 bit or 8 bit units Figure 16 25 Port Function Register 7 P7 Address Initial value 7 6 5 4 3 2 1 0 77 76 75 P74 P73 P72 71 P70 d ANI7 6 5 ANI2 ANH undef H P77 to P70 MTS P77 to P70 holds the digital input values of the A D input channels ANI7 to Note Reading the digital value of the analog input channel ANIx is disabled during A D conversion operation Remark xz0to7 572 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 8 Port 7 8 Port 7 8 is a 16 bit input port which is shared with the ADC input channels ANIO to ANI11 Port 7 8 holds the digital input values of the A D input channels ANIO to ANI11 P70 to P77 P80 to P83 Port mode and port mode control are not available for port 7 8 This register can only be read in 16 bit units Figure 16 26 Port Function Register 7 8 P7 P8 14 11 Initial P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 ANH 1 ANITO ANI9 ANI8 ANI7 ANIG ANI5 ANI4 ANI3 ANI2 ANI1 ANIQ Address value P7 P8 FFFFF40CH undef 11108 P83 to P80 ns BT P83 to P80 holds the digital input values of th
549. should be written after referencing the ASIFn register to confirm the transmission status and whether or not data can be written to the TXBn register n 0 1 Caution Transmit data should be written when the TXBF bit is 0 The transmission unit should be initialized when the TXSF bit is 0 If these actions are performed at other times the transmit data cannot be guaranteed Table 13 2 Transmission Status and Whether or Not Writing Is Enabled Whether or not Write Transmission Status Operation to TXBn is Enabled Initial status or transmission completed Writing is enabled Transmission in progress no data is in TXBn register Writing is enabled Awaiting transmission data is in TXBn register Writing is not enabled Transmission in progress data is in TXBn register Writing is not enabled Preliminary User s Manual U15839EE1VOUMOO 377 Chapter 13 Serial Interface Function a Starting procedure Figure 13 9 shows the procedure to start continuous transmission Figure 13 9 Continuous Transmission Starting Procedure nm MR TXD5n output Data 2 0 Parity INTST5n output TXB5n register Data 2 A Data 3 Transmission shift register D Data 2 S Data 3 ASIF5n register SEE TXBF TXSF bits lt 1 gt 2 3 4 b 60 7 85 9 ASIFn Register Transmission Starting Procedure Inter
550. signal of the receive message 1 CGTSC counter is captured into the corresponding M TIMEm register when the valid receive message is copied into the message buffer Remark For details refer to chapter 14 2 5 Time stamp on page 441 Selects the CAN stop mode 0 CAN module is not stop mode 1 CAN module stop mode selected Remarks 1 The CAN stop mode can be entered only if the CAN module is already in sleep mode SLEEP 1 In CAN stop mode the CAN module is disabled protocol layer activities stopped and set in suspend mode and wake up of the CAN module is only possible by CPU CPU clears STOP bit Selects the CAN sleep mode 0 Normal operation mode 1 CAN module sleep mode selected Remarks 1 Entering the CAN sleep mode from normal operating mode is just pos sible when the CAN bus is idle In CAN sleep mode the CAN module does not process any transmit request submitted by the CPU In case there is activity on the CAN bus and in parallel the SLEEP bit is set 1 the CAN module remains in normal operating mode and the SLEEP bit is cleared 0 automatically The CAN sleep mode is released and normal operating mode is entered under the following conditions a CPU clears the SLEEP bit i e internal wake up by CPU b first dominant bit on the idle CAN bus i e external wake up by CAN bus activity After releasing the CAN sleep mode the WAKE bit of the CxDEF regis ter is set 1 and an error interr
551. smission interrupt request When the transmission shift register becomes empty a transmission completion interrupt request INTSTn is generated The timing for generating the INTSTn interrupt differs according to the specification of the number of stop bits The INTSTn interrupt is generated at the same time that the last stop bit is output If the data to be transmitted next has not been written to the TXBn register the transmit operation is suspended Caution Normally when the transmission shift register becomes empty a transmission 376 completion interrupt INTSTn is generated However no transmission completion interrupt INTSTn is generated if the transmission shift register becomes empty due to the input of a RESET Figure 13 8 Asynchronous Serial Interface Transmission Completion Interrupt Timing a Stop bit length 1 TXDn output Start DOD INTSTn output b Stop bit length 2 TXDn output Start DOD INTSTn output Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 3 Continuous transmission operation UART5n can write the next transmit data to the TXBn register at the time that the transmission shift register starts the shift operation This enables an efficient transmission rate to be realized by continuously transmitting data even during the INTSTn interrupt service after the transmission of one data frame When continuous transmission is performed data
552. sssseeeenenenenen nennen 29 WORT 54 CPU Register Sel nd ease eee norat ee Io dede he tie 56 Program Counter PG 4 ied ee td Ears ree Fe ti 57 Interrupt Source Register ECR ssssssssssssssseseee ener 59 Program Status Word 5 2 2 60 GPU Address Space p eae Ue e 65 Image on Address Space sssssssssssssssseseeee eene nennen nennen intrent 66 Wrap around of Program Space 67 Wrap around of Data 67 Memory Map UPD703128 A essere nennen 68 Memory Map uPD703129 A UPD703129 1 69 Internal RAM Area of uPD703129 ssssessssseesseen eene nnne 73 Internal RAM Area of 0 703128 73 Internal Peripheral nnne nnns nennen 74 Example Application of wrap around 703129 75 Programmable Peripheral I O Register Outline esses 83 Peripheral Area Selection Control Register BPC 84 Command Register PRCMD Format sse en
553. ster CGST 1 3 457 CAN Global Interrupt Enable Register CGIE 1 2 460 CAN Timer Event Enable Register CGTEN sss 462 CAN Global Time System Counter and event 462 CAN Global Time System Counter CGTSO sse 463 CAN Message Search Start Register CGMSS 464 CAN Message Search Result Register CGMSR 465 CAN Test Bus Register ssssssssssesssesenennnene enne nennen 466 Internal CAN Test Bus Structure 466 CAN Interrupt Pending Registers CCINTPL CCINTPH _ 467 CAN Global Interrupt Pending Register CGINTP 1 2 468 CAN 1 to 4 Interrupt Pending Registers C1INTP to C4INTP 1 2 470 Message Identifier Registers LOO to L31 and HOO to H31 M IDLOO to M IDL31 M IDHOO to M IDH31 sese 472 Message Configuration Registers 00 to 31 M CONFOO to M CONF31 1 2 473 Message Status Registers 00 to 31 M STATOO to M STATS31 475 Message Set Clear Status Registers 00 to 31 SC STATOO to SC STAT31 477 Message Data Registers m0 to m7 M DATAmO0 to M DATAm7 m 00 to 31
554. t Either design the circuit that will not malfunction even if a glitch is generated or make sure that the ENTO bit and the ALV bit do not change at the same time 3 TOCO output remains unchanged by external interrupt signals INTCCCOO INTCCCO1 When using the signal set the capture compare register to the compare register CMS1 CMSO bits of TMCCO1 register 1 Remark A reset takes precedence for the flip flop of the output Figure 10 6 Timer C control Register 1 1 2 Initial 7 6 5 4 3 2 1 0 Address value Bit Position Bit name Function Setting of the timer operation after overflow 7 OST 0 After overflow the count operation is continued free running mode 1 After overflow the count operation is stopped overflow stop mode The count is restarted by writing 1 to the CE bit Enables disables output of external pulse output TOCO 0 Disable external pulse output Output of inactive level of ALV bit to TOCO pin is fixed TOCO pin level remains unchanged even if match signal from correspond ing compare register is generated 6 ETO 1 Enable external pulse output Compare register match causes TOCO output to change However in capture mode TOCO output does not change An ALV bit inactive level is output from the time when timer output is enabled until a match signal is generated Caution lf either CCCOO0 or CCC01 is specified as a capture register the ENTO bit must
555. t 4 mode register 4 b Control mode P40 to P45 can be set to port or control mode in 1 bit units using PMC4 c TOG11 to TOG14 Timer output Output These pins output a timer G 1 pulse signal d TIG10 to TIG15 Timer input Input These pins are the timer G 1 external capture trigger input pins e INPT10 INTP15 Interrupt request from peripherals Input These are external interrupt request input pins Preliminary User s Manual U15839EE1VOUMOO 43 5 Chapter 2 Pin Functions P50 to P56 Port 5 Input output Port 5 is a 7 bit input output port in which input or output can be set in 1 bit units Besides functioning as an input output port in control mode P50 to P56 operate as the real time pulse unit RPU input output as the serial interface FCAN4NOTE ang as external interrupt request input An operation mode of port or control mode can be selected for each bit and specified by the port 5 mode control register PMC5 a Port mode P50 to P56 can be set to input or output in 1 bit units using the port 5 mode register PM5 b Control mode P50 to P56 can be set to port or control mode in 1 bit units using PMC5 c TOO Timer output Output This pin output a timer C pulse signal d TIO TI1 Timer input Input These pins are the timer C external capture trigger input pins e 4 Transmit data for controller area network Output This pin outputs FCAN serial transmit
556. t b Interrupt request b and c are acknowledged first according to their priorities Because the priorities of b and c are YA the same b is acknowledged first ird priority Processing of interrupt request c according to the default rarity a gt b gt c NMI request fk Processing of interrupt request a Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts When returning from multiple interrupt servicing restore the values of EIPC and EIPSW after executing the DI instruction Remark lt a gt to c in the figure are the temporary names of interrupt requests shown for the sake of explanation Preliminary User s Manual U15839EE1VOUMOO 215 Chapter 8 Processing Function 8 3 4 Interrupt control register xxIC An interrupt control register is assigned to each interrupt request maskable interrupt and sets the con trol conditions for each maskable interrupt request This register can be read written in 8 bit or 1 bit units Figure 8 10 Interrupt Control Register xxIC 7 6 5 4 3 2 1 0 Address Initial value to FFFF18EH This is an interrupt request flag 0 Interrupt request not issued 1 Interrupt request issued The flag xxIFn is reset automatically by the hardware if an interrupt request is acknowl edged This is an interrupt mask flag 0 Enables interrupt processing 1 Disables interrupt processing pending
557. t died e tcs d alates 50 MOSD uf UE M bL Em dI tase n UEM URL A EC 50 608 Preliminary User s Manual U15839EE1VOUMOO Appendix B Index Tm 107 WALT win e 137 Malt TUriCtlOli Deus tnt teer D Pasa RUN SUERTE ENT BUR ETE Te UR d oes 109 WalliStates C 107 WATCH mode Bae ae Ds ire E 253 259 261 2e ee eum exi Red sie Vig ue wende ue RENE ee 349 Operation ee eee a tee DNO Rs ROUTE yet ig hath DOR ERES esata Era vk n E 352 Watch Timer Glock celu LESER Eee eA ee ee RUP I e RE HERE ee ER E mud 352 Watch timer clock frequency 355 Watch timer mode control 5 350 watchdog cre eee etse teen de e OE RR DIAC BU EINE RUE E RR EE 587 Watchdog timer clock selection register 359 Watchdog timer command register 361 Watchdog timer command status register 361 Watchdog Timer Control Register 359 Watchdog timer mode 360 eno PT 361 duel ease
558. t of maskable interrupts in service program Service program of maskable interrupt or exception EIPC saved to memory or register EIPSW saved to memory or register El instruction interrupt acknowledgment enabled Maskable interrupt acknowledgment Dl instruction interrupt acknowledgment disabled Saved value restored to EIPSW Saved value restored to EIPC RETI instruction 234 Preliminary User s Manual U15839EE1VOUMOO Chapter8 Interrupt Exception Processing Function 2 Generation of exception in service program Service program of maskable interrupt or exception EIPC saved to memory or register EIPSW saved to memory or register TRAP instruction Exception such as TRAP instruction acknowledged Saved value restored to EIPSW Saved value restored to EIPC RETI instruction The priority order for multiple interrupt processing control has 8 levels from 0 to 7 for each maska ble interrupt request 0 is the highest priority but it can be set as desired via software Setting of the priority order level is done using the PPRnO to PPRne bits of the interrupt control request reg ister PICn which is provided for each maskable interrupt request After system reset an interrupt request is masked by the PMKn bit and the priority order is set to level 7 by the PPRnO to PPRn2 bits The priority order of maskable interrupts is as follows High Level 0 gt Level 1 gt Level 2 gt Level 3 gt Lev
559. t of the PSW is 1 2 Transfers control to the address of the restored PC and PSW Figure 8 22 illustrates the processing of the RETI instruction Figure 8 22 RETI Instruction Processing RETI instruction PC EIPC PC FEPC PSW EIPSW PSW FEPSW Original processing restored Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction dur ing the software exception processing in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary to set PSW EP back to 1 using the LDSR instruction immediately before the RETI instruction Remark The solid lines show the CPU processing flow 228 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function 8 5 3 Exception status flag EP The EP flag is bit 6 of PSW and is a status flag used to indicate that exception processing is in progress It is set when an exception occurs Figure 8 23 Exception Status Flag EP Initial value rw J0 000000 0000000000000 o 0NE sTCO s z oo 31 876543210 Shows that exception processing is in progress EP 0 Exception processing not in progress 1 Exception processing in progress Preliminary User s Manual U15839EE1VOUMOO 229 Chapter8 Processing Function 8 6 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction ta
560. t of the TOGnm pins This bit can be rewritten during timer operation The CLRGx bit x 0 1 is a flag If this bit is read a 0 is read at all times This bit clears the corresponding counter TMGnO or TMGn1 When GCCnm register m 1 to 4 are used in capture operation If two or more overflows of TMGn0 or TMGn1 occur between captures a software based measure needs to be taken to count overflow interrupts INTTMGnO or INTTMGn1 If only one overflow is necessary the CCFGy bits y 0 to 5 can be used for overflow detection Only the overflow of the TMGnO or TMGn1counter clears the CCFGy bit TMGSTn register The software based clearing via CLRGO or CLRG1 bit TMGMLn register doesn t affect these bits The CCFGy bit is set if a TMGn0 TMGn1 overflow occurs This flag is only updated if the corresponding GCCny register was read so first read the GCCny register and then read this flag if necessary Preliminary User s Manual U15839EE1VOUMOO 347 4 348 Chapter 10 Timer Timing The delay of each timer output TOGnm m 1 to 4 varies according to the setting of the count clock with the CSEx2 to CSEx0 bits x 0 1 In capture operation to 4 periods of the count clock signal are required from the TlGny pin y 0 to 5 until a capture interrupt is output when x 0 1 is set earlier or simultaneously with POWER bit than the Timer Gn needs 7 peripheral clocks periods fpc to start coun
561. t only if the processing involves operations within the CPU processing without any VSB and NPB accesses Run the code to perform the above operations from the memory areas shown below 1 2 3 Uncacheable area su duit Cacheable area If bit 4 FILLO of the ICC register is set using an uncacheable area autofill cannot be performed invalid operation EE C etc Either a cacheable area or an uncacheable area Preliminary Users Manual U15839EE1VOUMOO 165 Chapter 6 Instruction Cache 6 5 Instruction Cache Initialisation The instruction cache settings must be performed using the following procedure with the initial settings of the user program immediately following a system reset 1 Wait until the contents of the ICC register becomes OOOOH TAG initialization is completed 2 Clear all bits of the ICI register using the following instruction sth rO Oxfffff072 r0 3 Setthe ICC and ICD registers 4 the instruction cache settings of the cache configuration register BHC Caution Be sure to make the BHC register settings running the code from an uncacheable area an instruction is not correctly fetched if settings are made using a cacheable area 166 Preliminary User s Manual U15839EE1VOUMOO Chapter6 Instruction Cache 6 6 Operating Precautions 1 2 Operation on Reset At the time of a reset tags are automatically cleared invalidated which puts the next data replacement in a sta
562. t output Serial interface input output Port 3 6 bit input output Real time pulse unit input output external interrupt input PWM output Port 4 6 bit input output Real time pulse unit input output external interrupt input PWM output Port 5 7 bit input output Serial interface input output external interrupt input Port 6 8 bit input output Serial interface input output external interrupt input Port 7 8 bit input A D converter analog input Port 8 4 bit input A D converter analog input Port 9 8 bit input output Port AH 8 bit input output External address bus Port CS 3 bit input output External bus interface control signal output Port CT 3 bit input output External bus interface control signal output LW Port CM 1 bit input output Wait insertion signal input WAIT Preliminary User s Manual U15839EE1VOUMOO 31 MEMO 32 Preliminary User s Manual U15839EE1VOUMOO Chapter 2 Pin Functions 2 1 List of Pin Functions The names and functions of this product s pins are listed below These pins can be divided into port pins and non port pins according to their functions 1 Port pins P10 P11 P12 P13 P14 P15 P16 P17 Table 2 1 Port Pins 1 3 Function Alternate FCRXD1 FCTXD1 FCRXD2 Port 1 FCTXD2 8 bit input output port FCRXD3Nete FCTXD3Note RXD1 TXD1
563. t output port mode 1 CSO Chip select output 578 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 12 Port CT Port CT is a 3 bit input output port in which input or output can be specified in 1 bit units After reset port pin PCT4 operates as a read strobe signal output RD The port pins PCTO and PCT1 operate as port input after reset Each port bit can be independently configured to port input port output or periph eral functionNete 1 This register can be read in 1 bit and 8 bit units Figure 16 35 Port CT PCT Address At Reset 7 6 5 4 3 2 1 0 PCTn n 4 1 0 Input output port Remark n Input Mode When the PCT register is read the pin levels at that time are read Writing to the PCT register writes the values to that register This does not affect the input pins In Output Mode When the PCT register is read the values of PCT are read Writing to the PCT register writes the values to that register and those values are immediately output Besides functioning as a port in control mode PCTO and PCT1 can operate as the write strobe signal outputs when memory is accessed externally PCT4 can also operate as the read strobe signal input Notes 1 lf using peripheral functions the direction setting for the respective port bit is not forced automatically Port bit direction has to be programmed according to the peripheral function requirement by setting the port mode register 2 Th
564. t port mode 1 TOO output mode Specifies operation mode of P55 pin 0 Input output port mode 1 TH input mode or external interrupt request INTP21 input mode Specifies operation mode of P54 pin 0 Input output port mode 1 TIO input mode or external interrupt request INTP20 input mode Specifies operation mode of P53 pin 0 Input output port mode 1 External interrupt request INTP5 input mode Specifies operation mode of P52 pin 0 Input output port mode 1 External interrupt request INTP4 input mode Specifies operation mode of P51 pin 0 Input output port mode 1 CTXD4N te output mode Specifies operation mode of P50 pin 0 Input output port mode 1 CRXD4Note input mode Note CAN module 4 is available in the derivatives PD703129 A and PD703129 A1 only 568 Preliminary User s Manual U15839EE1VOUMOO Chapter 16 Port Functions 16 3 6 Port 6 Port 6 is an 8 bit input output port in which input or output can be specified in 1 bit units Each port bit can be independently configured to port input port output or peripheral functionNete 1 This register can be read or written in 1 bit and 8 bit units Figure 16 22 Port 6 P6 Address At Reset 7 6 5 4 3 2 1 0 P6n n 7 to 0 Input output port Remark In Input Mode When the P6 register is read the pin levels at that time are read Writing to the P6 register writes the values to that register This does not affect the input pins
565. ta is transferred to the slave register In a compare operation the slave register s value is compared with the count value of the TMDn register When a read operation to a CMDn register is performed data in the master side is read out CMDn can be read written in 16 bit units Figure 10 20 Timer Dn Compare Register CMDn n 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address al value Cautions 1 A write operation to the a CMDn register requires fpc 2 clocks until the value that was set in the CMDn register is transferred to internal units When writing continuously to the CMDn register be sure to reserve a time interval of at least fpcik 2 clocks 2 The CMDn register can be overwritten only once in a single TMDn register cycle from 0000H until an INTTMDn interrupt is generated due to a match of the TMDn register and CMDn register If this cannot be secured by the application make sure that the CMDn register is not overwritten during timer operation 3 Note that an INTTMDn interrupt will be generated after an overflow if a value less than the counter value is written in the CMDn register during TMDn register operation Figure 10 21 Timing of Timer Dn Operation on page 300 Preliminary User s Manual U15839EE1VOUMOO 299 Chapter 10 Timer Figure 10 21 Timing of Timer Dn Operation a When TMDn CMDn TMDn CE _ T _ INTTMDn b When TMDn gt CMDn TMDn INTTMDn
566. tart trigger of DMA channel 0 through interrupt requests from on chip peripheral I O The interrupt requests set with these registers serve as DMA transfer start factors This register can be read written in 8 bit 1 bit units Figure 7 10 DMA Trigger Factor Registers 0 DTFRO 7 6 5 4 3 2 1 0 Address Initial value Bit Position Bit Name Function DRQNete DOFLNete IFC3 to Sets the interrupt source that serves as the DMA start factor IFCO Interrupt Source Peripheral Source INTIN1 CSIO INTIN2 csi CSI2 INTIN4 UARTO Reception INTIN6 UART1 Reception INTIN8 ADC INTIN9 TMGO 1 INTIN10 TMG1 1 Note DRQ and DOFL are set by hardware and reset by software Setting these bits by software is not possible A 0 must be written to the respective bit location to reset DRQ or DOFL Cautions 1 Be sure to stop DMA operation before making changes to DTFRO register set tings 2 Aninterrupt request input in a standby mode IDLE or software STOP mode can not be used as a DMA transfer start factor Preliminary User s Manual U15839EE1VOUMOO 179 Chapter 7 DMA Functions DMA Controller 7 2 9 DMA trigger factor register 1 DTFR1 This 8 bit registers is used to control the DMA transfer start trigger of DMA channel 1 through interrupt requests from on chip peripheral I O The interrupt requests set with these registers serve as DMA transfer start factors This regist
567. tched value is held in the capture register until the next time the capture operation is performed When the CAE bit of Timer C control register 0 is 0 OOOOH is read If the CCCOO or CCCO1 register is specified as capture register an interrupt is generated INTCCCOO or INTCCCO 1 by detecting the valid edge of signals Caution If the capture operation and the TMCO register count prohibit setting CE bit of TMCCOO register 0 timings conflict the captured data becomes undefined and no INTCCCOO interrupt is generated n O 1 b Setting CCCOn registers to compare registers CMS1 and CMSO of TMCCO1 1 When these registers are set to compare registers the TMCO and register values are compared for each timer count clock and an interrupt is generated by a match If the CCLR bit of Timer C control register 1 TMCCO1 is set 1 the TMCO value is cleared 0 at the same time as a match with the CCCOO register it is not cleared 0 by a match with the CCCO1 register A compare register is equipped with a set reset output function The corresponding timer output TOCO is set or reset synchronized with the generation of a match signal The interrupt selection source differs according to the function of the selected register Cautions 1 The minimum value for CCCO to achieve a symmetrical output wave with the Compare Clear Enable function CLR bit 1 is 0003H 2 To write to capture compare registers 0 and 1 C
568. te In INIT state the transmission and reception error counters are cleared and any error status is reset Indicates the transmit pin status 0 CAN transmit pin is disabled tri state 1 CAN transmit pin is enabled Specifies the dominant level of the CAN receive input pin 0 Low level at the receive input is interpreted as a dominant bit 0 1 High level at the receive input is interpreted as a dominant bit 0 Remark From software point of view a dominant bit is always a 0 value Specifies the dominant level of the CAN transmit output pin 0 A dominant bit 0 results in a low level output 1 A dominant bit 0 results in a high level output Remark From software point of view a dominant bit is always a 0 value 488 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 34 1 to 4 Control Registers C1CTRL to CACTRL 3 5 Read 2 2 Bit Position Bit Name Function Specifies the CAN message buffer overwrite mode 0 A new CAN message overwrites a message buffer with DN flag set 1 1 A new CAN message is discarded if it would be stored in a message buffer with DN bit set 1 Remark The OVM bit determines how to handle a receive message in case this message would overwrite the corresponding receive message buffer Specifies the time stamp mode for reception 0 CGTSC counter is captured into the corresponding M TIMEm register at SOF
569. te of being performed from way 0 Therefore if there is an access to the instruction cache within a period of as many clock cycles as the number of lines after a reset the CPU stops until the tags are cleared become valid Setting registers Be sure to set the registers shown below running the code from an uncacheable area However set bit 4 of the instruction cache control register ICC using a cacheable area Chip area select control registers CSCO CSC1 Peripheral I O area select control register BPC e Bus size configuration register BSC Endian configuration register BEC e Cache configuration register BHC e Instruction cache control register ICCNete Instruction cache data configuration register ICD Note Excluding bit 4 3 4 Initial program settings Always execute the following instruction before setting the cache configuration register BHC with the initial settings of the user program immediately following system reset st h rO OxfffffO72 r0 Following execution of this instruction the cache is enabled by setting cache enable bit 1 as the instruction cache setting with the BHC register n 7 to 0 Setting BHC register In the case of CSn areas for which an instruction to set the BHC register exists in the same CSn area cache enable disable settings for the instruction cache using this instruction cannot be per formed n 7 to 0 Instruction cache enabl
570. ten in 8 bit units Figure 14 29 Message Data Length Code Registers 00 to 31 M to M DLC31 Address is 7 6 5 4 3 2 1 OttsetNote 1 Initial value M DLOm pics DLC2 plci DLCO 804H undef m x 20H Bit Position Bit Name Function Specifies the data length code of the transmit receive message Data Length Code DLC No data bytes 0 1 data byte 2 data bytes DLC3 to 3 data bytes DLCO 4 data bytes 5 data bytes 6 data bytes 7 data bytes 8 data bytes Others than above Setting not recommendedete 3 Notes 1 The register address is calculated according to the following formula effective address PP BASE address offset 2 RFU Reserved for future use Ensure to set these bits to 0 when writing to the M DLCm register 3 If a DLC is specified to a value greater 8 for a transmit message 8 byte transfer is per formed regardless of the DLC value Remark 00 to 31 Cautions 1 If a remote frame is received on a transmit buffer the DLC value leaves unchanged 2 If a remote frame is received on a receive buffer the DLC value is updated by the DLC value of the remote frame 480 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 7 Message control registers 00 to 31 M CTRLO to M CTRL31 The M CTRLm registers control the behaviour on reception or transmission of the corresponding message buffer m m 00 to 31 These registers
571. tenNete 1 in 16 bit units only Figure 14 16 Global Time System Counter CGTSC Address Initial OffsetNote2 value 1018H 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Notes 1 When writing is performed to CGTSC register the counter is cleared to O 2 The register address is calculated according to the following formula effective address PP BASE address offset Remark The CGTSC register can be read at any time Preliminary User s Manual U15839EE1VOUMOO 463 Chapter 14 FCAN Interface Function 7 CAN message search start register CGMSS The CGMSS register controls the start of a message search It can be used for a fast message retrieval within the message buffers matching a search criteria e g messages with DN flag set This register is write only and must be written in 16 bit units Figure 14 17 CAN Message Search Start Register CGMSS Address Initial OffsetNote value cous DE CON uuu ws Search criteria for message identifier type IDE 0 Do not check status of the message identifier type 1 Message identifier type must be standard identifier IDE 0 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 Search criteria for event processing request flag ERQ of the M STATm registers 0 Do not check status of the ERQ flag 1 ERQ flag must be set Search criteria for transmit request flag TRQ and message ready flag RDY of the M STATm registers 0 Do n
572. ter 21 M CONF21 Undefined xxxxn2B5H CAN message status register 21 M STAT 1 Undefined xxxxn2B6H CAN status set cancel register 21 SC_STAT21 0000H xxxxn2COH CAN message event pointer 220 M EVT220 Undefined xxxxn2C1H CAN message event pointer 221 M EVT221 Undefined xxxxn2C2H CAN message event pointer 222 M EVT222 Undefined xxxxn2C3H CAN message event pointer 223 M EVT223 Undefined xxxxn2CA4H CAN message data length register 22 M DLC22 Undefined Xxxxn2C5H CAN message control register 22 M_CTRL22 Undefined xxxxn2C6H CAN message time stamp register 22 M TIME22 Undefined Xxxxn2C8H CAN message data register 220 M_DATA220 Undefined xxxxn2C9H CAN message data register 221 M DATA221 Undefined Xxxxn2CAH CAN message data register 222 M_DATA222 Undefined xxxxn2CBH CAN message data register 223 M DATA223 Undefined xxxxn2C CH CAN message data register 224 M DATA224 Undefined xxxxn2CDH CAN message data register 225 M DATA225 Undefined xxxxn2CEH CAN message data register 226 M DATA226 Undefined xxxxn2CFH CAN message data register 227 M DATA227 Undefined xxxxn2DOH CAN message ID register L22 M IDL22 Undefined xxxxn2D2H CAN message ID register H22 M IDH22 Undefined xxxxn2D4H
573. ternal timer counter is cleared by writing to the PRSMn register Therefore do not write to the PRSCMn register during transmission 2 Set the PRSCMn register prior to setting the CE bit of the PRSMn register to 1 If the contents of the PRSCMn register are overwritten when the value of the CE bit is 1 the cycle of the baud rate signal is not guaranteed d Baud rate signal cycle The baud rate signal cycle is calculated as follows When setting value of PRSCMn register is 00H Cycle of signal selected with bits BGCS1 BGCSO of PRSMn register 256 x 2 In cases other than above Cycle of signal selected with bits BGCS1 BGCS2 of PRSMn register setting value of PRSCMn register x 2 Preliminary User s Manual U15839EE1VOUMOO 425 Chapter 13 Serial Interface Function e Baud rate setting example Table 13 6 Baud Rate Generator Setting Data lt 1 gt When 16 MHz PRSCM Register Value Clock Hz 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 OF Ol Ol o OJ O O O Ek lt 2 gt When fpc 20 MHz BGCS1 BGCSO PRSCM Register Value Clock Hz 0 2 2500000 5 1000000 500000 250000 100000 Caution Setthe transfer clock so that it does not fall below the minimum value of 200 ns of the SCKOn cycle tcysk prescribed in the electrical specifications
574. ters Low SIOLO to SIOL2 407 Timing Chart in single Transfer Mode 1 2 409 Timing Chart According to Clock Phase Selection 1 2 411 Preliminary User s Manual U15839EE1VOUMOO Figure 13 36 Figure 13 37 Figure 13 38 Figure 13 39 Figure 13 40 Figure 13 41 Figure 13 42 Figure 13 43 Figure 13 44 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 14 10 Figure 14 11 Figure 14 12 Figure 14 13 Figure 14 14 Figure 14 15 Figure 14 16 Figure 14 17 Figure 14 18 Figure 14 19 Figure 14 20 Figure 14 21 Figure 14 22 Figure 14 23 Figure 14 24 Figure 14 25 Figure 14 26 Figure 14 27 Figure 14 28 Figure 14 29 Figure 14 30 Figure 14 31 Figure 14 32 Figure 14 33 Figure 14 34 Figure 14 35 Figure 14 36 Figure 14 37 Figure 14 38 Figure 14 39 Figure 14 40 Figure 14 41 Figure 14 42 Figure 14 43 Figure 14 44 Figure 14 45 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 413 Repeat Transfer Receive Only Timing 415 Repeat Transfer Transmission Reception Timing 417 Timing Chart of Next Transfer Reservation Period 1 2 418 Transfer Request Clear
575. ters are used to set the transfer counts for DMA channels n They store the remaining transfer counts during DMA transfer Since these registers are configured as 2 stage FIFO buffer registers a new DMA transfer count for DMA transfer can be specified during DMA transfer refer to 7 3 Next Address Setting Function During DMA transfer these registers are decremented by 1 for each transfer that is performed DMA transfer is terminated when an underflow occurs from 0 to FFFFH On terminal count these registers are rewritten with the value that was set immediately before These registers can be read written in 16 bit units Figure 7 5 DMA Transfer Count Registers 0 to 3 DBCO to DBC3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DBCO FFFFFOCOH undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DBC1 FFFFFOC2H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value DBC2 FFFFFOC4H undef 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O Address Initial value Bit Position Bit Name Function Sets the transfer count It stores the remaining transfer count during DMA transfer DBCn States Transfer count 1 or remaining transfer count Transfer count 2 or remaining transfer count Transfer count 65 536 21 or remaining transfer count Cautions 1 In case of a line transfer and the setting of the DBCn register is 0003H four trans fers one line transfer is appl
576. the message data byte 7 Note The register address is calculated according to the following formula effective address PP BASE address offset Remark m Cautions 1 00 to 31 When transmitting data only the number of bytes defined by the data length code DLC in the M DLCm register are transmitted on the CAN bus The transmission always starts with M If the ATS flag of the corresponding CxCTRL register is set 1 and the data length code DLC in the M DLCm register is greater or equal 2 the last two bytes which are normally taken from the data part of the message buffer are ignored and instead of these bytes a time stamp value is sent x 1 to 2 for the derivative HPD703128 A x 1 to 4 for the derivatives PD703129 A and PD703129 A1 refer to chapter 14 2 5 Time stamp on page 441 When a new message is received all data bytes are updated even if the data length code DLC in the M DLCm register is less than 8 The values of the data bytes that have not been received may be change undefined Preliminary User s Manual U15839EE1VOUMOO 479 Chapter 14 FCAN Interface Function 6 Message data length code registers 00 to 31 M DLCO to M DLC31 The M_DLCm registers specify the data length code DLC of the corresponding message m m 00 to 31 The DLC determines how many data bytes have to be transmitted or received respectively for the corresponding data frame These registers can be read writ
577. the operation status of each pin during Reset period Table 17 1 Operation Status of each pin during Reset period Pin Function RESET TIGO5 to TIGOO TIG15 to TIG10 TICO1 to TICOO INTPOS5 INTPOO INTP15 INTP10 INTP21 INTP20 INTP5 to INTPO NMI TOG04 to TOG01 TOG14 to TOG11 TOCO 5002 5001 5000 5102 5101 5100 SCK02 SCK01 SCK00 RXD51 RXD50 TXD51 TXD50 FCRXD3 to FCRXpoNete FCTXD3 to FCTXpoNete ANH 1 to ANIO P1 P2 P3 P4 P5 P6 P9 PAH 7 0 PCS 4 3 0 PCT 1 0 PCT 4 PCM 0 Remarks 1 N A This configuration is not available 2 Input data is not sampled Note FCTXD4 to FCTXD3 FCRXD4 to FCRXD3 only for uPD703129 584 Preliminary User s Manual U15839EE1VOUMOO Chapter 17 RESET 17 4 Reset by RESET Pin If a low level signal is input to the RESET pin a system reset is performed and the hardware is initial ized When the RESET pin level changes from low to high the Reset State is released and the program execution is started All register will be initialized The RESET pin incorporates a noise eliminator which uses analogue delay to prevent malfunction due to noise 1 Reset signal acknowledgment Figure 17 1 Reset signal acknowledgment RESET 4 Analog 1 Analog Analog delay delay i delay Elimination as noise Internal system Note reset signal MEA Reset acknowledgment Reset rele
578. the pro gram branches to the reset entry address in the external memory to start instruction execution Address output is not masked in the ROMLESS Mode 1 Address is always output This is the ordinary operation of external memory interface Data and instructions in the internal boot ROM cannot be accessed or fetched FLASH Programming Mode 0 In FLASH Programming Mode 0 external flash memory programming is enabled by starting from the internal boot ROM of Jupiter This boot ROM contains bootstrap code to download FLASH pro gramming routines into iRAM and execute these routines Address masking on the external mem ory interface is active Note The lower 1MB memory area is occupied by the boot ROM in FLASH Programming Mode 0 4 Please refer to Chapter 3 5 Memory Map on page 68 for a memory map FLASH Programming Mode 1 In FLASH Programming Mode 1 external flash memory programming is enabled by starting from the internal boot ROM of Jupiter This boot ROM contains bootstrap code to download FLASH pro gramming routines into iRAM and execute these routines Address on the external memory inter face is not masked Note The lower 1MB memory area is occupied by the boot ROM in FLASH Programming Mode 1 64 Please refer to Chapter 3 5 Memory Map on page 68 for a memory map Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function 3 4 Address Space 3 4 4 CPU address space The CPU of the V850E CA2 is of 32 bit
579. the test procedures required by ISO 16845 The CAN macro successfully passed all test patterns Beyond these test patterns other tests like robustness tests and processor interface tests as recommended by C amp S FH Wolfenbuettel have successfully been issued Preliminary User s Manual U15839EE1VOUMOO 25 Chapter 1 Introduction 1 3 Application Fields The V850E CA2 Jupiter is ideally suited for automotive applications like dashboard or gateway appli cations It is also an excellent choice for other applications where a combination of sophisticated periph eral functions and CAN network support is required 1 4 Ordering Information Part number Packade Internal ROM Internal RAM Full CAN RAM 9 bytes bytes bytes Channels 1K 32 message buffers PD703128 A 144 pin QFP fine pitch 20 20 mm Rom less 2 FCAN Channels 1K 32 message buffers PD703129 A 144 pin QFP fine pitch 20 20 mm Rom less 4 FCAN Channels i 1K 32 message buffers uPD703129 A1 144 pin QFP fine pitch 20 20 mm Rom less 4 FCAN Channels 26 Preliminary User s Manual U15839EE1VOUMOO Chapter 1 Introduction 1 5 Pin Configuration Top View 144 pin QFP fine pitch 20 x 20 mm uPD703128 A uPD703129 A uPD703129 A1 Figure 1 1 V850E CA2 Jupiter Pin Configuration o e lt a a 25 a E E E ES 2 af 2 26 Sere St or or wsozooroos
580. this CAN module might be overwritten by new messages although the DN flag is already set Checking the MOVR bit additionally indicates whether the message buffer has been overwritten Reserved bit value of CAN bus bit rO for receive message buffer Reserved bit value of CAN bus bit r1 for receive message buffer Specifies remote or data frame type of the message buffer 0 Message received or to be sent is a data frame 1 Message received or to be sent is a remote frame Remark When the RTR bit is set 1 for a transmit message a remote frame is transmitted for the given identifier instead of a data frame The RTR bit can be read for a receive message to determine whether a data frame or a remote frame was received Remarks 1 00 to 31 2 1 to 4 for the derivatives uPD703129 A and uPD703129 A1 3 1 to 2 for the derivative uPD703128 A 482 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function 8 Message time stamp registers 00 to 31 M to M_TIME31 The M TIMEm registers store the captured time stamp value on reception of the corresponding message m m 00 to 31 These registers can be read written in 16 bit units Figure 14 31 Message Time Stamp Registers 00 to 31 M TIMEO0 to M Address Initial OffsetNote value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 cc m x 20H 7915 to 16 bit time stamp value captured on message receptio
581. this time interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m 7 Processing of m Processing of o m Processing of P ccs rocessing of q ride xs Interrupt Interrupt Processing of r level 3 request p eyed level 2 level 1 Interrupt request r level 0 If levels 3 to 0 are acknowledged Processing of s Pending interrupt requests t and u are acknowledged after processing of s interrupt Because the priorities of t and u are the same u is request t acknowledged first because it has the higher Interrupt request s level 2 Note 1 default priority regardless of the order in which the level 1 dar Missa interrupt requests have been generated evel 2 Processing of u Notes 1 Lower default priority 2 Higher default priority Processing of t Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts When returning from multiple interrupt servicing restore the values of EIPC and EIPSW after executing the DI instruction 214 Preliminary User s Manual U15839EE1VOUMOO Chapter 8 Interrupt Exception Processing Function Figure 8 9 Example of Processing Interrupt Requests Simultaneously Generated EI Interrupt request a level 2 Interrupt request b level 1 Interrupt request c level 1 Processing of interrupt reques
582. time Interval time gt lt Remarks 1 p Setting value of CCCOO register 0000H to FFFFH 2 t Count clock cycle 3 Interval time p 1 xt 290 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 5 PWM output Timer C has one timer output pin TOCO An external pulse output TOCO can be generated when a match of the two compare registers CCC00 and CCCO01 and the TMCO register is detected If a match is detected when the TMCO count value and the CCCOO0 value are compared the output level of the TOCO pin is set Also if a match is detected when the TMCO count value and the CCC01 value are compared the output level of the TOCO pin is reset The output level set reset depends on the settings of the ALV and ENTO bits of the TMCCO1 register Table 10 2 TOCO Output Control Output External Pulse Output Output Level Disable High level Disable Low level When the CCCOO0 register is matched Low level When the 1 register is matched High level When the CCCOO register is matched High level When the CCC01 register is matched Low level Enable Enable Figure 10 15 Timing of PWM output operation overview FFFFH FFFFH TMCO count value 0 Count start lt 1 OVF lt 1 Interrupt request INTCCCOO 1 1 Interrupt request INTCCCO1 20 i dL 5S db oiu 1 i 1 ENT1 lt 1 up ALV lt
583. timer is started when the WTMO bit and the WTM bit of the watch timer mode control register WTM are set to 1 Both prescalers are stopped and cleared if the WTMO bit is set to 0 For independent start or stop of watch timer function operation This functionality is only available when the 11 bit Prescaler is running too The count operation of the watch timer is started when the WTM1 bit and the WTMO bit of the watch timer mode control register WTM are set to 1 The WTMO bit has to be set to 1 either it was 1 before In that case the frequency of the running 11 bit prescaler is not influenced The 5 bit watch timer function prescaler is stopped and cleared if the WTM bit is set to 0 Caution If the 5 bit watch timer function prescaler is clocked by fw 2 WTM3 0 This prescaler is started with the next edge of the fw 2 clock Therefore if the 11 bit prescaler was running before the 5 bit prescaler watch timer is started the INTWT interrupt is generated up to one fw 29 period later then the time that the WTM1 bit was set to 1 For example if fw fyx7 32 i e fxxr 32000 Hz this be up to 1 ms This happens only at the first starting edge of the fw 2 clock Table 11 3 Example for Interval Time of Watch Timer fw fcksgLo fw fcksEL1 Interval Time fx 4096 fxr 32 KHz WTSEL1 0 WTSEL1 1 Remarks 1 fy 4 MHz WTSELO bit 1 CKC regist
584. ting when TMGxE x 0 1 is set later than POWER bit than the Timer Gn needs 4 peripheral clocks periods fpc to start counting When a capture register GCCny is read the capturing is disable during read operation This is intended to prevent undefined data during reading So if a contention occurs between an external trigger signal and the read operation capture operation may be cancelled and old data may be read GCOnm register m 1 to 4 in Compare mode After setting the POWER bit you have to wait for 10 peripheral clocks periods to perform write access to the GCCnm register m 1 to 4 To perform successive write access during operation for rewriting the GCCnm register n 1 to 4 you have to wait for minimum 7f peripheral clocks periods Preliminary User s Manual U15839EE1VOUMOO Chapter 11 Watch Timer 11 1 Function The watch timer has the following functions Watch timer e Interval timer The watch timer and interval timer functions can be used at the same time Figure 11 1 shows the block diagram of the watch timer Figure 11 1 Block Diagram of Watch Timer 8 5 5 bit counter 2 INTWT fckseLi 5 o 2 Clear fCKSEL2 4 gt INTWTI Selector Watch timer mode control register WTM g Internal bus 1 Watch timer The watch timer generates an interrupt request INTWT at time intervals of
585. ting Data can be written to it only in a sequence of specific instructions so that its contents are not eas ily rewritten in case of program hang up See also WCMD register Once the watchdog timer is started RUN 1 after reset this register cannot be changed WDTM is set by an 8 1 bit memory manipulation instruction Cautions 1 The WDTM4 bit has to set to 1 at the initialisation of the WDT 2 WDTM register setting by DMA transfer is prohibited This registers should be written with STORE instruction execution by CPU only Figure 12 3 Watchdog Timer Mode Register WDTM 6 5 4 3 2 1 0 Address R W After reset 7 WDTM RUN 0 WDTMAWDTM3 FFFF F572H R W 00H Note 1 Operating Mode Selection for the Watchdog Timer After Reset disable count writing during counting clear old count After Reset start counting writing during counting clear old count WDTM4 Nis WDTMS Watchdog Timer Operation Mode Selection Watchdog timer mode 1 Non maskable interrupt occurs upon generation of an overflow Watchdog timer mode 2 RESET operation is activated upon generation of an overflow Notes 1 If RUN is set to 1 once the register cannot be cleared to 0 by software Therefore when the count starts the count cannot be stopped except by RESET input 2 The WDTM4 bit has to set to 1 at the initialisation of the WDT Cautions 1 Data is set to the CKC register by the following seque
586. tion 1 bit 8 bit 16 bit Initial Value Undefined xxxxn365H CAN message control register 27 M CTRL27 Undefined xxxxn366H CAN message time stamp register 27 M TIME27 Undefined Xxxxn368H CAN message data register 270 M_DATA270 Undefined Xxxxn369H CAN message data register 271 M_DATA271 Undefined Xxxxn36AH CAN message data register 272 M_DATA272 Undefined Xxxxn36BH CAN message data register 273 M_DATA273 Undefined xxxxn36CH CAN message data register 274 M DATA274 Undefined xxxxn36DH CAN message data register 275 M DATA275 Undefined xxxxn36EH CAN message data register 276 M DATA276 Undefined xxxxn36FH CAN message data register 277 M DATA277 Undefined xxxxn370H CAN message ID register L27 M IDL27 Undefined xxxxn372H CAN message ID register H27 M IDH27 Undefined xxxxn374H CAN message configuration register 27 M CONF27 Undefined xxxxn375H CAN message status register 27 M STAT27 Undefined xxxxn376H CAN status set cancel register 27 SC STAT27 0000H Xxxxn380H CAN message event pointer 280 M_EVT280 Undefined Xxxxn381H CAN message event pointer 281 M EVT281 Undefined xxxxn382H CAN message event pointer 282 M EVT282 Undefined xxxxn383H CAN message event pointer 283 M
587. tion Set List ssssssssssssseeeeeeennne eene 589 Preliminary Users Manual U15839EE1VOUMOO 19 20 Preliminary User s Manual U15839EE1VOUMOO Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 4 1 Table 4 2 Table 7 1 Table 8 1 Table 8 2 Table 8 3 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 9 8 Table 9 9 Table 9 10 Table 9 11 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 12 1 Table 13 1 Table 13 2 Table 13 3 Table 13 4 Table 13 5 Table 13 6 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 14 5 Table 14 6 Table 14 7 List of Tables onde 33 NonsPort PIhs 2o tede eere al pee exte eere eee e E dea ue cede de eve pede ad 36 Pin Status in Reset and Standby 39 Types of Pin I O Circuit and Connection of Unused 51 Program Registers cie ree ud NER KIAIA RAEAN AARRE ues sire VES RAE 57 System Register nnns innen 58 Saturation Processed Operation Result 61 Operation MOodesS tae aA rn ei Mou EU adn ee ets 63 Interrupt Exception Table
588. tion register PRC This register specifies whether page ROM on page access is enabled or disabled If on page access is enabled the masking address no comparison is made out of the addresses A3 to A6 corresponding to the configuration of the page ROM being connected to and the number of bits that can be read con tinuously as well as the number of waits corresponding to the internal system clock are set This register can be read written in 16 bit units Figure 5 5 Page ROM Configuration Register PRC 15 14 13 42 41 10 9 8 7 8 5 4 8 2 dress 1 value wc s epe wr T9 T9 T3 Le T9 T5 T5 Ton e ues Jenn Page ROM On page Wait Control Sets the number of waits corresponding to the internal system clock The number of waits set by this bit are inserted only when on page When off page the waits set by registers DWCO and DWC1 are inserted Number of Inserted Wait Cycles PRW2 to PRWO 14to 12 Mask Address Each respective address A6 to A3 corresponding to MA6 to MA3 is masked masked by 1 The masked address is not subject to comparison during on off page judgment It is set S to the number of readable bits 4 words x 16 bits 8 words x 8 bits 8 words x 16 bits 16 words x 8 bits 16 words x 16 bits 32 words x 8 bits 32 words x 16 bits 64 words x 8 bits 64 words x 16 bits 128 words x 8 bits Caution Write to the PRC register after reset and then
589. tions e Saturated operation instructions e One clock 32 bit shift instruction barrel shifter Long short instruction format Four types of bit manipulation instructions Set Clear Not Test Preliminary Users Manual U15839EE1VOUMOO 55 Chapter 3 CPU Function 3 2 CPU Register Set The registers of the V850E CA2 Jupiter can be classified into two categories a general program regis ter set and a dedicated system register set All the registers are 32 bit width For details refer to V850E User s Manual Architecture Figure 3 1 CPU Register Set 1 Program register set 2 System register set 31 0 Zero Register EIPC Status Saving Register during interrupt Reserved for Assembler EIPSW Status Saving Register during interrupt Interrupt Stack Pointer Stack Pointer SP FEPC Status Saving Register during NMI Global Pointer GP FEPSW Status Saving Register during NMI Text Pointer TP ECR Interrrupt Source Register PSW Program Status Word CTPC Status Saving Register during CALLT execution CTPSW Status Saving Register during CALLT execution DBPC Status Saving Register during exception debug trap DBPSW Status Saving Register during exception debug trap CTBP Base Pointer Element Pointer EP Link Pointer LP 31 0 PC Program Counter 56 Preliminary User
590. to SIRB2 Lis aede ee fan asad Da enu eR fara TE s a gla RUEDA 398 SIBBEO to SIRBE2 eue rendere iste niu eA a wy oe SSE 400 SIRBELO to SIRBELZ ici Senate ata c Lctinsst eheu rdg eu E exeun 401 SIRBEO to SIBBE2E sett osa mesa e buque 399 Software exception qu nd des waked solos scade S dnbio ia ER egens 227 Software STOP MOJE uei hes pbi eae atas pa Vac ter miei eae VOR De RICE acs 253 265 SOTBO to SOTB2 TI AME xdg et ale leu iei ote ae 402 SOTBFO to SOIBE2 edd EMO X IER PET ELLE EXE Ghee PE DES 404 Preliminary User s Manual U15839EE1VOUMOO 607 Appendix Index SOTBELO 1t0 SOTBEL2 eut siters dues Ee ads de eee 405 SOTBEO to SOTBEO2 i et EE aem aee dor b tp tan e Cie o eee e st 403 SpecifiC InStructiOlis EM 360 Specific Registers 2er uU heels ae elle es 103 Spread Spectrum PLL 0 00 ehh 239 eene hah tells tae E eod dar eet dp eek ae EUR E a AE ex Tu E es 137 Stack eet ote det p are bap ela E Me EE RES 57 Standby f nction uu e pei edere CERRO Cd eser e el gerit ege ede EE ete e et qid 523 Standby MOE e cr sepe cene ere Uude Lebe by Sean ERU Ee Ms iced aper a TR ER RE ed 541 Sub Oscillator Calibration Function eh 293 sub oscillator calibration function
591. to capture mode 4 On the next watch timer wake up interrupt the captured value of CCC01 gives the modulo counter for main oscillator clocks per watch timer interrupt To achieve a higher accuracy measurement capture value of the n th watch timer interrupt should be taken as the result 294 Preliminary User s Manual U15839EE1VOUMOO Chapter 10 Timer 10 1 7 Precautions Timer C Various precautions concerning Timer C are shown below 1 The following bits and registers must not be rewritten during operation TMCCOO register CE 1 e CS2 to CSO bits of TMCCOO register e TMCC01 register e SESCO register The CAE bit of the TMCCOO register is a TMCO counter reset signal To use TMCO first set the CAE bit to 1 The analog noise elimination time two cycles of the input clock are required to detect a valid edge of the external input TICOO or TICO1 Therefore edge detection will not be performed normally for changes that are less than the analog noise elimination time two cycles of the input clock The operation of an interrupt output INTCCCOO or INTCCCO 1 is automatically determined according to the operating state of the capture compare registers CCC00 CCCO01 When the capture compare registers are used for a capture mode the external trigger TICO0 TICO1 is used for valid edge detection When the capture compare registers are used for a compare mode the external interrupt output is used for a match interrupt indicati
592. to reset input this register can also be initialized by clearing 0 the CSIE bit of the CSIMn register The SIRBEn register is the same as the SIRBn register It is used to read the contents of the SIRBn register Figure 13 26 Clocked Serial Interface Read Only Reception Buffer Registers SIRBEO to SIRBE2 Initial value SIRBEO SIRBE S5 SIRBE 4 SIRBET3 SIRBET SIRBEt SIRBET0 SIRBES SIRBES8 SIRBE SIRBES SIRBES SIRBEA SIRBE3 SIRBE2 SIRBE1 SIRBEO FFFF FDO6H 0000H RES ESE SEE prp SE SESE EERE tr v eo mn RE ESE ES praep erae aerae eer 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Biss Ene SIRBE15 to 15to0 SIRBEO Store receive data Cautions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit of CSIMn register 1 400 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 6 Clocked serial interface read only reception buffer registers Low SIRBELO to SIRBEL2 The SIRBELn register is an 8 bit buffer register that stores receive data n 0 to 2 These registers are read only in 8 bit units In addition to reset input this register can also be initialized by clearing 0 the CSIE bit of the CSIMn register The SIRBELn register is the same as the lower byte of the SIRBn register It is used to read the contents of the SIRBLn register Figu
593. to the registers by the following sequence Write the set data to the command register PHCMD see Chapter 3 6 2 Peripheral Command Register PHCMD on page 105 Write the set data to the destination register WCC Remarks 1 If it is required to switch to another WDT clock source it is recommended to monitor the status of the concerned clock source to be selected before Switching to an unstable clock source is not protected by hardware 2 The WCC register should be programmed immediately after occurrence of a system Reset even in the case that the default settings are intended to be used 3 It is possible to change the contents of the WCC register only for one time after the occurrence of a Reset 244 Preliminary User s Manual U15839EE1VOUMOO Chapter 9 Clock Generator 9 3 4 Processor Clock Control Register PCC This is an 8 bit register that controls the CPU clock Data can be written to it only in a sequence of spe cific instructions so that its contents are not easily rewritten in case of program hang up See also PHCMD register The setup of this register can be changed only one time After a power save mode has been released the CPU clock is supplied by the main oscillator and again a new clock source can be selected This register can be read or written in 8 bit units Figure 9 5 Processor Clock Control Register PCC 1 2 7 6 5 4 3 2 1 0 Address jas value Bit name Function Sub system clock oscillatio
594. transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects internal RAM or peripheral I O during DMA transfer Transfer of misaligned data DMA transfer of 16 bit 32 bit bus width misaligned data is not supported Times related to DMA transfer The overhead before and after DMA transfer and the minimum execution clock for DMA transfer are shown below Internal RAM access 2 clocks Bus arbitration for CPU The CPU can access on chip peripheral I O and internal RAM not undergoing DMA transfer While data transfer is being executed between internal RAMs the CPU can access external mem ory and peripheral I O Interrupt factors DMA transfer is interrupted if a bus hold is issued If the factor bus hold interrupting DMA transfer disappears DMA transfer promptly restarts Preliminary User s Manual U15839EE1VOUMOO Chapter8 Interrupt Exception Processing Function The V850E CA2 is provided with a dedicated interrupt controller INTC for interrupt servicing and can process a total of 64 maskable and three non maskable interrupt requests An interrupt is an event that occurs independently of program execution and an exception is an event whose occurrence is dependent on program execution Generally an exception takes precedence over an interrupt The V850E CA2 can process interrupt requests from the on chip peripheral hardware and external sources Moreover exception processing c
595. tten in 8 bit or 1 bit units Figure 16 12 Port 2 Mode Control Register PMC2 3 2 1 0 Address At Reset 7 6 5 4 PMC2 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 FFFFF442H 00H Specifies operation mode of P27 pin 0 Input output port mode 1 TXDO output mode Specifies operation mode of P26 pin 0 Input output port mode 1 RXDO input mode Specifies operation mode of P25 pin 0 Input output port mode 1 SCK1 input output mode Specifies operation mode of P24 pin 0 Input output port mode 1 SO1 output mode Specifies operation mode of P23 pin 0 Input output port mode 1 511 input mode Specifies operation mode of P22 pin 0 Input output port mode 1 SCKO input output mode Specifies operation mode of P21 pin 0 Input output port mode 1 SOO output mode Specifies operation mode of P20 pin 0 Input output port mode 1 SIO input mode Preliminary User s Manual U15839EE1VOUMOO 561 Chapter 16 Port Functions 16 3 3 Port 3 Port 3 is a 6 bit input output port in which input or output can be specified in 1 bit units Each port bit can be independently configured to port input port output or peripheral functionNete 1 This register can be read or written in 1 bit and 8 bit units Figure 16 13 Port 3 P3 Address At Reset 7 6 5 4 3 2 1 0 c ux 71 0 Input output port Remark In Input Mode When the P3 register i
596. ture compare register Programmable pulse generator function Interval timer function PWM output External signal cycle measurement Sub oscillator calibration function Remark In this Timer C chapter following indexes were consequently used e nz0 1 for each of the 2 Timer C Capture Compare Channels Preliminary User s Manual U15839EE1VOUMOO 271 Chapter 10 Timer 10 1 2 Function overview Timer C 16 bit timer counter TMCO 1 channel Capture compare registers 2 Count clock division selectable by prescaler maximum frequency of count clock 8 MHz Prescaler divide ratio from fpc 2 to fpc 256 Interrupt request sources Capture compare match interrupt requests 2 sources In case of capture register INTCCCOO generated by TICOO INTCCCO 1 generated by TICO1 input In case of compare register INTCCCOO generated by CCCO00 match signal INTCCCO1 generated by CCCO01 match signal Overflow interrupt request 1 source INTTMCO generated upon overflow of TMCO register Timer counter count clock sources 1 type internal peripheral clock cycle One of two operation modes when the timer counter overflows can be selected free running mode or overflow stop mode The timer counter can be cleared by match of timer counter and compare register External pulse output TOCO 1 With the sub oscillator calibration function the actual sub clock frequency can be measured taking the main oscillator frequency as ref
597. tus flag that indicates a parity error 0 When the ASIMn registers Power and RXE bits are both set to 0 or when the ASISn register has been read 2 PE 1 When reception was completed the transmit data parity did not match the parity bit Caution The operation of the PE bit differs according to the settings of the PS1 and PSO bits of the ASIMn register This is a status flag that indicates a framing error 0 When the ASIMn register s Power and RXE bits are both set to O or when the ASISn register has been read 1 FE 1 When reception was completed no stop bit was detected Caution For receive data stop bits only the first bit is checked regardless of the number of stop bits This is a status flag that indicates an overrun error 0 When the ASIMn register s Power and RXE bits are both 0 or when the ASISn register has been read 1 UART5n completed the next receive operation before reading the 0 OVE RXBn receive data Caution When an overrun error occurs the next receive data value is not written to the RXBn register and the data is discarded 370 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 3 Asynchronous serial interface transmission status registers ASIFO ASIF1 The ASIFn register which consists of 2 bit status flags indicates the status during transmission By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmission shift register transmit
598. ty level cannot be nested However if multiple interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose register before executing the El instruc tion 2 Execute the DI instruction before executing the RETI instruction then reset EIPC and EIPSW with the values saved in 1 8 3 1 Operation If a maskable interrupt occurs by INT input the CPU performs the following processing and transfers control to a handler routine 1 Saves the restored PC to EIPC 1 2 Saves the current PSW to EIPSW 3 Writes an exception code to the lower halfword of ECR EICC 4 Sets the ID bit of the PSW and clears the EP bit 5 Sets the handler address corresponding to each interrupt to the PC and transfers control The processing configuration of a maskable interrupt is shown in Figure 8 6 Maskable Interrupt Processing on page 210 Preliminary User s Manual U15839EE1VOUMOO 209 Chapter8 Interrupt Exception Processing Function Figure 8 6 Maskable Interrupt Processing INT input Y INTC accepted Is the interrupt mask released Priority higher than that of interrupt currently processed No Priority higher than that of other interrupt request ighest default priority of interrupt requests with the same priority Yes Maskable interrupt request Interrupt request pending Cue m 1 0 0 restored
599. uction Cache Control Register ICC 158 Instruction Cache Data Configuration Register ICD 159 Instruction Cache Hit 160 Instruction Cache Initial Register ICI 159 Instruction Cache Miss 161 INSTUCTION CY ClO oem EIC MES NUR RAPIT eme ding 55 Internal peripheral I O area 74 604 Preliminary User s Manual U15839EE1VOUMOO Appendix B Index Intermal RAM area unes Lae RE RIDERE RR UE Pun awe CER ee M EUR ieee eee 73 Internal ROM area eek ied e ed Ro e e ea dd Pe dune 70 Interrupt control register Ihn 216 Interrupt mask registers 1 0 3 219 Interm ptimod6 eb Re pata eon eo LER MERE DEF Rib E RENTUR 357 Interrupt mode register O 223 Interrupt mode register 1 arie o ea e gt n 224 Interrupt mode register 2 225 Interrupt mode register RART e e nh 226 Interrupt response time 236 Interrupt Source Register l liiisiseleelseeees hn 59 Interrupt source
600. uffer register after serial transfer is completed during a reception enabled state Transmission completion interrupt INTSTn Interrupt is generated when the serial transmission of transmit data 8 or 7 bits from the shift register is completed Character length 7 or 8 bits e Parity functions Odd even 0 or none e Transmission stop bits 1 or 2 bits e On chip dedicated baud rate generator Remark n 0 1 364 Preliminary User s Manual U15839EE1VOUMOO Chapter 13 Serial Interface Function 13 2 2 Configuration UARTS5n is controlled by the asynchronous serial interface mode register ASIMn asynchronous serial interface status register ASISn and asynchronous serial interface transmission status register ASIFn Receive data is maintained in the reception buffer register RXBn and transmit data is written to the transmission buffer register TXBn Figure 13 1 Asynchronous Serial Interfaces Block Diagram on page 366 shows the configuration of the asynchronous serial interface UART5n n 0 1 1 2 3 4 5 6 7 Asynchronous serial interface mode registers ASIMO ASIM1 The ASIMn register is an 8 bit register for specifying the operation of the asynchronous serial interface Asynchronous serial interface status registers ASISO ASIS1 The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs The various reception error flags ar
601. ule 1 CAN module 2 CAN module 3Nete CAN module 4N t which provide each an interface to a Controller Area Network CAN The CAN modules are conform to ISO 11898 former CAN specification version 2 0B active An external bus transceiver has to be used to connect a CAN module to a CAN bus That external bus transceiver converts the transmit data line and receive data line signals to the necessary electrical sig nal characteristic on the CAN bus itself All protocol activities in a CAN module are handled by hardware transfer layer The CAN modules themselves provide no memory for the necessary data buffers rather all CAN mod ules have access to the common CAN memory area via a memory access controller MAC The MAC allows integration of machines other than CAN modules e g CAN bridge The CPU also accesses to the common CAN memory via the MAC The MAC offers data scan capability beside con trolling the arbitration of CAN modules or CPU accesses to the CAN memory By means of that scan capability inner priority inversions at message transmissions are automatically avoided and received messages are sorted into the corresponding receive message buffers according to an inner storage priority rule Figure 14 1 Functional Blocks of the FCAN Interface Internal Peripheral Bus to from CPU Memory Access Controller CAN Memory CAN CAN CAN CAN Module 1 Module 2 Module 3 Note Module 4 Note FCTXD1 FCR
602. unction 2 global interrupt pending register CGINTP The CGINTP register indicates the global interrupt pending signals The interrupt pending flags can be cleared by writing to the register according to the special bit clear method Refer to chap ter 14 3 1 Bit set clear function on page 452 This register can be read in 8 bit and 16 bit units It can be written in 16 bit units only Figure 14 22 CAN Global Interrupt Pending Register CGINTP 1 2 Address Initial Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OffsetNote value cewre o T T T3 T9 T T PL T3 BRENT 00004 14 13 12 11 10 15 9 8 7 6 5 4 3 2 1 0 CL CL TeL TeL GINT7 GINT3 GINT2IGINT1 Read Indicates an interrupt of the CAN bridge ELISA GINT7 bit of CGINTP register 0 No Interrupt pending 1 Interrupt pending Write CGINTP 1020H Indicates a wake up interrupt from CAN sleep mode while clock supply to the FCAN system was stopped ref to CSTOP register 0 No Interrupt pending 1 Interrupt pending Indicates an illegal address access interrupt 0 No Interrupt pending 1 Interrupt pending Remarks 1 Interrupt signals an illegal address access refer to Figure 9 2 2 Interrupt signals a write access to temporary buffer while GOM bit of the CGST register is set 1 Indicates an invalid write access interrupt 0 No Interrupt pending 1 Interrupt pending Remarks 1 Interrupt signals a write access to a CAN
603. upt interrupt INTSERS5n output INTSERS5n output Reception error Reception error 1 interrupt interrupt i INTSERSn does not occur Preliminary User s Manual U15839EE1VOUMOO 381 6 382 Chapter 13 Serial Interface Function Parity types and corresponding operation A parity bit is used to detect a bit error in communication data Normally the same type of parity bit is used at the transmission and reception sides a Even parity During transmission The parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is even The parity bit value is as follows f the number of bits with the value 1 within the transmit data is odd 1 f the number of bits with the value 1 within the transmit data is even 0 During reception The number of bits with the value 1 within the receive data including the parity bit is counted and a parity error is generated if this number is odd b Odd parity During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd The parity bit value is as follows f the number of bits with the value 1 within the transmit data is odd 0 f the number of bits with the value 1 within the t
604. upt control register 22 CCG121C R W x x 47H Preliminary User s Manual U15839EE1VOUMOO 77 Chapter 3 CPU Function Table 3 6 List of Peripheral I O Registers 3 7 Bit Units Address Function Register Name for Manipulation 1 bit 8 bit 16 bit FFFF F13E Interrupt control register 23 CCG13IC FFFF F140 Interrupt control register 24 CCG14IC FFFF F142 Interrupt control register 25 CCG15lC FFFF F144 Interrupt control register 26 TMCOIC FFFF F146 Interrupt control register 27 CCCO IC FFFF F148 Interrupt control register 28 CCC1IC FFFF F14A Interrupt control register 29 ADIC FFFF F14C Interrupt control register 30 MACIC FFFF F14E Interrupt control register 31 FC1RXIC FFFF F150 Interrupt control register 32 FC1TXIC FFFF F152 Interrupt control register 33 FC1ERIC FFFF F154 Interrupt control register 34 FC2RXIC FFFF F156 Interrupt control register 35 FC2TXIC FFFF F158 Interrupt control register 36 FC2ERIC FFFF F15A Interrupt control register 37 FC3RXIC FFFF F15C Interrupt control register 38 FC3TXIC FFFF F15E Interrupt control register 39 FC3ERIC FFFF F160 Interrupt control register 40 FC4RXIC R W x x 47H FFFF F162 Interrupt control register 41 FC4TXIC RW x x 47H FFFF F164 Interrupt control register 42 FC4ERIC RW x x 47H FFFF F166 Interrupt control register 43 CSIOIC R W
605. upt is generated upon external wake up by CAN bus activity Requests entering the initialisation mode 0 Normal operation mode 1 Initialisation mode request Remark The INIT flag is used to set the CAN module in initialisation mode The CAN module acknowledges the transition into initialisation state by setting the ISTAT flag 1 This may take some time especially when the protocol layer is handling a transmission or reception Preliminary User s Manual U15839EE1VOUMOO 489 Chapter 14 FCAN Interface Function Figure 14 34 CAN 1 to 4 Control Registers C1CTRL to C4CTRL 4 5 Write 1 2 Sets clears the TPE bit ST TPE CL TPE Status of TPE bit 0 1 TPE bit is cleared 0 1 0 TPE bit is set 1 Others No change in TPE bit value Sets clears the DLEVR bit ST DLEVR CL DLEVR Status of DLEVR bit ST DLEVR 0 1 DLEVR bit is cleared 0 CL DLEVR 1 0 DLEVR bit is set 1 Others No change in DLEVR bit value Sets clears the DLEVT bit ST DLEVT CL DLEVT Status of DLEVT bit ST DLEVT 1 DLEVT bit is cleared 0 CL DLEVT 0 1 0 DLEVT bit is set 1 Others No change in DLEVT bit value Sets clears the OVM bit ST OVM CL OVM Status of OVM bit 0 1 OVM bit is cleared 0 1 0 OVM bit is set 1 Others No change in OVM bit value Sets clears the TMR bit Status of TMR bit TMR bit is cleared 0 TMR bit is set 1 Others No change
606. upt signals an access to any CAN memory area not explicitly specified 2 Interrupt signals an illegal FCAN system shut down i e GOM bit is going to be cleared while at least one of the CAN modules is not in ini tialisation state or forced shut down is not selected Note Ihe register address is calculated according to the following formula effective address PP BASE address offset 460 Preliminary User s Manual U15839EE1VOUMOO Chapter 14 FCAN Interface Function Figure 14 13 Global Interrupt Enable Register CGIE 2 2 Write Sets clears the G_IE7 bit ST_G_IE7 CL_G_IE7 Status of G_IE7 Bit ST_G_IE7 G_IE7 bit is cleared 0 CL G IE7 G_IE7 bit is set 1 No change in G_IE7 bit value Status of G_IE2 Bit ST G IE2 G_IE2 bit is cleared 0 CL_G_IE2 G_IE2 bit is set 1 No change in G_IE2 bit value Status of G_IE1 Bit ST G IE1 IET IE1 CL G IE1 G_IE1 bit is cleared 0 G_IE1 bit is set 1 Others No change in G_IE1 bit value Preliminary User s Manual U15839EE1VOUMOO 461 Chapter 14 FCAN Interface Function 5 CAN timer event enable register CGTEN The CGTEN register enables disables the 4 timer events This register can read and written in 8 bit and 16 bit units Figure 14 14 CAN Timer Event Enable Register CGTEN Address Initial OffsertNote value coen o T 9 8 9 9 4 3 1016H ooo
607. us Transmission Error Counter Status Transmission error counter below warning level 96 Transmission error counter in warning level range 96 to 127 Reserved not possible Transmission error counter above warning level 2 128 Reception Error Counter Status Reception error counter below warning level 96 Reception error counter in warning level range 96 to 127 Reserved not possible Reception error counter in the error passive range 2 128 Indicates a bus off status of the CAN module 0 CAN module is not in bus off state transmission error counter 256 1 CAN module is in bus off state transmission error counter 256 Indicates the transmission status 0 No transmission activity on the CAN bus 1 Transmission activity on the CAN bus Indicates the reception status 0 No reception activity on the CAN bus 1 Reception activity on the CAN bus Indicates the initialisation mode 0 CAN module is in normal operation mode 1 CAN module is stopped and set into initialisation mode Reset value Remarks 1 The ISTAT bit is set when the setting of the INIT bit is acknowledged by the CAN protocol layer It is cleared automatically when the INIT bit is cleared In initialisation mode the level of the corresponding CAN transmit out put is recessive logical high Data manipulation of the CXSYNC and CxBRP registers is only possi ble during INIT sta
608. use of basic instructions that can each be executed in 1 clock period and an optimized pipeline achieves marked improvements in instruction execution speed In addition in order to make it ideal for use in digital servo control a 32 bit hardware multiplier enables this CPU to support multiply instructions saturated multiply instructions bit operation instructions etc Also through 2 byte basic instructions and instructions compatible with high level languages etc object code efficiency in a C compiler is increased and program size can be made more compact Further since the on chip interrupt controller provides high speed interrupt response including processing this device is suited for high level real time control fields 2 External memory interface function The V850E CA2 contains a non multiplexed external bus interface including an address bus 24 bits and data bus 16 bits SRAM and ROM can be connected as well as page ROM memories The DMA controller allows data transfers between internal RAM and peripheral I O This reduces the CPU load 3 A full range of development environment products A development environment system that includes an optimized C compiler debugger in circuit emula tor simulator system performance analyzer and other elements is also available Preliminary Users Manual U15839EE1VOUMOO 23 Chapter 1 Introduction 1 2 Device Features CPU Core V850E1 Number of instructions 81 Min
609. x x 47H FFFF F168 Interrupt control register 44 CSHIC R W x x 47H FFFF F16A Interrupt control register 45 CSI2IC R W x x 47H FFFF F16C Interrupt control register 46 SEROIC R W x x 47H FFFF F16E Interrupt control register 47 SROIC R W x x 47H FFFF F170 Interrupt control register 48 STOIC R W x x 47H FFFF F172 Interrupt control register 49 SER1IC R W x x 47H FFFF F174 Interrupt control register 50 SR1IC RW x x 47H FFFF F176 Interrupt control register 51 ST1IC R W x x 47H FFFF F178 Interrupt control register 52 DMAOIC RW x x 47H FFFF F17A Interrupt control register 53 DMA1IC RW x 47H FFFF F17C Interrupt control register 54 DMA2IC RW x x 47H FFFF F17E Interrupt control register 55 DMASIC R W x x 47H FFFF F180 Interrupt control register 56 DOVFIC R W x x 47H FFFF F182 Interrupt control register 57 POOIC R W x x 47H FFFF F184 Interrupt control register 58 5 R W x x 47H FFFF F186 Interrupt control register 59 P10IC R W x x 47H FFFF F188 Interrupt control register 60 P15IC R W x x 47H FFFF F18A Interrupt control register 61 P20IC R W x x 47H FFFF F18C Interrupt control register 62 P21IC R W x x 47H FFFF F18E Interrupt control register 63 Reserved R W x x 47H 78 Preliminary User s Manual U15839EE1VOUMOO Chapter 3 CPU Function Table 3 6 List of Peripheral I O Registers 4 7

V850E/CA2 JUPITER 32-/16-bit Romless Microcontroller Hardware

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